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2024-08-22ARM: dts: aspeed: mtmitchell: Add I2C temperature sensor alias portsChanh Nguyen
Add the I2C alias ports to read temperature sensors via channels of the I2C muxes. Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com> Link: https://lore.kernel.org/r/20240806071806.1666550-3-chanh@os.amperecomputing.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: mtjade, mtmitchell: Add OCP temperature sensorsChanh Nguyen
Define I2C alias ports from I2C Switch 0x70 at BMC I2C5. Add the tmp421 sensors via the I2C alias ports as OCP device temperature sensors. Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com> Link: https://lore.kernel.org/r/20240806071806.1666550-2-chanh@os.amperecomputing.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: catalina: add Meta Catalina BMCPotin Lai
Add linux device tree entry for Meta(Facebook) Catalina compute-tray BMC using AT2600 SoC. Signed-off-by: Potin Lai <potin.lai.pt@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240805-potin-catalina-dts-v7-2-286bfd2ab93b@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: minerva: add host0-ready pinYang Chen
Add host0-ready pin for phosphor-state-manager. Signed-off-by: Yang Chen <yangchen.openbmc@gmail.com> Link: https://lore.kernel.org/r/20240711130501.2900301-2-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: minerva: Add spi-gpioYang Chen
Add spi-gpio for TPM device. Signed-off-by: Yang Chen <yang.chen@quantatw.com> Link: https://lore.kernel.org/r/20240626130332.929534-18-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: minerva: add ltc4287 deviceYang Chen
Enable LTC4287 device on i2c-0. Signed-off-by: Yang Chen <yangchen.openbmc@gmail.com> Link: https://lore.kernel.org/r/20240626130332.929534-17-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: minerva: remove unused power deviceYang Chen
Remove unused power device. Signed-off-by: Yang Chen <yangchen.openbmc@gmail.com> Link: https://lore.kernel.org/r/20240626130332.929534-16-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: minerva: Switch the i2c bus numberYang Chen
Switch the i2c bus number to map the i2c tag according to the hardware design. Signed-off-by: Yang Chen <yang.chen@quantatw.com> Link: https://lore.kernel.org/r/20240626130332.929534-15-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: minerva: revise sgpio line nameYang Chen
Revise the SGPIO naming to mapping the SGPIO from the CPLD. Signed-off-by: Yang Chen <yang.chen@quantatw.com> Link: https://lore.kernel.org/r/20240626130332.929534-14-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: minerva: add power monitor xdp710Yang Chen
Add HSC xdp710 on i2c bus0. Signed-off-by: Yang Chen <yang.chen@quantatw.com> Link: https://lore.kernel.org/r/20240626130332.929534-13-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: minerva: add tmp75 sensorYang Chen
Add tmp75 sensor on the i2c bus connect to each fan board. Signed-off-by: Yang Chen <yang.chen@quantatw.com> Link: https://lore.kernel.org/r/20240626130332.929534-12-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: minerva: enable ehci0 for USBYang Chen
Enable ehci0 for USB. Signed-off-by: Yang Chen <yang.chen@quantatw.com> Link: https://lore.kernel.org/r/20240626130332.929534-11-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: minerva: add linename of two pinsYang Chen
Add linename of two pins for power good/control. Signed-off-by: Yang Chen <yang.chen@quantatw.com> Link: https://lore.kernel.org/r/20240626130332.929534-10-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: minerva: Add adc sensors for fan boardYang Chen
Add ina238 support to read the sensors in front of fans. Signed-off-by: Yang Chen <yang.chen@quantatw.com> Link: https://lore.kernel.org/r/20240626130332.929534-9-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: minerva: Define the LEDs node nameYang Chen
Define the LEDs node name. Signed-off-by: Yang Chen <yang.chen@quantatw.com> Link: https://lore.kernel.org/r/20240626130332.929534-8-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: minerva: remove unused bus and deviceYang Chen
Remove unused bus and device. Signed-off-by: Yang Chen <yang.chen@quantatw.com> Link: https://lore.kernel.org/r/20240626130332.929534-7-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: minerva: enable mdio3Yang Chen
Change usage of I2C bus 11 to mdio3. Signed-off-by: Yang Chen <yang.chen@quantatw.com> Link: https://lore.kernel.org/r/20240626130332.929534-6-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: minerva: change RTC referenceYang Chen
Change the RTC reference from on-chip to externel on i2c bus 9 and address is 0x51. Signed-off-by: Yang Chen <yang.chen@quantatw.com> Link: https://lore.kernel.org/r/20240626130332.929534-5-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: minerva: add eeprom on i2c busYang Chen
Add eeprom on the i2c-9 address 0x50 and i2c-15 address 0x56. Signed-off-by: Yang Chen <yang.chen@quantatw.com> Link: https://lore.kernel.org/r/20240626130332.929534-4-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: minerva: change aliases for uartYang Chen
Change and add aliases name for uart interface. Signed-off-by: Yang Chen <yang.chen@quantatw.com> Link: https://lore.kernel.org/r/20240626130332.929534-3-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-22ARM: dts: aspeed: minerva: change the address of tmp75Yang Chen
Revise the address of tmp75 on I2C bus 1 from 0x48 to 0x4f due to design change. Signed-off-by: Yang Chen <yang.chen@quantatw.com> Link: https://lore.kernel.org/r/20240626130332.929534-2-yangchen.openbmc@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2024-08-20ARM: OMAP1: Remove unused declarations in arch/arm/mach-omap1/pm.hGaosheng Cui
The omap1510_idle_loop_suspend/_sz() and omap1610_idle_loop_suspend/_sz() has been removed since commit feb72f3b313e ("ARM: OMAP1: Remove omap_sram_idle()"), so remove them. Signed-off-by: Gaosheng Cui <cuigaosheng1@huawei.com> Link: https://lore.kernel.org/r/20240813071125.1044697-1-cuigaosheng1@huawei.com Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2024-08-20ARM: dts: bcm-mobile: Split out nodes used by both BCM21664 and BCM23550Artur Weber
The BCM21664 is nearly identical in terms of register layout to the BCM23550. Move the shared nodes into a new file, bcm2166x-common.dtsi, and make both bcm21664.dtsi and bcm23550.dtsi include it. This new common file is based on the former bcm23550.dtsi file, and inherits its licensing. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/r/20240729-bcm21664-common-v2-2-ebc21a89bf63@gmail.com Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
2024-08-20ARM: 9412/1: Convert to arch_cpu_is_hotpluggable()Jinjie Ruan
Convert arm32 to use the arch_cpu_is_hotpluggable() helper rather than arch_register_cpu(). Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2024-08-20ARM: 9411/1: Switch over to GENERIC_CPU_DEVICES using arch_register_cpu()Jinjie Ruan
Currently, almost all architectures have switched to GENERIC_CPU_DEVICES, except for arm32. Also switch over to GENERIC_CPU_DEVICES, and provide an arch_register_cpu() that populates the hotpluggable flag for arm32. The struct cpu in struct cpuinfo_arm is never used directly, remove it to use the one GENERIC_CPU_DEVICES provides. This also has the effect of moving the registration of CPUs from subsys to driver core initialisation, prior to any initcalls running. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2024-08-20ARM: 9410/1: vfp: Use asm volatile in fmrx/fmxr macrosCalvin Owens
Floating point instructions in userspace can crash some arm kernels built with clang/LLD 17.0.6: BUG: unsupported FP instruction in kernel mode FPEXC == 0xc0000780 Internal error: Oops - undefined instruction: 0 [#1] ARM CPU: 0 PID: 196 Comm: vfp-reproducer Not tainted 6.10.0 #1 Hardware name: BCM2835 PC is at vfp_support_entry+0xc8/0x2cc LR is at do_undefinstr+0xa8/0x250 pc : [<c0101d50>] lr : [<c010a80c>] psr: a0000013 sp : dc8d1f68 ip : 60000013 fp : bedea19c r10: ec532b17 r9 : 00000010 r8 : 0044766c r7 : c0000780 r6 : ec532b17 r5 : c1c13800 r4 : dc8d1fb0 r3 : c10072c4 r2 : c0101c88 r1 : ec532b17 r0 : 0044766c Flags: NzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none Control: 00c5387d Table: 0251c008 DAC: 00000051 Register r0 information: non-paged memory Register r1 information: vmalloc memory Register r2 information: non-slab/vmalloc memory Register r3 information: non-slab/vmalloc memory Register r4 information: 2-page vmalloc region Register r5 information: slab kmalloc-cg-2k Register r6 information: vmalloc memory Register r7 information: non-slab/vmalloc memory Register r8 information: non-paged memory Register r9 information: zero-size pointer Register r10 information: vmalloc memory Register r11 information: non-paged memory Register r12 information: non-paged memory Process vfp-reproducer (pid: 196, stack limit = 0x61aaaf8b) Stack: (0xdc8d1f68 to 0xdc8d2000) 1f60: 0000081f b6f69300 0000000f c10073f4 c10072c4 dc8d1fb0 1f80: ec532b17 0c532b17 0044766c b6f9ccd8 00000000 c010a80c 00447670 60000010 1fa0: ffffffff c1c13800 00c5387d c0100f10 b6f68af8 00448fc0 00000000 bedea188 1fc0: bedea314 00000001 00448ebc b6f9d000 00447608 b6f9ccd8 00000000 bedea19c 1fe0: bede9198 bedea188 b6e1061c 0044766c 60000010 ffffffff 00000000 00000000 Call trace: [<c0101d50>] (vfp_support_entry) from [<c010a80c>] (do_undefinstr+0xa8/0x250) [<c010a80c>] (do_undefinstr) from [<c0100f10>] (__und_usr+0x70/0x80) Exception stack(0xdc8d1fb0 to 0xdc8d1ff8) 1fa0: b6f68af8 00448fc0 00000000 bedea188 1fc0: bedea314 00000001 00448ebc b6f9d000 00447608 b6f9ccd8 00000000 bedea19c 1fe0: bede9198 bedea188 b6e1061c 0044766c 60000010 ffffffff Code: 0a000061 e3877202 e594003c e3a09010 (eef16a10) ---[ end trace 0000000000000000 ]--- Kernel panic - not syncing: Fatal exception in interrupt ---[ end Kernel panic - not syncing: Fatal exception in interrupt ]--- This is a minimal userspace reproducer on a Raspberry Pi Zero W: #include <stdio.h> #include <math.h> int main(void) { double v = 1.0; printf("%fn", NAN + *(volatile double *)&v); return 0; } Another way to consistently trigger the oops is: calvin@raspberry-pi-zero-w ~$ python -c "import json" The bug reproduces only when the kernel is built with DYNAMIC_DEBUG=n, because the pr_debug() calls act as barriers even when not activated. This is the output from the same kernel source built with the same compiler and DYNAMIC_DEBUG=y, where the userspace reproducer works as expected: VFP: bounce: trigger ec532b17 fpexc c0000780 VFP: emulate: INST=0xee377b06 SCR=0x00000000 VFP: bounce: trigger eef1fa10 fpexc c0000780 VFP: emulate: INST=0xeeb40b40 SCR=0x00000000 VFP: raising exceptions 30000000 calvin@raspberry-pi-zero-w ~$ ./vfp-reproducer nan Crudely grepping for vmsr/vmrs instructions in the otherwise nearly idential text for vfp_support_entry() makes the problem obvious: vmlinux.llvm.good [0xc0101cb8] <+48>: vmrs r7, fpexc vmlinux.llvm.good [0xc0101cd8] <+80>: vmsr fpexc, r0 vmlinux.llvm.good [0xc0101d20] <+152>: vmsr fpexc, r7 vmlinux.llvm.good [0xc0101d38] <+176>: vmrs r4, fpexc vmlinux.llvm.good [0xc0101d6c] <+228>: vmrs r0, fpscr vmlinux.llvm.good [0xc0101dc4] <+316>: vmsr fpexc, r0 vmlinux.llvm.good [0xc0101dc8] <+320>: vmrs r0, fpsid vmlinux.llvm.good [0xc0101dcc] <+324>: vmrs r6, fpscr vmlinux.llvm.good [0xc0101e10] <+392>: vmrs r10, fpinst vmlinux.llvm.good [0xc0101eb8] <+560>: vmrs r10, fpinst2 vmlinux.llvm.bad [0xc0101cb8] <+48>: vmrs r7, fpexc vmlinux.llvm.bad [0xc0101cd8] <+80>: vmsr fpexc, r0 vmlinux.llvm.bad [0xc0101d20] <+152>: vmsr fpexc, r7 vmlinux.llvm.bad [0xc0101d30] <+168>: vmrs r0, fpscr vmlinux.llvm.bad [0xc0101d50] <+200>: vmrs r6, fpscr <== BOOM! vmlinux.llvm.bad [0xc0101d6c] <+228>: vmsr fpexc, r0 vmlinux.llvm.bad [0xc0101d70] <+232>: vmrs r0, fpsid vmlinux.llvm.bad [0xc0101da4] <+284>: vmrs r10, fpinst vmlinux.llvm.bad [0xc0101df8] <+368>: vmrs r4, fpexc vmlinux.llvm.bad [0xc0101e5c] <+468>: vmrs r10, fpinst2 I think LLVM's reordering is valid as the code is currently written: the compiler doesn't know the instructions have side effects in hardware. Fix by using "asm volatile" in fmxr() and fmrx(), so they cannot be reordered with respect to each other. The original compiler now produces working kernels on my hardware with DYNAMIC_DEBUG=n. This is the relevant piece of the diff of the vfp_support_entry() text, from the original oopsing kernel to a working kernel with this patch: vmrs r0, fpscr tst r0, #4096 bne 0xc0101d48 tst r0, #458752 beq 0xc0101ecc orr r7, r7, #536870912 ldr r0, [r4, #0x3c] mov r9, #16 -vmrs r6, fpscr orr r9, r9, #251658240 add r0, r0, #4 str r0, [r4, #0x3c] mvn r0, #159 sub r0, r0, #-1207959552 and r0, r7, r0 vmsr fpexc, r0 vmrs r0, fpsid +vmrs r6, fpscr and r0, r0, #983040 cmp r0, #65536 bne 0xc0101d88 Fixes: 4708fb041346 ("ARM: vfp: Reimplement VFP exception entry in C code") Signed-off-by: Calvin Owens <calvin@wbinvd.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2024-08-20ARM: 9409/1: mmu: Do not use magic number for TTBCR settingsLinus Walleij
The code in early_paging_init is directly masking off bits 8, 9, 10 and 11 to temporarily disable caching of the translation tables. There is some exlanations in the comment, but use some defines instead of magic numbers so ut becomes more evident what is going on. Change the type of the register to u32 since these are indeed unsigned 32bit registers, and use a temporary variable instead of baking too much into the inline assembly call to increase readability. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
2024-08-20ARM: dts: aspeed: System1: Updates to BMC boardNinad Palsule
- Changed temperature sensor monitor chip from tmp423 to tmp432 Signed-off-by: Ninad Palsule <ninad@linux.ibm.com> Reviewed-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20240605160604.2135840-1-ninad@linux.ibm.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-08-20ARM: dts: aspeed: convert ASRock SPC621D8HM3 NVMEM content to layout syntaxRafał Miłecki
Use cleaner (and non-deprecated) bindings syntax. See commit bd912c991d2e ("dt-bindings: nvmem: layouts: add fixed-layout") for details. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Zev Weiss <zev@bewilderbeest.net> Link: https://lore.kernel.org/r/20240520063044.4885-1-zajec5@gmail.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-08-20ARM: dts: aspeed: Add IBM P11 Fuji BMC systemEddie James
Add the device tree for the new BMC system. The Fuji is a P11 system with eight processors. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ninad Palsule <ninad@linux.ibm.com> Link: https://lore.kernel.org/r/20240522192524.3286237-17-eajames@linux.ibm.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-08-20ARM: dts: aspeed: Add IBM P11 Blueridge 4U BMC systemEddie James
The 4U Blueridge is identical to the Blueridge system but has two extra power supplies. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ninad Palsule <ninad@linux.ibm.com> Link: https://lore.kernel.org/r/20240522192524.3286237-16-eajames@linux.ibm.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-08-20ARM: dts: aspeed: Add IBM P11 Blueridge BMC systemEddie James
Add the device tree for the new BMC system. The Blueridge is a P11 system with four processors. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ninad Palsule <ninad@linux.ibm.com> Link: https://lore.kernel.org/r/20240522192524.3286237-15-eajames@linux.ibm.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-08-20ARM: dts: aspeed: Add IBM P11 FSI devicesEddie James
Add the P11 FSI device tree for use in upcoming BMC systems. Unlike P10, there is no system with only two processors, so only the quad processor FSI layout is necessary. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Ninad Palsule <ninad@linux.ibm.com> Link: https://lore.kernel.org/r/20240522192524.3286237-14-eajames@linux.ibm.com Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
2024-08-19ARM: s3c: remove unused s3c2410_cpu_suspend() declarationGaosheng Cui
The s3c2410_cpu_suspend() has been removed since commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"), so remove it. Signed-off-by: Gaosheng Cui <cuigaosheng1@huawei.com> Link: https://lore.kernel.org/r/20240813105545.1180788-3-cuigaosheng1@huawei.com Fixes: 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-19ARM: s3c: remove unused declarations for s3c6400Gaosheng Cui
These declarations for s3c6400 have been removed since commit 6bac4f78ea3d ("ARM: s3c: remove s3c6400 support"), so remove it. Signed-off-by: Gaosheng Cui <cuigaosheng1@huawei.com> Link: https://lore.kernel.org/r/20240813105545.1180788-2-cuigaosheng1@huawei.com Fixes: 6bac4f78ea3d ("ARM: s3c: remove s3c6400 support") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-19ARM: s3c: Remove unused s3c_init_uart_irqs() declarationGaosheng Cui
The s3c_init_uart_irqs() has not been used since commit 2a8d7bddf273 ("ARM: SAMSUNG: Remove uart irq handling from plaform code"), so remove it. Signed-off-by: Gaosheng Cui <cuigaosheng1@huawei.com> Link: https://lore.kernel.org/r/20240813105037.1178393-1-cuigaosheng1@huawei.com Fixes: 2a8d7bddf273 ("ARM: SAMSUNG: Remove uart irq handling from plaform code") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-08-19ARM: davinci: remove unused cpuidle codeBartosz Golaszewski
The cpuidle driver in mach-davinci is no longer used by anyone. Remove it. Link: https://lore.kernel.org/r/20240813082735.52402-1-brgl@bgdev.pl Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2024-08-19ARM: dts: microchip: sama5d29_curiosity: Add reg_5v to supply PMIC nodesAndrei Simion
Align with the datasheet by adding regulator-5v which supplies each node from the regulator using phandle to regulator-5v through pvin[1-4]-supply and lvin-supply. Co-developed-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Andrei Simion <andrei.simion@microchip.com> Link: https://lore.kernel.org/r/20240812135231.43744-8-andrei.simion@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2024-08-19ARM: dts: microchip: at91-sama5d27_wlsom1: Add reg_5v to supply PMIC nodesAndrei Simion
Align with the datasheet by adding regulator-5v which supplies each node from the regulator using phandle to regulator-5v through pvin[1-4]-supply and lvin-supply. Co-developed-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Andrei Simion <andrei.simion@microchip.com> Link: https://lore.kernel.org/r/20240812135231.43744-7-andrei.simion@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2024-08-19ARM: dts: microchip: at91-sama5d2_icp: Add reg_5v to supply PMIC nodesAndrei Simion
Align with the datasheet by adding regulator-5v which supplies each node from the regulator using phandle to regulator-5v through pvin[1-4]-supply and lvin-supply. Co-developed-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Andrei Simion <andrei.simion@microchip.com> Link: https://lore.kernel.org/r/20240812135231.43744-6-andrei.simion@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2024-08-19ARM: dts: microchip: at91-sama7g54_curiosity: Add reg_5v to supply PMIC nodesAndrei Simion
Align with the datasheet by adding regulator-5v which supplies each node from the regulator using phandle to regulator-5v through pvin[1-4]-supply and lvin-supply. Co-developed-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Andrei Simion <andrei.simion@microchip.com> Link: https://lore.kernel.org/r/20240812135231.43744-5-andrei.simion@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2024-08-19ARM: dts: microchip: at91-sama7g5ek: Add reg_5v to supply PMIC nodesAndrei Simion
Align with the datasheet by adding regulator-5v which supplies each node from the regulator using phandle to regulator-5v through pvin[1-4]-supply and lvin-supply. Co-developed-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Mihai Sain <mihai.sain@microchip.com> Signed-off-by: Andrei Simion <andrei.simion@microchip.com> Link: https://lore.kernel.org/r/20240812135231.43744-4-andrei.simion@microchip.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2024-08-17crypto: arm/aes-neonbs - go back to using aes-arm directlyEric Biggers
In aes-neonbs, instead of going through the crypto API for the parts that the bit-sliced AES code doesn't handle, namely AES-CBC encryption and single-block AES, just call the ARM scalar AES cipher directly. This basically goes back to the original approach that was used before commit b56f5cbc7e08 ("crypto: arm/aes-neonbs - resolve fallback cipher at runtime"). Calling the ARM scalar AES cipher directly is faster, simpler, and avoids any chance of bugs specific to the use of fallback ciphers such as module loading deadlocks which have happened twice. The deadlocks turned out to be fixable in other ways, but there's no need to rely on anything so fragile in the first place. The rationale for the above-mentioned commit was to allow people to choose to use a time-invariant AES implementation for the fallback cipher. There are a couple problems with that rationale, though: - In practice the ARM scalar AES cipher (aes-arm) was used anyway, since it has a higher priority than aes-fixed-time. Users *could* go out of their way to disable or blacklist aes-arm, or to lower its priority using NETLINK_CRYPTO, but very few users customize the crypto API to this extent. Systems with the ARMv8 Crypto Extensions used aes-ce, but the bit-sliced algorithms are irrelevant on such systems anyway. - Since commit 913a3aa07d16 ("crypto: arm/aes - add some hardening against cache-timing attacks"), the ARM scalar AES cipher is partially hardened against cache-timing attacks. It actually works like aes-fixed-time, in that it disables interrupts and prefetches its lookup table. It does use a larger table than aes-fixed-time, but even so, it is not clear that aes-fixed-time is meaningfully more time-invariant than aes-arm. And of course, the real solution for time-invariant AES is to use a CPU that supports AES instructions. Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2024-08-16perf: arm_pmuv3: Add support for Armv9.4 PMU instruction counterRob Herring (Arm)
Armv9.4/8.9 PMU adds optional support for a fixed instruction counter similar to the fixed cycle counter. Support for the feature is indicated in the ID_AA64DFR1_EL1 register PMICNTR field. The counter is not accessible in AArch32. Existing userspace using direct counter access won't know how to handle the fixed instruction counter, so we have to avoid using the counter when user access is requested. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Tested-by: James Clark <james.clark@linaro.org> Link: https://lore.kernel.org/r/20240731-arm-pmu-3-9-icntr-v3-7-280a8d7ff465@kernel.org Signed-off-by: Will Deacon <will@kernel.org>
2024-08-14ARM: dts: qcom: add generic compat string to RPM glink channelsDmitry Baryshkov
Add the generic qcom,smd-rpm compatible to RPM nodes to follow the schema. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240729-fix-smd-rpm-v2-4-0776408a94c5@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14ARM: dts: qcom: msm8226-microsoft-common: Add inertial sensorsRayyan Ansari
Add nodes for the Asahi Kasei AK09911 magnetometer and the Kionix KX022-1020 accelerometer, both of which are connected over i2c2, in the common device tree for msm8x26 Lumias. Moneypenny (Lumia 630) does not have a magnetometer, and so the node is deleted. Tesla's (Lumia 830's) magnetometer is currently unknown. Signed-off-by: Rayyan Ansari <rayyan@ansari.sh> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240714173431.54332-4-rayyan@ansari.sh Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14ARM: dts: qcom: msm8226: Convert APCS usages to mbox interfaceLuca Weiss
Since we now have the apcs set up as a mailbox provider, let's use the interface for all drivers where possible. Signed-off-by: Luca Weiss <luca@lucaweiss.eu> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240619-msm8226-cpufreq-v1-7-85143f5291d1@lucaweiss.eu Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14ARM: dts: qcom: msm8226: Hook up CPU coolingLuca Weiss
Add cooling-maps for the CPU thermal zones so the driver can actually do something when the CPU temperature rises too much. Signed-off-by: Luca Weiss <luca@lucaweiss.eu> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240619-msm8226-cpufreq-v1-6-85143f5291d1@lucaweiss.eu Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14ARM: dts: qcom: msm8226: Add CPU frequency scaling supportLuca Weiss
Add a node for the a7pll with its frequencies. With this we can use the apcs-kpss-global driver for the apcs node and use the apcs to scale the CPU frequency according to the opp-table. At the same time unfortunately we need to provide the gcc node xo_board instead of the XO via rpmcc since otherwise we'll have a circular dependency between apcs, gcc and the rpm. Signed-off-by: Luca Weiss <luca@lucaweiss.eu> Link: https://lore.kernel.org/r/20240619-msm8226-cpufreq-v1-5-85143f5291d1@lucaweiss.eu Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-13ARM: dts: bcm2837/bcm2712: adjust local intc node namesStefan Wahren
After converting the bcm2836-l1-intc DT binding to YAML, the DT schema checks gave warnings like: 'local_intc@40000000' does not match '^interrupt-controller(@[0-9a-f,]+)*$' So fix them accordingly. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Link: https://lore.kernel.org/r/20240812200358.4061-4-wahrenst@gmx.net Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
generated by cgit (git 2.34.1) at 2025-07-18 22:08:28 +0000