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2025-04-23ARM: dts: ls1021a-tqmals1021a: Fix licenseAlexander Stein
With commit 784bdc6f2697c ("ARM: dts: ls1021a: change to use SPDX identifiers") the SoC .dtsi specifies the license using SPDX tags. Fix license according to the ls1021a.dtsi this platform DT files are based on. Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-04-23ARM: dts: imx: Drop redundant CPU "clock-latency"Rob Herring (Arm)
The "clock-latency" property is part of the deprecated opp-v1 binding and is redundant if the opp-v2 table has equal or larger values in any "clock-latency-ns". The OPP tables have values of 150000, so it can be removed. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-04-23crypto: arm/sha512-asm - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: arm/sha512-neon - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Also remove the unnecessary SIMD fallback path. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: arm/sha256-asm - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: arm/sha256-neon - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Also remove the unnecessary SIMD fallback path. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: arm/sha256-ce - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Also remove the unnecessary SIMD fallback path. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: arm/sha1-asm - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: arm/sha1-neon - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Also remove the unnecessary SIMD fallback path. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: arm/sha1-ce - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Also remove the unnecessary SIMD fallback path. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: arm/ghash - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Also switch to the generic export format. Finally remove a couple of stray may_use_simd() calls in gcm. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-23crypto: arm/blake2b - Use API partial block handlingHerbert Xu
Use the Crypto API partial block handling. Also remove the unnecessary SIMD fallback path. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-22ARM: dts: amlogic: meson8b: enable UART RX and TX pull up by defaultMartin Blumenstingl
Some boards have noise on the UART RX line when the UART pins are not connected to another device (such as an USB UART adapter). This can be addressed by using a pull up resistor. Not all boards may provide such a pull up resistor on the PCB so enable the SoC's pull-up on the UART RX and TX pads by default. This matches the default (from u-boot or SoC hardware) state for the pinmux configuration on these pads. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250329185855.854186-3-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-04-22ARM: dts: amlogic: meson8: enable UART RX and TX pull up by defaultMartin Blumenstingl
Some boards have noise on the UART RX line when the UART pins are not connected to another device (such as an USB UART adapter). This can be addressed by using a pull up resistor. Not all boards may provide such a pull up resistor on the PCB so enable the SoC's pull-up on the UART RX and TX pads by default. This matches the default (from u-boot or SoC hardware) state for the pinmux configuration on these pads. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250329185855.854186-2-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-04-22ARM: dts: amlogic: meson8b: fix reference to unknown/untested PWM clockMartin Blumenstingl
Device-tree expects absent clocks to be specified as <0> (instead of using <>). This fixes using the FCLK4/FCLK3 clocks as they are now seen at their correct index (while before they were recognized, but at the correct index - resulting in the hardware using a different clock than what the kernel sees). Fixes: dbf921861985 ("ARM: dts: amlogic: meson8b: switch to the new PWM controller binding") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250420164801.330505-3-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-04-22ARM: dts: amlogic: meson8: fix reference to unknown/untested PWM clockMartin Blumenstingl
Device-tree expects absent clocks to be specified as <0> (instead of using <>). This fixes using the FCLK4/FCLK3 clocks as they are now seen at their correct index (while before they were recognized, but at the correct index - resulting in the hardware using a different clock than what the kernel sees). Fixes: 802cff460aab ("ARM: dts: amlogic: meson8: switch to the new PWM controller binding") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250420164801.330505-2-martin.blumenstingl@googlemail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-04-22ARM: dts: imx51-digi-connectcore-som: Fix MMA7455 compatibleFabio Estevam
The "fsl,mma7455l" compatible string is not documented anywhere. MMA7455L is the exact same device as the MMA7455, with the exception that it is lead-free. Use the documented compatible string. Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-04-22ARM: dts: nxp: Align NAND controller node name with bindingsKrzysztof Kozlowski
Bindings expect NAND controller device nodes to be named "nand-controller". Cc: Fabio Estevam <festevam@gmail.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-04-22ARM: dts: opos6ul: add ksz8081 phy propertiesSébastien Szymanski
Commit c7e73b5051d6 ("ARM: imx: mach-imx6ul: remove 14x14 EVK specific PHY fixup") removed a PHY fixup that setted the clock mode and the LED mode. Make the Ethernet interface work again by doing as advised in the commit's log, set clock mode and the LED mode in the device tree. Fixes: c7e73b5051d6 ("ARM: imx: mach-imx6ul: remove 14x14 EVK specific PHY fixup") Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-04-22ARM: dts: imx: Fix the iim compatible stringFabio Estevam
Per imx-iim.yaml, the compatible string should only contain a single entry. Change it accordingly to fix the following dt-schema warnings: efuse@83f98000: compatible: ['fsl,imx51-iim', 'fsl,imx27-iim', 'syscon'] is too long Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-04-22ARM: dts: imx31/imx6: Use flash as the NOR node nameFabio Estevam
According to mtd-physmap.yaml, 'nor' is not a valid node name. Change it to 'flash' to fix the following dt-schema warning: nor@0,0: $nodename:0: 'nor@0,0' does not match '^(flash|.*sram|nand)(@.*)?$' Signed-off-by: Fabio Estevam <festevam@denx.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-04-20Merge branch 'arm32-for-6.15' into arm64-for-6.16Bjorn Andersson
Changes queued for v6.15 would have had the potential to break bisectability and was therefor not accepted. Merge the whole set towards v6.16, as this is no longer a concern.
2025-04-19crypto: lib/poly1305 - restore ability to remove modulesEric Biggers
Though the module_exit functions are now no-ops, they should still be defined, since otherwise the modules become unremovable. Fixes: 1f81c58279c7 ("crypto: arm/poly1305 - remove redundant shash algorithm") Fixes: f4b1a73aec5c ("crypto: arm64/poly1305 - remove redundant shash algorithm") Fixes: 378a337ab40f ("crypto: powerpc/poly1305 - implement library instead of shash") Fixes: 21969da642a2 ("crypto: x86/poly1305 - remove redundant shash algorithm") Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-19crypto: lib/chacha - restore ability to remove modulesEric Biggers
Though the module_exit functions are now no-ops, they should still be defined, since otherwise the modules become unremovable. Fixes: 08820553f33a ("crypto: arm/chacha - remove the redundant skcipher algorithms") Fixes: 8c28abede16c ("crypto: arm64/chacha - remove the skcipher algorithms") Fixes: f7915484c020 ("crypto: powerpc/chacha - remove the skcipher algorithms") Fixes: ceba0eda8313 ("crypto: riscv/chacha - implement library instead of skcipher") Fixes: 632ab0978f08 ("crypto: x86/chacha - remove the skcipher algorithms") Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-16ARM: davinci: remove support for da830Bartosz Golaszewski
We no longer support any boards with the da830 SoC in mainline linux. Let's remove all bits and pieces related to it. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: David Lechner <dlechner@baylibre.com> Link: https://lore.kernel.org/r/20250407-davinci-remove-da830-v1-1-39f803dd5a14@linaro.org Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
2025-04-16crypto: arm/poly1305 - remove redundant shash algorithmEric Biggers
Since crypto/poly1305.c now registers a poly1305-$(ARCH) shash algorithm that uses the architecture's Poly1305 library functions, individual architectures no longer need to do the same. Therefore, remove the redundant shash algorithm from the arch-specific code and leave just the library functions there. Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-16crypto: poly1305 - centralize the shash wrappers for arch codeEric Biggers
Following the example of the crc32, crc32c, and chacha code, make the crypto subsystem register both generic and architecture-optimized poly1305 shash algorithms, both implemented on top of the appropriate library functions. This eliminates the need for every architecture to implement the same shash glue code. Note that the poly1305 shash requires that the key be prepended to the data, which differs from the library functions where the key is simply a parameter to poly1305_init(). Previously this was handled at a fairly low level, polluting the library code with shash-specific code. Reorganize things so that the shash code handles this quirk itself. Also, to register the architecture-optimized shashes only when architecture-optimized code is actually being used, add a function poly1305_is_arch_optimized() and make each arch implement it. Change each architecture's Poly1305 module_init function to arch_initcall so that the CPU feature detection is guaranteed to run before poly1305_is_arch_optimized() gets called by crypto/poly1305.c. (In cases where poly1305_is_arch_optimized() just returns true unconditionally, using arch_initcall is not strictly needed, but it's still good to be consistent across architectures.) Signed-off-by: Eric Biggers <ebiggers@google.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-16arm: Make simd.h more resilientHerbert Xu
Add missing header inclusions and protect against double inclusion. Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-04-14ARM: dts: qcom: sdx55/sdx65: Fix CPU power-domain-namesRob Herring (Arm)
"rpmhpd" is not documented nor used anywhere. The power-domain is used for performance scaling (cpufreq), so "perf" is the correct name to use. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250410-dt-cpu-schema-v2-7-63d7dc9ddd0a@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-04-14ARM: dts: renesas: r9a06g032-rzn1d400-eb: describe SD card portWolfram Sang
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250410071406.9669-6-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-14ARM: dts: renesas: r9a06g032: Describe SDHCI controllersWolfram Sang
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250410071406.9669-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-14ARM: dts: renesas: r9a06g032-rzn1d400-db: Describe keysWolfram Sang
The keys are connected to the I2C GPIO extender which has the interrupt pin not connected. So, we need to poll. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250328153134.2881-12-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-14ARM: dts: renesas: r9a06g032-rzn1d400-eb: Describe I2C busWolfram Sang
The actual sensor might differ, but all known are LM75B compatible. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250328153134.2881-10-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-14ARM: dts: renesas: r9a06g032-rzn1d400-db: Describe I2C busWolfram Sang
Schematics mention a 24cs64 on the bus, but I definitely have only a 24c64. So, it is only mentioned as a comment. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250328153134.2881-9-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-14ARM: dts: renesas: r9a06g032: Describe I2C controllersWolfram Sang
To match the documentation and schematics, they are numbered from 1 and not from 0. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250328153134.2881-8-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-14ARM: dts: renesas: Add r9a06g032-rzn1d400-eb board device-treeClément Léger
The EB board (Expansion board) supports both RZ/N1D and RZ-N1S. Since this configuration targets only the RZ/N1D, it is named r9a06g032-rzn1d400-eb. It adds support for the 2 additional switch ports (port C and D) that are available on that board. Signed-off-by: Clément Léger <clement.leger@bootlin.com> [Thomas: move the DTS to the Renesas directory, declare the PHY LEDs] Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/20250324-rzn1d400-eb-v4-1-d7ebbbad1918@bootlin.com [wsa: Correct LAN LED nodes] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250411095425.1842-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-11ARM: dts: at91: at91sam9263: fix NAND chip selectsWolfram Sang
NAND did not work on my USB-A9263. I discovered that the offending commit converted the PIO bank for chip selects wrongly, so all A9263 boards need to be fixed. Fixes: 1004a2977bdc ("ARM: dts: at91: Switch to the new NAND bindings") Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20250402210446.5972-2-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-04-11ARM: dts: at91: usb_a9g20: move wrong RTC nodeWolfram Sang
Only the LPW variant has the external RTC. Move it to that board specific DT. As a result, the common include for A9G20 boards can go now. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20250402204856.5197-5-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-04-11ARM: dts: at91: calao_usb: simplify chosen nodeWolfram Sang
All devices use equal parameters in 'chosen'. So, the memory node can be put into the most generic DTSI. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20250402204856.5197-4-wsa+renesas@sang-engineering.com [claudiu.beznea: s/can bet put/can be put/g in commit description] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-04-11ARM: dts: at91: usb_a9260: use 'stdout-path'Wolfram Sang
Do not use the kernel command line for specifying the default serial console. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20250402204856.5197-3-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-04-11ARM: dts: at91: calao_usb: simplify memory nodeWolfram Sang
All devices have 64MB RAM. So, the memory node can be put into the most generic DTSI. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20250402204856.5197-2-wsa+renesas@sang-engineering.com [claudiu.beznea: s/can bet put/can be put/g in commit description] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-04-11ARM: dts: at91: usb_a9263: fix GPIO for Dataflash chip selectWolfram Sang
Dataflash did not work on my board. After checking schematics and using the proper GPIO, it works now. Also, make it active low to avoid: flash@0 enforce active low on GPIO handle Fixes: 2432d201468d ("ARM: at91: dt: usb-a9263: add dataflash support") Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20250404112742.67416-2-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-04-11ARM: dts: at91: usb_a9g20: add SPI EEPROMWolfram Sang
Schematics and board layout indicate that versions with a dataflash instead of an EEPROM might exist. Let's handle that once we have hardware to test. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20250403064336.4846-2-wsa+renesas@sang-engineering.com Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-04-10ARM: omap: pmic-cpcap: do not mess around without CPCAP or OMAP4Andreas Kemnade
The late init call just writes to omap4 registers as soon as CONFIG_MFD_CPCAP is enabled without checking whether the cpcap driver is actually there or the SoC is indeed an OMAP4. Rather do these things only with the right device combination. Fixes booting the BT200 with said configuration enabled and non-factory X-Loader and probably also some surprising behavior on other devices. Fixes: c145649bf262 ("ARM: OMAP2+: Configure voltage controller for cpcap to low-speed") CC: stable@vger.kernel.org Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Reivewed-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20250331144439.769697-1-andreas@kemnade.info Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2025-04-10ARM: dts: nokia n900: remove useless io-channel-cells propertyDavid Heidelberg
This property is irrelevant for the ad5820 DAC, the driver nor the hardware indicate use of channel cells. Fixes: d510d12f26f4 ("ARM: dts: nokia n900: update dts with camera support") Signed-off-by: David Heidelberg <david@ixit.cz> Link: https://lore.kernel.org/r/20250213203208.93316-1-david@ixit.cz Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2025-04-10ARM: omap2plus_defconfig: enable I2C devices of GTA04Andreas Kemnade
Enable I2C devices of GTA04 to get better test coverage when using the defconfig. Until the I2C host driver is fixed, BMG160 module should be blacklisted when booting on the GTA04A5. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Link: https://lore.kernel.org/r/20250228112750.367251-1-andreas@kemnade.info Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2025-04-09arm: multi_v7_defconfig: Drop individual Renesas SoC entriesLad Prabhakar
ARCH_RENESAS is already enabled in multi_v7_defconfig, which ensures that all ARM32 Renesas SoCs are enabled by default. As a result, explicitly listing individual Renesas SoC entries is redundant. Remove these entries to simplify the configuration. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250401090133.68146-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-09arm: shmobile_defconfig: Drop individual Renesas SoC entriesLad Prabhakar
ARCH_RENESAS is already enabled in shmobile_defconfig, which ensures that all ARM32 Renesas SoCs are enabled by default. As a result, explicitly listing individual Renesas SoC entries is redundant. Remove these entries to simplify the configuration. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250401090133.68146-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-04-09ARM: s3c/gpio: use new line value setter callbacksBartosz Golaszewski
struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the driver to using them. Link: https://lore.kernel.org/r/20250407-gpiochip-set-rv-arm-v1-4-9e4a914c7fd4@linaro.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-04-09ARM: scoop/gpio: use new line value setter callbacksBartosz Golaszewski
struct gpio_chip now has callbacks for setting line values that return an integer, allowing to indicate failures. Convert the driver to using them. Link: https://lore.kernel.org/r/20250407-gpiochip-set-rv-arm-v1-3-9e4a914c7fd4@linaro.org Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
generated by cgit (git 2.34.1) at 2025-07-18 02:44:19 +0000