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2023-12-12riscv: dts: thead: Enable BeagleV Ahead eMMC and microSDDrew Fustini
Add emmc node properties for the eMMC device and add sdio0 node properties for the microSD slot. Set the frequency for the sdhci reference clock. Signed-off-by: Drew Fustini <dfustini@baylibre.com> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-12-12riscv: dts: thead: Add TH1520 mmc controllers and sdhci clockDrew Fustini
Add node for the fixed reference clock used for emmc and sdio nodes. Add emmc node for the 1st dwcmshc instance which is typically connected to an eMMC device. Add sdio0 node for the 2nd dwcmshc instance which is typically connected to microSD slot. Add sdio1 node for the 3rd dwcmshc instance which is typically connected to an SDIO WiFi module. The node names are based on Table 1-2 C910/C906 memory map in the TH1520 System User Manual. Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs Signed-off-by: Drew Fustini <dfustini@baylibre.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-12-06riscv: dts: microchip: add the mpfs' system controller qspi & associated flashConor Dooley
The system controller's flash can be accessed via an MSS-exposed QSPI controller sitting, which sits between the mailbox's control & data registers. On Icicle, it has an MT25QL01GBBB8ESF connected to it. The system controller and MSS both have separate QSPI controllers, both of which can access the flash, although the system controller takes priority. Unfortunately, on engineering sample silicon, such as that on Icicle kits, the MSS' QSPI controller cannot write to the flash due to a bug. As a workaround, a QSPI controller can be implemented in the FPGA fabric and the IO routing modified to connect it to the flash in place of the "hard" controller in the MSS. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-11-30Merge patch series "Add Huashan Pi board support"Conor Dooley
Inochi Amaoto <inochiama@outlook.com> says: Huashan Pi board is an embedded development platform based on the CV1812H chip. Add minimal device tree files for this board. Currently, it can boot to a basic shell. NOTE: this series is based on the Jisheng's Milk-V Duo patch. Link: https://en.sophgo.com/product/introduce/huashan.html Link: https://en.sophgo.com/product/introduce/cv181xH.html Link: https://lore.kernel.org/linux-riscv/20231006121449.721-1-jszhang@kernel.org/ Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-11-30riscv: dts: sophgo: add Huashan Pi board device treeInochi Amaoto
Add initial device tree files for the Huashan Pi board. Note: The boot of CV1812H chip needs a rtos firmware for coprocessor to function properly. To make the soc happy, reserved the last 2M memory for the rtos firmware. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Link: https://en.sophgo.com/product/introduce/huashan.html Link: https://en.sophgo.com/product/introduce/cv181xH.html Link: https://github.com/milkv-duo/duo-buildroot-sdk/blob/develop/build/boards/cv181x/cv1812h_wevb_0007a_emmc_huashan/memmap.py#L15 Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-11-30riscv: dts: sophgo: add initial CV1812H SoC device treeInochi Amaoto
Add initial device tree for the CV1812H RISC-V SoC by SOPHGO. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Acked-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-11-30riscv: dts: sophgo: cv18xx: Add gpio devicesInochi Amaoto
Add common GPIO devices for the CV180x and CV181x soc. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-11-30riscv: dts: sophgo: Separate compatible specific for CV1800B socInochi Amaoto
As CV180x and CV181x have the identical layouts, it is OK to use the cv1800b basic device tree for the whole series. For CV1800B soc specific compatible, just move them out of the common file. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Acked-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-11-26riscv: dts: microchip: move timebase-frequency to mpfs.dtsiConor Dooley
The timebase-frequency on PolarFire SoC is not set by an oscillator on the board, but rather by an internal divider, so move the property to mpfs.dtsi. This looks to be copy-pasta from the SiFive Unleashed as the comments in both places were almost identical. In the Unleashed's case this looks to actually be valid, as the clock is provided by a crystal on the PCB. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- CC: Conor Dooley <conor.dooley@microchip.com> CC: Daire McNamara <daire.mcnamara@microchip.com> CC: Rob Herring <robh+dt@kernel.org> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> CC: Paul Walmsley <paul.walmsley@sifive.com> CC: Palmer Dabbelt <palmer@dabbelt.com> CC: linux-riscv@lists.infradead.org CC: devicetree@vger.kernel.org
2023-11-16riscv: dts: sophgo: remove address-cells from intc nodeConor Dooley
A recent submission [1] from Rob has added additionalProperties: false to the interrupt-controller child node of RISC-V cpus, highlighting that the new cv1800b DT has been incorrectly using #address-cells. It has no child nodes, so #address-cells is not needed. Remove it. Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/ [1] Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree") Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-11-13riscv: dts: renesas: Convert isa detection to new propertiesConor Dooley
Convert the RZ/Five devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20231009-smog-gag-3ba67e68126b@wendy Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-11-10Merge tag 'riscv-for-linus-6.7-mw2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull more RISC-V updates from Palmer Dabbelt: - Support for handling misaligned accesses in S-mode - Probing for misaligned access support is now properly cached and handled in parallel - PTDUMP now reflects the SW reserved bits, as well as the PBMT and NAPOT extensions - Performance improvements for TLB flushing - Support for many new relocations in the module loader - Various bug fixes and cleanups * tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (51 commits) riscv: Optimize bitops with Zbb extension riscv: Rearrange hwcap.h and cpufeature.h drivers: perf: Do not broadcast to other cpus when starting a counter drivers: perf: Check find_first_bit() return value of: property: Add fw_devlink support for msi-parent RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs riscv: Fix set_memory_XX() and set_direct_map_XX() by splitting huge linear mappings riscv: Don't use PGD entries for the linear mapping RISC-V: Probe misaligned access speed in parallel RISC-V: Remove __init on unaligned_emulation_finish() RISC-V: Show accurate per-hart isa in /proc/cpuinfo RISC-V: Don't rely on positional structure initialization riscv: Add tests for riscv module loading riscv: Add remaining module relocations riscv: Avoid unaligned access when relocating modules riscv: split cache ops out of dma-noncoherent.c riscv: Improve flush_tlb_kernel_range() riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb riscv: Improve flush_tlb_range() for hugetlb pages riscv: Improve tlb_flush() ...
2023-11-06riscv: boot: Fix creation of loader.binGeert Uytterhoeven
When flashing loader.bin for K210 using kflash:     [ERROR] This is an ELF file and cannot be programmed to flash directly: arch/riscv/boot/loader.bin Before, loader.bin relied on "OBJCOPYFLAGS := -O binary" in the main RISC-V Makefile to create a boot image with the right format. With this removed, the image is now created in the wrong (ELF) format. Fix this by adding an explicit rule. Fixes: 505b02957e74f0c5 ("riscv: Remove duplicate objcopy flag") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Damien Le Moal <dlemoal@kernel.org> Link: https://lore.kernel.org/r/1086025809583809538dfecaa899892218f44e7e.1698159066.git.geert+renesas@glider.be Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-11-01Merge tag 'soc-dt-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds
Pull SoC DT updates from Arnd Bergmann: "There are a couple new SoCs that are supported for the first time: - AMD Pensando Elba is a data processing unit based on Cortex-A72 CPU cores - Sophgo makes RISC-V based chips, and we now support the CV1800B chip used in the milkv-duo board and the massive sg2042 chip in the milkv-pioneer, a 64-core developer workstation. - Qualcomm Snapdragon 720G (sm7125) is a close relative of Snapdragon 7c and gets added with some Xiaomi phones - Renesas gains support for the R8A779F4 (R-Car S4-8) automotive SoC and the RZ/G3S (R9A08G045) embedded SoC. There are also a bunch of newly supported machines that use already supported chips. On the 32-bit side, we have: - USRobotics USR8200 is a NAS/Firewall/router based on the ancient Intel IXP4xx platform - A couple of machines based on the NXP i.MX5 and i.MX6 platforms - One machine each for Allwinner V3s, Aspeed AST2600, Microchip sama5d29 and ST STM32mp157 The other ones all use arm64 cores on chips from allwinner, amlogic, freescale, mediatek, qualcomm and rockchip" * tag 'soc-dt-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (641 commits) ARM: dts: BCM5301X: Set switch ports for Linksys EA9200 ARM: dts: BCM5301X: Set fixed-link for extra Netgear R8000 CPU ports ARM: dts: BCM5301X: Explicitly disable unused switch CPU ports ARM: dts: BCM5301X: Relicense Vivek's code to the GPL 2.0+ / MIT ARM: dts: BCM5301X: Relicense Felix's code to the GPL 2.0+ / MIT ARM: dts: BCM5301X: Set MAC address for Asus RT-AC87U arm64: dts: socionext: add missing cache properties riscv: dts: thead: convert isa detection to new properties arm64: dts: Update cache properties for socionext arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports arm64: dts: ti: k3-am654-icssg2: add ICSSG2 Ethernet support arm64: dts: ti: k3-am65-main: Add ICSSG IEP nodes arm64: dts: ti: k3-am62p5-sk: Updates for SK EVM arm64: dts: ti: k3-am62p: Add nodes for more IPs arm64: dts: rockchip: Add Turing RK1 SoM support dt-bindings: arm: rockchip: Add Turing RK1 dt-bindings: vendor-prefixes: add turing arm64: dts: rockchip: Add DFI to rk3588s arm64: dts: rockchip: Add DFI to rk356x arm64: dts: rockchip: Always enable DFI on rk3399 ...
2023-10-23riscv: dts: thead: convert isa detection to new propertiesConor Dooley
Convert the th1520 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Reviewed-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Guo Ren <guoren@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231022154135.3746-1-jszhang@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-10-18Merge tag 'riscv-dt-for-v6.7' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.7 StarFive: Things are a bit slower for StarFive this window, there's only the addition of audio related DT nodes to speak of here. Generic: The SiFive, StarFive and Microchip devicetrees have had my replacement ISA extension detection properties added. Unfortunately, the old "riscv,isa" property never defined exactly what the extensions it contained meant, and people were want to fill it in incorrectly (and call upstream kernel devs idiots for not doing the same). The new properties have explicit definitions and hopefully will stand up better to some of the variation from RVI. Sophgo: Two new SoCs, one is probably the first of several with up/down tuned variants, that have a pair of T-Head c906 cores and appear aimed at the IP camera, smart <insert whatever> etc markets. They are intended to run in AMP mode, with an RTOS on the less powerful core. The other is far more interesting to kernel developers however, the 64-core SG2042, with more recent c920 cores from T-Head at 2 GHz. For both, support is at a very basic stage - some of the same developers are working on them as other T-Head powered SoCs, but hopefully things will move beyond a basic console boot. The goal is for Chen Wang to take over maintaining the Sophgo support once they have some more experience with the process. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: (22 commits) riscv: dts: starfive: convert isa detection to new properties riscv: dts: sifive: convert isa detection to new properties riscv: dts: microchip: convert isa detection to new properties riscv: dts: sophgo: add Milk-V Duo board device tree riscv: dts: sophgo: add initial CV1800B SoC device tree dt-bindings: riscv: Add Milk-V Duo board compatibles dt-bindings: timer: Add SOPHGO CV1800B clint dt-bindings: interrupt-controller: Add SOPHGO CV1800B plic riscv: defconfig: enable SOPHGO SoC riscv: dts: sophgo: add Milk-V Pioneer board device tree riscv: dts: add initial Sophgo SG2042 SoC device tree dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi dt-bindings: timer: Add Sophgo sg2042 CLINT timer dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC dt-bindings: riscv: Add T-HEAD C920 compatibles dt-bindings: riscv: add sophgo sg2042 bindings dt-bindings: vendor-prefixes: add milkv/sophgo riscv: Add SOPHGO SOC family Kconfig support riscv: dts: starfive: add assigned-clock* to limit frquency riscv: dts: starfive: Add JH7110 PWM-DAC support ... Link: https://lore.kernel.org/r/20231016-filing-payroll-7aca51b8f1a3@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-10-17riscv: dts: thead: set dma-noncoherent to soc busJisheng Zhang
riscv select ARCH_DMA_DEFAULT_COHERENT by default, and th1520 isn't dma coherent, so set dma-noncoherent to reflect this fact. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Tested-by: Drew Fustini <dfustini@baylibre.com> Reviewed-by: Guo Ren <guoren@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-10-16Merge tag 'riscv-dt-for-v6.6-final' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.6-final A single fix for the Starfive VisionFive 2 platform so that chip select for SPI matches the vendor documentation. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.6-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: visionfive 2: correct spi's ss pin riscv: dts: starfive: visionfive 2: Fix uart0 pins sort order riscv: dts: starfive: visionfive 2: Enable usb0 riscv: dts: starfive: fix NOR flash reserved-data partition size Link: https://lore.kernel.org/r/20231015-outmatch-tragedy-228f91d396b5@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-10-15riscv: dts: starfive: convert isa detection to new propertiesConor Dooley
Convert the jh7100 and jh7110 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-15riscv: dts: sifive: convert isa detection to new propertiesConor Dooley
Convert the fu540 and fu740 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-15riscv: dts: microchip: convert isa detection to new propertiesConor Dooley
Convert the PolarFire SoC devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-13Merge tag 'sunxi-dt-for-6.7-1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt - Added V3s nodes for PWM pinctrl, EHCI and OHCI - RISC-V DT cleanups - Added new ISA property and PMU node to Allwinner D1 - Added interconnect to R40 video codec node - New boards: Anbernic RG-Nano, BigTreeTech Pi, BigTreeTech CB1 SOM * tag 'sunxi-dt-for-6.7-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: riscv: dts: allwinner: convert isa detection to new properties ARM: dts: sun8i-r40: Add interconnect to video-codec ARM: dts: sunxi: add support for Anbernic RG-Nano dt-bindings: arm: sunxi: add Anbernic RG-Nano ARM: dts: sun8i: v3s: add EHCI and OHCI to v3s dts arm: dts: sun8i: V3s: Add pinctrl for pwm riscv: dts: allwinner: d1: Add PMU event node arm64: dts: allwinner: h616: Add BigTreeTech Pi support arm64: dts: allwinner: h616: Add BigTreeTech CB1 SoM & boards support dt-bindings: arm: sunxi: Add BigTreeTech boards dt-bindings: vendor-prefixes: Add BigTreeTech arm64: dts: allwinner: h616: Add SID controller node dt-bindings: nvmem: SID: Add binding for H616 SID controller riscv: dts: allwinner: remove address-cells from intc node riscv: dts: use capital "OR" for multiple licenses in SPDX Link: https://lore.kernel.org/r/20231013194203.GA2155816@jernej-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-10-13riscv: dts: allwinner: convert isa detection to new propertiesConor Dooley
Convert the D1 devicetrees to use the new properties "riscv,isa-base" & "riscv,isa-extensions". For compatibility with other projects, "riscv,isa" remains. Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231009-moonlight-gray-92debdc89f30@wendy Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-10-12riscv: dts: starfive: visionfive 2: correct spi's ss pinNam Cao
The ss pin of spi0 is the same as sck pin. According to the visionfive 2 documentation, it should be pin 49 instead of 48. Fixes: 74fb20c8f05d ("riscv: dts: starfive: Add spi node and pins configuration") Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Nam Cao <namcao@linutronix.de> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-07riscv: dts: sophgo: add Milk-V Duo board device treeJisheng Zhang
Milk-V Duo[1] board is an embedded development platform based on the CV1800B chip. Add minimal device tree files for the development board. Support basic uart drivers, so supports booting to a basic shell. Link: https://milkv.io/duo [1] Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-07riscv: dts: sophgo: add initial CV1800B SoC device treeJisheng Zhang
Add initial device tree for the CV1800B RISC-V SoC by SOPHGO. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-07riscv: dts: sophgo: add Milk-V Pioneer board device treeChen Wang
Milk-V Pioneer [1] is a developer motherboard based on SG2042 in a standard mATX form factor. Currently only support booting into console with only uart enabled, other features will be added soon later. Link: https://milkv.io/pioneer [1] Reviewed-by: Guo Ren <guoren@kernel.org> Acked-by: Chao Wei <chao.wei@sophgo.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-07riscv: dts: add initial Sophgo SG2042 SoC device treeChen Wang
Milk-V Pioneer motherboard is powered by SG2042. SG2042 is server grade chip with high performance, low power consumption and high data throughput. Key features: - 64 RISC-V cpu cores - 4 cores per cluster, 16 clusters on chip - More info is available at [1]. Currently only support booting into console with only uart, other features will be added soon later. Link: https://en.sophgo.com/product/introduce/sg2042.html [1] Reviewed-by: Guo Ren <guoren@kernel.org> Acked-by: Chao Wei <chao.wei@sophgo.com> Co-developed-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com> Signed-off-by: Xiaoguang Xing <xiaoguang.xing@sophgo.com> Co-developed-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-10-05riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly ↵Lad Prabhakar
disabled Now that noncoherent dma support for the RZ/Five SoC has been added, enable the IP blocks which were disabled on the RZ/Five SMARC. This adds support for the below peripherals: * Ethernet * DMAC * SDHI * USB * RSPI * SSI Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929000704.53217-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-05riscv: dts: renesas: r9a07g043f: Add dma-noncoherent propertyLad Prabhakar
RZ/Five is a noncoherent SoC so to indicate this add dma-noncoherent property to RZ/Five SoC DTSI. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929000704.53217-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-10-05riscv: dts: renesas: r9a07g043f: Add L2 cache nodeLad Prabhakar
Add L2 cache node for RZ/Five SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230929000704.53217-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2023-09-30riscv: dts: starfive: add assigned-clock* to limit frquencyWilliam Qiu
In JH7110 SoC, we need to go by-pass mode, so we need add the assigned-clock* properties to limit clock frquency. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-09-24riscv: dts: allwinner: d1: Add PMU event nodeInochi Amaoto
D1 has several pmu events supported by opensbi. These events can be used by perf for profiling. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657 Reviewed-by: Guo Ren <guoren@kernel.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/IA1PR20MB49534918FCA69399CE2E0C53BBE0A@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-09-24riscv: dts: allwinner: remove address-cells from intc nodeConor Dooley
A recent submission [1] from Rob has added additionalProperties: false to the interrupt-controller child node of RISC-V cpus, highlighting that the D1 DT has been incorrectly using #address-cells since its introduction. It has no child nodes, so #address-cells is not needed. Remove it. Fixes: 077e5f4f5528 ("riscv: dts: allwinner: Add the D1/D1s SoC devicetree") Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/ [1] Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20230916-saddling-dastardly-8cf6d1263c24@spud Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-09-24riscv: dts: use capital "OR" for multiple licenses in SPDXKrzysztof Kozlowski
Documentation/process/license-rules.rst and checkpatch expect the SPDX identifier syntax for multiple licenses to use capital "OR". Correct it to keep consistent format and avoid copy-paste issues. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230823085238.113642-1-krzysztof.kozlowski@linaro.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-09-13riscv: dts: starfive: Add JH7110 PWM-DAC supportHal Feng
Add PWM-DAC support for StarFive JH7110 SoC. Reviewed-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-09-13riscv: dts: starfive: Add the nodes and pins of I2Srx/I2Stx0/I2Stx1Xingyu Wu
Add I2Srx/I2Stx0/I2Stx1 nodes and pins configuration for the StarFive JH7110 SoC. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Walker Chen <walker.chen@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-09-13riscv: dts: starfive: pinfunc: Fix the pins name of I2STX1Xingyu Wu
These pins are actually I2STX1 clock input, not I2STX0, so their names should be changed. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Walker Chen <walker.chen@starfivetech.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-09-13riscv: dts: starfive: visionfive 2: Fix uart0 pins sort orderHal Feng
Node uart0_pins should be sorted alphabetically. Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-09-13riscv: dts: starfive: visionfive 2: Enable usb0Hal Feng
usb0 was disabled by mistake when merging, so enable it. Fixes: e7c304c0346d ("riscv: dts: starfive: jh7110: add the node and pins configuration for tdm") Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-09-12riscv: dts: starfive: fix NOR flash reserved-data partition sizeAurelien Jarno
The Starfive VisionFive 2 has a 16MiB NOR flash, while the reserved-data partition is declared starting at address 0x600000 with a size of 0x1000000. This causes the kernel to output the following warning: [ 22.156589] mtd: partition "reserved-data" extends beyond the end of device "13010000.spi.0" -- size truncated to 0xa00000 It seems to be a confusion between the size of the partition and the end address. Fix that by specifying the right size. Fixes: 8384087a4223 ("riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC") Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-21Merge tag 'riscv-dt-for-v6.6-pt2' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.6 Part 2 T-Head: Add a second minimal devicetree for the second board using the th1520 SoC, the BeagleV Ahead. As with the Lichee Pi 4a, this is sufficient only for booting to a console, with work on the mmc, clocks and ethernet sides of things under way. A relicense to a dual licence for the existing devicetree files is also done, for good measure. RISC-V Devicetrees for v6.6-pt2 StarFive: Fix the sort order of some nodes that I resolved incorrectly during a merge conflict. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.6-pt2' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: change TH1520 files to dual license riscv: dts: thead: add BeagleV Ahead board device tree dt-bindings: riscv: Add BeagleV Ahead board compatibles riscv: dts: starfive: fix jh7110 qspi sort order Link: https://lore.kernel.org/r/20230819-unwieldy-railing-9bba2b176aa7@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-08-16riscv: dts: change TH1520 files to dual licenseDrew Fustini
Modify the SPDX-License-Identifier for dual license of GPL-2.0 OR MIT. Signed-off-by: Drew Fustini <dfustini@baylibre.com> Acked-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Guo Ren <guoren@kernel.org> Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-16riscv: dts: thead: add BeagleV Ahead board device treeDrew Fustini
The BeagleV Ahead single board computer uses the T-Head TH1520 SoC. Add a minimal device tree to support basic uart/gpio/dmac drivers so that a user can boot to a basic shell. Link: https://beagleboard.org/beaglev-ahead Reviewed-by: Guo Ren <guoren@kernel.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Drew Fustini <dfustini@baylibre.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-15riscv: dts: starfive: fix jh7110 qspi sort orderConor Dooley
Emil pointed out that "13010000 sorts after 12070000". Reshuffle the entries to be in-order. Reported-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-14Merge tag 'sunxi-dt-for-6.6-2' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt - Add D1 CAN controller nodes * tag 'sunxi-dt-for-6.6-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: riscv: dts: allwinner: d1: Add CAN controller nodes Link: https://lore.kernel.org/r/ZNjRV0kJ7v7+DAH5@wens.tw Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-08-14Merge tag 'riscv-dt-for-v6.6' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt RISC-V Devicetrees for v6.6 StarFive: There's only StarFive stuff this time around, starting with some bindings to get clock ID defines out of the binding headers. Getting these (and the syscon bindings) in unblocked a swathe of stuff sitting on the list. Added are: new clock controllers and sycons, ethernet support, thermal sensors, USB and PCIe PHYs, hwrng, mmc and a few more besides for the VisionFive v2. The original VisionFive and BeagleV Starlight got some the thermal sensor support too, as that is supported by the same driver. These changes make the board actually usable with something other than an initramfs. Overlay support by way of the -@ flag set during dtb building, is added also. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: (26 commits) riscv: dts: starfive: jh7110: Fix GMAC configuration riscv: dts: starfive - Add hwrng node for JH7110 SoC riscv: dts: starfive - Add crypto and DMA node for JH7110 riscv: dts: starfive: Add mmc nodes on VisionFive 2 board riscv: dts: starfive: enable DCDC1&ALDO4 node in axp15060 riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC riscv: dts: starfive: jh7110: add the node and pins configuration for tdm riscv: dts: starfive: jh7110: add dma controller node riscv: dts: starfive: Add spi node and pins configuration riscv: dts: starfive: Add USB dts node for JH7110 riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110 riscv: dts: starfive: jh7110: Add temperature sensor node and thermal-zones riscv: dts: starfive: jh7100: Add temperature sensor node and thermal-zones riscv: dts: starfive: visionfive 2: Add configuration of gmac and phy riscv: dts: starfive: jh7110: Add ethernet device nodes riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node riscv: dts: starfive: jh7110: Add syscon nodes riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator ... Link: https://lore.kernel.org/r/20230813-naturist-fragment-ac7d10c453ba@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-08-13riscv: dts: starfive: jh7110: Fix GMAC configurationSamin Guo
Fixed configuration to improve the speed of TCP RX. Before: # iperf3 -s ----------------------------------------------------------- Server listening on 5201 (test #1) ----------------------------------------------------------- Accepted connection from 192.168.1.4, port 47604 [ 5] local 192.168.1.3 port 5201 connected to 192.168.1.4 port 47612 [ ID] Interval Transfer Bitrate [ 5] 0.00-1.00 sec 36.3 MBytes 305 Mbits/sec [ 5] 1.00-2.00 sec 35.6 MBytes 299 Mbits/sec [ 5] 2.00-3.00 sec 36.5 MBytes 306 Mbits/sec [ 5] 3.00-4.00 sec 36.5 MBytes 306 Mbits/sec [ 5] 4.00-5.00 sec 35.7 MBytes 300 Mbits/sec [ 5] 5.00-6.00 sec 35.4 MBytes 297 Mbits/sec [ 5] 6.00-7.00 sec 37.1 MBytes 311 Mbits/sec [ 5] 7.00-8.00 sec 35.6 MBytes 298 Mbits/sec [ 5] 8.00-9.00 sec 36.4 MBytes 305 Mbits/sec [ 5] 9.00-10.00 sec 36.3 MBytes 304 Mbits/sec - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate [ 5] 0.00-10.00 sec 361 MBytes 303 Mbits/sec receiver After: # iperf3 -s ----------------------------------------------------------- Server listening on 5201 (test #1) ----------------------------------------------------------- Accepted connection from 192.168.1.4, port 47710 [ 5] local 192.168.1.3 port 5201 connected to 192.168.1.4 port 47720 [ ID] Interval Transfer Bitrate [ 5] 0.00-1.00 sec 111 MBytes 932 Mbits/sec [ 5] 1.00-2.00 sec 111 MBytes 934 Mbits/sec [ 5] 2.00-3.00 sec 111 MBytes 934 Mbits/sec [ 5] 3.00-4.00 sec 111 MBytes 934 Mbits/sec [ 5] 4.00-5.00 sec 111 MBytes 934 Mbits/sec [ 5] 5.00-6.00 sec 111 MBytes 935 Mbits/sec [ 5] 6.00-7.00 sec 111 MBytes 934 Mbits/sec [ 5] 7.00-8.00 sec 111 MBytes 935 Mbits/sec [ 5] 8.00-9.00 sec 111 MBytes 934 Mbits/sec [ 5] 9.00-10.00 sec 111 MBytes 934 Mbits/sec [ 5] 10.00-10.00 sec 167 KBytes 933 Mbits/sec - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate [ 5] 0.00-10.00 sec 1.09 GBytes 934 Mbits/sec receiver Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Fixes: 1ff166c97972 ("riscv: dts: starfive: jh7110: Add ethernet device nodes") Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> [conor: converted to decimal per emil's request] Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-08-13riscv: dts: allwinner: d1: Add CAN controller nodesJohn Watts
The Allwinner D1, T113 provide two CAN controllers that are variants of the R40 controller. I have tested support for these controllers on two boards: - A Lichee Panel RV 86 Panel running a D1 chip - A Mango Pi MQ Dual running a T113-s3 chip Both of these fully support both CAN controllers. Signed-off-by: John Watts <contact@jookia.org> Link: https://lore.kernel.org/r/20230807191952.2019208-1-contact@jookia.org Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2023-08-12Merge tag 'sunxi-dt-for-6.6-1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt - Add D1 GPADC node - Introduce support for OrangePi Zero 3 SBC - Enable DT overlay support for Allwinner H3 boards * tag 'sunxi-dt-for-6.6-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm: dts: Enable device-tree overlay support for sun8i-h3 pi devices arm64: dts: allwinner: h616: Add OrangePi Zero 3 board support dt-bindings: arm: sunxi: document Orange Pi Zero 3 board name arm64: dts: allwinner: h616: Split Orange Pi Zero 2 DT riscv: dts: allwinner: d1: Add GPADC node Link: https://lore.kernel.org/r/20230806180546.GA127039@jernej-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
generated by cgit (git 2.34.1) at 2025-07-19 02:03:48 +0000