summaryrefslogtreecommitdiff
path: root/arch
AgeCommit message (Collapse)Author
2025-05-14ARM: dts: qcom: apq8064: link LVDS clocksDmitry Baryshkov
Link LVDS clocks to the from MDP4 to the MMCC and back from the MMCC to the MDP4 display controller. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250425-fd-mdp4-lvds-v4-7-6b212160b44c@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-14arm64: dts: qcom: x1e001de-devkit: Enable support for both Type-A USB portsAbel Vesa
The Qualcomm X Elite Devkit has 2 USB-A ports, both connected to the USB multiport controller, each one via a separate NXP PTN3222 eUSB2-to-USB2 redriver to the eUSB2 PHY for High-Speed support, with a dedicated QMP PHY for SuperSpeed support. Describe each redriver and then enable each pair of PHYs and the USB controller itself, in order to enable support for the 2 USB-A ports. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250324-x1e001de-devkit-dts-enable-usb-a-ports-v1-1-81153b2d1edf@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-14arm64: dts: qcom: Add industrial mezzanine support for qcs6490-rb3gen2Nirmesh Kumar Singh
Add DTS support for Qualcomm qcs6490-rb3gen2 industrial mezzanine board. Signed-off-by: Sahil Chandna <quic_chandna@quicinc.com> Signed-off-by: Nirmesh Kumar Singh <quic_nkumarsi@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250323123333.1622860-1-quic_nkumarsi@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-14arm64: dts: qcom: x1e80100-hp-omnibook-x14: Enable SMB2360 0 and 1Juerg Haefliger
Commit d37e2646c8a5 ("arm64: dts: qcom: x1e80100-pmics: Enable all SMB2360 separately") disables all SMB2360s and let the board DTS explicitly enable them. The HP OmniBook DTS is from before this change and is missing the explicit enabling. Add that to get all USB root ports. Fixes: 6f18b8d4142c ("arm64: dts: qcom: x1e80100-hp-x14: dt for HP Omnibook X Laptop 14") Cc: stable@vger.kernel.org # 6.14 Signed-off-by: Juerg Haefliger <juerg.haefliger@canonical.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20250319160509.1812805-1-juerg.haefliger@canonical.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-14ARM: dts: qcom-msm8960: add missing clocks to the timer nodeRudraksha Gupta
In order to fix DT schema warning and describe hardware properly, add missing sleep clock to the timer node. Solved by Dmitry Baryshkov on the APQ8064 SoC Link: https://lore.kernel.org/all/20250318-fix-nexus-4-v2-6-bcedd1406790@oss.qualcomm.com/ Signed-off-by: Rudraksha Gupta <guptarud@gmail.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250318-expressatt-solve-dts-errors-v1-1-14012a4bc315@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-14arm64: dts: qcom: ipq5018: enable the download mode supportGeorge Moussalem
Enable support for download mode to collect RAM dumps in case of a system crash, allowing post mortem analysis. Signed-off-by: George Moussalem <george.moussalem@outlook.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250512-ipq5018-syscon-v1-2-eb1ad2414c3c@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-14arm64: dts: qcom: msm8998-lenovo-miix-630: add Venus nodeDmitry Baryshkov
Enable Venus on Lenovo Miix 630 and specify corresponding firmware file. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Link: https://lore.kernel.org/r/20250425-miix-630-venus-v2-1-cdfca385a0c8@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-14arm64: dts: qcom: ipq5018: Enable PCIeNitheesh Sekar
Enable the PCIe controller and PHY nodes for RDP 432-c2. Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://lore.kernel.org/r/20250514-ipq5018-pcie-v10-2-5b42a8eff7ea@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-14arm64: dts: qcom: ipq5018: Add PCIe related nodesNitheesh Sekar
Add phy and controller nodes for a 2-lane Gen2 and a 1-lane Gen2 PCIe bus. IPQ5018 has 8 MSI SPI interrupts and one global interrupt. NOTE: the PCIe controller supports gen3, yet the phy is limited to gen2. Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> Signed-off-by: Sricharan R <quic_srichara@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://lore.kernel.org/r/20250514-ipq5018-pcie-v10-1-5b42a8eff7ea@outlook.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-14arm64: dts: qcom: sm8350: Fix typo in pil_camera_mem nodeAlok Tiwari
There is a typo in sm8350.dts where the node label mmeory@85200000 should be memory@85200000. This patch corrects the typo for clarity and consistency. Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC") Cc: stable@vger.kernel.org Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com> Link: https://lore.kernel.org/r/20250514114656.2307828-1-alok.a.tiwari@oracle.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-14arm64: dts: qcom: x1e80100-romulus: Enable DP over Type-CKonrad Dybcio
Both ports seem to work, just like on other X1E laptops. Tested with a Type-C-to-HDMI2.0 dock (translating into up to 2 DP lanes worth of bandwidth). Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250514-topic-romu_dp-v1-1-6242d6acb5e5@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-05-14Merge tag 'soc-fixes-6.15-2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC fixes from Arnd Bergmann: "These all address issues in devicetree files: - The Rockchip rk3588j are now limited the same way as the vendor kernel, to allow room for the industrial-grade temperature ranges. - Seven more Rockchip fixes address minor issues with specific boards - Invalid clk controller references in multiple amlogic chips, plus one accidentally disabled audio on clock - Two devicetree fixes for i.MX8MP boards, both for incorrect regulator settings - A power domain change for apple laptop touchbar, fixing suspend/resume problems - An incorrect DMA controller setting for sophgo cv18xx chips" * tag 'soc-fixes-6.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: arm64: dts: amazon: Fix simple-bus node name schema warnings MAINTAINERS: delete email for Shiraz Hashim arm64: dts: imx8mp-var-som: Fix LDO5 shutdown causing SD card timeout arm64: dts: imx8mp: use 800MHz NoC OPP for nominal drive mode arm64: dts: amlogic: dreambox: fix missing clkc_audio node riscv: dts: sophgo: fix DMA data-width configuration for CV18xx arm64: dts: rockchip: fix Sige5 RTC interrupt pin arm64: dts: rockchip: Assign RT5616 MCLK rate on rk3588-friendlyelec-cm3588 arm64: dts: rockchip: Align wifi node name with bindings in CB2 arm64: dts: amlogic: g12: fix reference to unknown/untested PWM clock arm64: dts: amlogic: gx: fix reference to unknown/untested PWM clock ARM: dts: amlogic: meson8b: fix reference to unknown/untested PWM clock ARM: dts: amlogic: meson8: fix reference to unknown/untested PWM clock arm64: dts: apple: touchbar: Mark ps_dispdfr_be as always-on mailmap: Update email for Asahi Lina arm64: dts: rockchip: Fix mmc-pwrseq clock name on rock-pi-4 arm64: dts: rockchip: Use "regulator-fixed" for btreg on px30-engicam for vcc3v3-btreg arm64: dts: rockchip: Add pinmuxing for eMMC on QNAP TS433 arm64: dts: rockchip: Remove overdrive-mode OPPs from RK3588J SoC dtsi arm64: dts: rockchip: Allow Turing RK1 cooling fan to spin down
2025-05-14ARM: dts: davinci: da850-evm: Increase fifo thresholdAdam Ford
When operating at low speeds, the display may throw an underflow error and the display itself goes blank. Increasing the fifo-th value appears to correct this problem and the display can now operate when the system is operating at speeds as low as 100MHz. Signed-off-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/20250504102959.81830-1-aford173@gmail.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
2025-05-14LoongArch: uprobes: Remove redundant code about resume_eraTiezhu Yang
arch_uprobe_skip_sstep() returns true if instruction was emulated, that is to say, there is no need to single step for the emulated instructions. regs->csr_era will point to the destination address directly after the exception, so the resume_era related code is redundant, just remove them. Cc: stable@vger.kernel.org Fixes: 19bc6cb64092 ("LoongArch: Add uprobes support") Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-05-14LoongArch: uprobes: Remove user_{en,dis}able_single_step()Tiezhu Yang
When executing the "perf probe" and "perf stat" test cases about some cryptographic algorithm, the output shows that "Trace/breakpoint trap". This is because it uses the software singlestep breakpoint for uprobes on LoongArch, and no need to use the hardware singlestep. So just remove the related function call to user_{en,dis}able_single_step() for uprobes on LoongArch. How to reproduce: Please make sure CONFIG_UPROBE_EVENTS is set and openssl supports sm2 algorithm, then execute the following command. cd tools/perf && make ./perf probe -x /usr/lib64/libcrypto.so BN_mod_mul_montgomery ./perf stat -e probe_libcrypto:BN_mod_mul_montgomery openssl speed sm2 Cc: stable@vger.kernel.org Fixes: 19bc6cb64092 ("LoongArch: Add uprobes support") Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-05-14LoongArch: Save and restore CSR.CNTC for hibernationHuacai Chen
Save and restore CSR.CNTC for hibernation which is similar to suspend. For host this is unnecessary because sched clock is ensured continuous, but for kvm guest sched clock isn't enough because rdtime.d should also be continuous. Host::rdtime.d = Host::CSR.CNTC + counter Guest::rdtime.d = Host::CSR.CNTC + Host::CSR.GCNTC + Guest::CSR.CNTC + counter so, Guest::rdtime.d = Host::rdtime.d + Host::CSR.GCNTC + Guest::CSR.CNTC To ensure Guest::rdtime.d continuous, Host::rdtime.d should be at first continuous, while Host::CSR.GCNTC / Guest::CSR.CNTC is maintained by KVM. Cc: stable@vger.kernel.org Signed-off-by: Xianglai Li <lixianglai@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-05-14LoongArch: Move __arch_cpu_idle() to .cpuidle.text sectionHuacai Chen
Now arch_cpu_idle() is annotated with __cpuidle which means it is in the .cpuidle.text section, but __arch_cpu_idle() isn't. Thus, fix the missing .cpuidle.text section assignment for __arch_cpu_idle() in order to correct backtracing with nmi_backtrace(). The principle is similar to the commit 97c8580e85cf81c ("MIPS: Annotate cpu_wait implementations with __cpuidle") Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-05-14LoongArch: Fix MAX_REG_OFFSET calculationHuacai Chen
Fix MAX_REG_OFFSET calculation, make it point to the last register in 'struct pt_regs' and not to the marker itself, which could allow regs_get_register() to return an invalid offset. Cc: stable@vger.kernel.org Fixes: 803b0fc5c3f2baa6e5 ("LoongArch: Add process management") Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-05-14LoongArch: Prevent cond_resched() occurring within kernel-fpuTianyang Zhang
When CONFIG_PREEMPT_COUNT is not configured (i.e. CONFIG_PREEMPT_NONE/ CONFIG_PREEMPT_VOLUNTARY), preempt_disable() / preempt_enable() merely acts as a barrier(). However, in these cases cond_resched() can still trigger a context switch and modify the CSR.EUEN, resulting in do_fpu() exception being activated within the kernel-fpu critical sections, as demonstrated in the following path: dcn32_calculate_wm_and_dlg() DC_FP_START() dcn32_calculate_wm_and_dlg_fpu() dcn32_find_dummy_latency_index_for_fw_based_mclk_switch() dcn32_internal_validate_bw() dcn32_enable_phantom_stream() dc_create_stream_for_sink() kzalloc(GFP_KERNEL) __kmem_cache_alloc_node() __cond_resched() DC_FP_END() This patch is similar to commit d02198550423a0b (x86/fpu: Improve crypto performance by making kernel-mode FPU reliably usable in softirqs). It uses local_bh_disable() instead of preempt_disable() for non-RT kernels so it can avoid the cond_resched() issue, and also extend the kernel-fpu application scenarios to the softirq context. Cc: stable@vger.kernel.org Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-05-14arm64: dts: allwinner: a100: add Liontron H-A133L board supportAndre Przywara
The H-A133L board is an industrial development board made by Liontron. It contains a number of dedicated JST connectors, to connect external peripherals. It features: - Allwinner A133 SoC (4 * Arm Cortex-A53 cores at up to 1.6 GHz) - 1 GiB, 2 GiB or 4 GiB of LPDDR4 DRAM - between 16 and 128 GiB eMMC flash - AXP707 PMIC (compatible to AXP803) - 100 Mbit/s RJ45 Ethernet socket, using an JLSemi JL1101 PHY - XR829 WIFI+Bluetooth chip - 2 * USB 2.0 USB-A ports, plus three sets of USB pins on connectors (connected via a USB hub connected to USB1 on the SoC) - microSD card slot - 3.5mm A/V port - 12V power supply - connectors for an LVDS or MIPI-DSI panel Add the devicetree describing the board's peripherals and their connections. Despite being a devboard, the manufacturer does not publish a schematic (I asked), so the PMIC rail assignments were bases on BSP dumps, educated guesses and some experimentation. Dropping the always-on property from any of the rails carrying it will make the board hang as soon as the kernel turns off unused regulators. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Link: https://patch.msgid.link/20250505164729.18175-4-andre.przywara@arm.com [wens@csie.org: fix property in &usbphy; fix comment typo in &usb_otg] Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-05-14arm64: defconfig: Enable configs for MediaTek Genio EVK boardsNícolas F. R. A. Prado
Enable the missing configs to get all devices on the MediaTek Genio 1200, 700, 510 and 350 EVK boards probing, as indicated by the DT kselftest. This includes support for: Genio 1200/700/510/350: * MT6359/MT6357 PMICs Auxiliary ADC Genio 1200/700/510: * MDP3 (video scaling and color space conversion IP block) * ITE IT5205 Type-C USB Alternate Mode Passive MUX * Himax HX8279 controller based KD070FHFID078 DSI panel Genio 700/510: * Richtek RT1715 USB Type-C PD Controller Genio 1200: * MediaTek PCIe PHY * Mediatek MT6360 USB Type-C Port Controller Genio 350: * STARTEK KD070FHFID015 DSI panel * MediaTek UART DMA controller (APDMA) Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250513-genio-defconfig-v1-1-c3862f91b6b2@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-14arm64: defconfig: mediatek: enable PHY driversVignesh Raman
The mediatek display driver fails to probe on mt8173-elm-hana and mt8183-kukui-jacuzzi-juniper-sku16 in v6.14-rc4 due to missing PHY configurations. Commit 924d66011f24 ("drm/mediatek: stop selecting foreign drivers") stopped selecting the MediaTek PHY drivers, requiring them to be explicitly enabled in defconfig. Enable the following PHY drivers for MediaTek platforms: CONFIG_PHY_MTK_HDMI=m for HDMI display CONFIG_PHY_MTK_MIPI_DSI=m for DSI display CONFIG_PHY_MTK_DP=m for DP display Fixes: 924d66011f24 ("drm/mediatek: stop selecting foreign drivers") Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com> Link: https://lore.kernel.org/r/20250512131933.1247830-1-vignesh.raman@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
2025-05-14arm64/mm: Permit lazy_mmu_mode to be nestedRyan Roberts
lazy_mmu_mode is not supposed to permit nesting. But in practice this does happen with CONFIG_DEBUG_PAGEALLOC, where a page allocation inside a lazy_mmu_mode section (such as zap_pte_range()) will change permissions on the linear map with apply_to_page_range(), which re-enters lazy_mmu_mode (see stack trace below). The warning checking that nesting was not happening was previously being triggered due to this. So let's relax by removing the warning and tolerate nesting in the arm64 implementation. The first (inner) call to arch_leave_lazy_mmu_mode() will flush and clear the flag such that the remainder of the work in the outer nest behaves as if outside of lazy mmu mode. This is safe and keeps tracking simple. Code review suggests powerpc deals with this issue in the same way. ------------[ cut here ]------------ WARNING: CPU: 6 PID: 1 at arch/arm64/include/asm/pgtable.h:89 __apply_to_page_range+0x85c/0x9f8 Modules linked in: ip_tables x_tables ipv6 CPU: 6 UID: 0 PID: 1 Comm: systemd Not tainted 6.15.0-rc5-00075-g676795fe9cf6 #1 PREEMPT Hardware name: QEMU KVM Virtual Machine, BIOS 2024.08-4 10/25/2024 pstate: 40400005 (nZcv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) pc : __apply_to_page_range+0x85c/0x9f8 lr : __apply_to_page_range+0x2b4/0x9f8 sp : ffff80008009b3c0 x29: ffff80008009b460 x28: ffff0000c43a3000 x27: ffff0001ff62b108 x26: ffff0000c43a4000 x25: 0000000000000001 x24: 0010000000000001 x23: ffffbf24c9c209c0 x22: ffff80008009b4d0 x21: ffffbf24c74a3b20 x20: ffff0000c43a3000 x19: ffff0001ff609d18 x18: 0000000000000001 x17: 0000000000000000 x16: 0000000000000000 x15: 0000000000000003 x14: 0000000000000028 x13: ffffbf24c97c1000 x12: ffff0000c43a3fff x11: ffffbf24cacc9a70 x10: ffff0000c43a3fff x9 : ffff0001fffff018 x8 : 0000000000000012 x7 : ffff0000c43a4000 x6 : ffff0000c43a4000 x5 : ffffbf24c9c209c0 x4 : ffff0000c43a3fff x3 : ffff0001ff609000 x2 : 0000000000000d18 x1 : ffff0000c03e8000 x0 : 0000000080000000 Call trace: __apply_to_page_range+0x85c/0x9f8 (P) apply_to_page_range+0x14/0x20 set_memory_valid+0x5c/0xd8 __kernel_map_pages+0x84/0xc0 get_page_from_freelist+0x1110/0x1340 __alloc_frozen_pages_noprof+0x114/0x1178 alloc_pages_mpol+0xb8/0x1d0 alloc_frozen_pages_noprof+0x48/0xc0 alloc_pages_noprof+0x10/0x60 get_free_pages_noprof+0x14/0x90 __tlb_remove_folio_pages_size.isra.0+0xe4/0x140 __tlb_remove_folio_pages+0x10/0x20 unmap_page_range+0xa1c/0x14c0 unmap_single_vma.isra.0+0x48/0x90 unmap_vmas+0xe0/0x200 vms_clear_ptes+0xf4/0x140 vms_complete_munmap_vmas+0x7c/0x208 do_vmi_align_munmap+0x180/0x1a8 do_vmi_munmap+0xac/0x188 __vm_munmap+0xe0/0x1e0 __arm64_sys_munmap+0x20/0x38 invoke_syscall+0x48/0x104 el0_svc_common.constprop.0+0x40/0xe0 do_el0_svc+0x1c/0x28 el0_svc+0x4c/0x16c el0t_64_sync_handler+0x10c/0x140 el0t_64_sync+0x198/0x19c irq event stamp: 281312 hardirqs last enabled at (281311): [<ffffbf24c780fd04>] bad_range+0x164/0x1c0 hardirqs last disabled at (281312): [<ffffbf24c89c4550>] el1_dbg+0x24/0x98 softirqs last enabled at (281054): [<ffffbf24c752d99c>] handle_softirqs+0x4cc/0x518 softirqs last disabled at (281019): [<ffffbf24c7450694>] __do_softirq+0x14/0x20 ---[ end trace 0000000000000000 ]--- Fixes: 5fdd05efa1cd ("arm64/mm: Batch barriers when updating kernel mappings") Reported-by: Catalin Marinas <catalin.marinas@arm.com> Closes: https://lore.kernel.org/linux-arm-kernel/aCH0TLRQslXHin5Q@arm.com/ Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20250512150333.5589-1-ryan.roberts@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2025-05-14arm64/mm: Disable barrier batching in interrupt contextsRyan Roberts
Commit 5fdd05efa1cd ("arm64/mm: Batch barriers when updating kernel mappings") enabled arm64 kernels to track "lazy mmu mode" using TIF flags in order to defer barriers until exiting the mode. At the same time, it added warnings to check that pte manipulations were never performed in interrupt context, because the tracking implementation could not deal with nesting. But it turns out that some debug features (e.g. KFENCE, DEBUG_PAGEALLOC) do manipulate ptes in softirq context, which triggered the warnings. So let's take the simplest and safest route and disable the batching optimization in interrupt contexts. This makes these users no worse off than prior to the optimization. Additionally the known offenders are debug features that only manipulate a single PTE, so there is no performance gain anyway. There may be some obscure case of encrypted/decrypted DMA with the dma_free_coherent called from an interrupt context, but again, this is no worse off than prior to the commit. Some options for supporting nesting were considered, but there is a difficult to solve problem if any code manipulates ptes within interrupt context but *outside of* a lazy mmu region. If this case exists, the code would expect the updates to be immediate, but because the task context may have already been in lazy mmu mode, the updates would be deferred, which could cause incorrect behaviour. This problem is avoided by always ensuring updates within interrupt context are immediate. Fixes: 5fdd05efa1cd ("arm64/mm: Batch barriers when updating kernel mappings") Reported-by: syzbot+5c0d9392e042f41d45c5@syzkaller.appspotmail.com Closes: https://lore.kernel.org/linux-arm-kernel/681f2a09.050a0220.f2294.0006.GAE@google.com/ Signed-off-by: Ryan Roberts <ryan.roberts@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20250512102242.4156463-1-ryan.roberts@arm.com Signed-off-by: Will Deacon <will@kernel.org>
2025-05-14riscv: dts: renesas: Add specific RZ/Five cache compatibleConor Dooley
When the binding was originally written, it was assumed that all ax45mp-caches had the same properties etc. This has turned out to be incorrect, as the QiLai SoC has a different number of cache-sets. Add a specific compatible for the RZ/Five for property enforcement and in case there turns out to be additional differences between these implementations of the cache controller. Acked-by: Ben Zong-You Xie <ben717@andestech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/20250512-sphere-plenty-8ce4cd772745@spud Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-14arm64: dts: renesas: sparrow-hawk: Disable dtc spi_bus_bridge checkGeert Uytterhoeven
make dtbs: arch/arm64/boot/dts/renesas/r8a779g0.dtsi:1269.24-1283.5: Warning (spi_bus_bridge): /soc/spi@e6ea0000: incorrect #address-cells for SPI bus also defined at arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts:471.9-486.3 arch/arm64/boot/dts/renesas/r8a779g0.dtsi:1269.24-1283.5: Warning (spi_bus_bridge): /soc/spi@e6ea0000: incorrect #size-cells for SPI bus also defined at arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts:471.9-486.3 arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dtb: Warning (spi_bus_reg): Failed prerequisite 'spi_bus_bridge' The Sparrow Hawk uses the MSIOF module in I2S mode instead of SPI mode, triggering a conflict between the SPI bus bindings and dtc: - Serial engines that can be SPI controllers must use "spi" as their node names, - Dtc assumes nodes named "spi" are always SPI controllers. Fix this by disabling this specific warning for this board. Fixes: ca764d5321a2cee7 ("arm64: dts: renesas: sparrow-hawk: Add MSIOF Sound support") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Closes: https://lore.kernel.org/20250506192033.77338015@canb.auug.org.au Suggested-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/fbad3581f297d5b95a3b2813bbae7dba25a523fd.1747039399.git.geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-05-14arm64: dts: marvell: uDPU: define pinctrl state for alarm LEDsGabor Juhos
The two alarm LEDs of on the uDPU board are stopped working since commit 78efa53e715e ("leds: Init leds class earlier"). The LEDs are driven by the GPIO{15,16} pins of the North Bridge GPIO controller. These pins are part of the 'spi_quad' pin group for which the 'spi' function is selected via the default pinctrl state of the 'spi' node. This is wrong however, since in order to allow controlling the LEDs, the pins should use the 'gpio' function. Before the commit mentined above, the 'spi' function is selected first by the pinctrl core before probing the spi driver, but then it gets overridden to 'gpio' implicitly via the devm_gpiod_get_index_optional() call from the 'leds-gpio' driver. After the commit, the LED subsystem gets initialized before the SPI subsystem, so the function of the pin group remains 'spi' which in turn prevents controlling of the LEDs. Despite the change of the initialization order, the root cause is that the pinctrl state definition is wrong since its initial commit 0d45062cfc89 ("arm64: dts: marvell: Add device tree for uDPU board"), To fix the problem, override the function in the 'spi_quad_pins' node to 'gpio' and move the pinctrl state definition from the 'spi' node into the 'leds' node. Cc: stable@vger.kernel.org # needs adjustment for < 6.1 Fixes: 0d45062cfc89 ("arm64: dts: marvell: Add device tree for uDPU board") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2025-05-14crypto: powerpc/poly1305 - Add SIMD fallbackHerbert Xu
Add a SIMD fallback path for poly1305-p10 by converting the 2^64 based hash state into a 2^44 base. In order to ensure that the generic fallback is actually 2^44, add ARCH_SUPPORTS_INT128 to powerpc and make poly1305-p10 depend on it. Fixes: ba8f8624fde2 ("crypto: poly1305-p10 - Glue code for optmized Poly1305 implementation for ppc64le") Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-05-14KVM: arm64: Don't feed uninitialised data to HCR_EL2Marc Zyngier
When the guest executes an AT S1E{0,1} from EL2, and that its HCR_EL2.{E2H,TGE}=={1,1}, then this is a pure S1 translation that doesn't involve a guest-supplied S2, and the full S1 context is already in place. This allows us to take a shortcut and avoid save/restoring a bunch of registers. However, we set HCR_EL2 to a value suitable for the use of AT in guest context. And we do so by using the value that we saved. Or not. In the case described above, we restore whatever junk was on the stack, and carry on with it until the next entry. Needless to say, this is completely broken. But this also triggers the realisation that saving HCR_EL2 is a bit pointless. We are always in host context at the point where reach this code, and what we program to enter the guest is a known value (vcpu->arch.hcr_el2). Drop the pointless save/restore, and wrap the AT operations with writes that switch between guest and host values for HCR_EL2. Reported-by: D Scott Phillips <scott@os.amperecomputing.com> Link: https://lore.kernel.org/r/20250422122612.2675672-4-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-05-14KVM: arm64: Teach address translation about access faultsMarc Zyngier
It appears that our S1 PTW is completely oblivious of access faults. Teach the S1 translation code about it. Reviewed-by: Joey Gouly <joey.gouly@arm.com> Link: https://lore.kernel.org/r/20250422122612.2675672-3-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-05-14KVM: arm64: Fix PAR_EL1.{PTW,S} reporting on AT S1E*Marc Zyngier
When an AT S1E* operation fails, we need to report whether the translation failed at S2, and whether this was during a S1 PTW. But these two bits are not independent. PAR_EL1.PTW can only be set of PAR_EL1.S is also set, and PAR_EL1.S can only be set on its own when the full S1 PTW has succeeded, but that the access itself is reporting a fault at S2. As a result, it makes no sense to carry both ptw and s2 as parameters to fail_s1_walk(), and they should be unified. This fixes a number of cases where we were reporting PTW=1 *and* S=0, which makes no sense. Link: https://lore.kernel.org/r/20250422122612.2675672-2-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-05-14ARM: dts: stm32: add initial support for stm32mp157-ultra-fly-sbc boardGoran Rađenović
Add support for Ultratronik's stm32mp157c fly board. This board embeds a STM32MP157c SOC and 1GB of DDR3. Several connections are available on this boards: 2*USB2.0, 1*USB2.0 MiniUSB, Debug UART, 1*UART, 1*USART, SDcard, RJ45, ... This patch enables basic support for a kernel boot - SD-card or eMMC. Signed-off-by: Goran Rađenović <goran.radni@gmail.com> Link: https://lore.kernel.org/r/20250508143818.2574558-5-goran.radni@gmail.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14arm64: dts: st: use lptimer3 as tick broadcast source on stm32mp257f-ev1Fabrice Gasnier
During the low power modes the generic ARM timer is deactivated, so the the tick broadcast is used, based on LPTIMER3 which is clocked by LSE on STMicroelectronics boards. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14arm64: dts: st: add low-power timer nodes on stm32mp251Fabrice Gasnier
Add low-power timer (LPTimer) support on STM32MP25 SoC. The full feature set is implemented in LPTIM1/2/3/4. LPTIM5 supports a smaller set of features (no capture/compare) channel. Still, LPTIM5 can be used as single PWM, counter, trigger or timer. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250429125133.1574167-7-fabrice.gasnier@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14arm64: defconfig: enable STM32 LP timer clockevent driverFabrice Gasnier
Enable the STM32 LP timer MFD core and clockevent drivers used on STM32MP257F-EV1 board, for PSCI OSI. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250429125133.1574167-6-fabrice.gasnier@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14arm64: dts: st: Add SPI NOR flash support on stm32mp257f-ev1 boardPatrice Chotard
Add SPI NOR flash nor support on stm32mp257f-ev1 board. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20250512-upstream_omm_ospi_dts-v10-3-fca0fbe6d10a@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14arm64: dts: st: Add ospi port1 pinctrl entries in stm32mp25-pinctrl.dtsiPatrice Chotard
Add pinctrl entry related to OSPI's port1 in stm32mp25-pinctrl.dtsi Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20250512-upstream_omm_ospi_dts-v10-2-fca0fbe6d10a@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14arm64: dts: st: Add OMM node on stm32mp251Patrice Chotard
Add Octo Memory Manager (OMM) entry on stm32mp251 and its two OSPI instance. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20250512-upstream_omm_ospi_dts-v10-1-fca0fbe6d10a@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14ARM: dts: stm32: support STM32h747i-disco boardDario Binacchi
The board includes an STM32H747XI SoC with the following resources: - 2 Mbytes Flash - 1 Mbyte SRAM - LCD-TFT controller - MIPI-DSI interface - FD-CAN - USB 2.0 high-speed/full-speed - Ethernet MAC - camera interface Detailed information can be found at: https://www.st.com/en/evaluation-tools/stm32h747i-disco.html Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://lore.kernel.org/r/20250427074404.3278732-9-dario.binacchi@amarulasolutions.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14ARM: dts: stm32: add an extra pin map for USART1 on stm32h743Dario Binacchi
Add an additional pin map configuration for using the USART1 controller on the stm32h743 MCU. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://lore.kernel.org/r/20250427074404.3278732-8-dario.binacchi@amarulasolutions.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14ARM: dts: stm32: add pin map for UART8 controller on stm32h743Dario Binacchi
Add a pin map configuration for using the UART8 controller on the stm32h743 MCU. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://lore.kernel.org/r/20250427074404.3278732-7-dario.binacchi@amarulasolutions.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14ARM: dts: stm32: add uart8 node for stm32h743 MCUDario Binacchi
Add support for UART8 by applying the settings specified in the reference manual RM0433. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://lore.kernel.org/r/20250427074404.3278732-6-dario.binacchi@amarulasolutions.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14ARM: stm32: add a new SoC - STM32H747Dario Binacchi
The STM32H747 is a dual-core MCU (Cortex-M7 running up to 480 MHz + Cortex-M4 running up to 240 MHz) containing from 1 to 2 Mbytes of Flash memory and 1 Mbyte of internal RAM. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://lore.kernel.org/r/20250427074404.3278732-4-dario.binacchi@amarulasolutions.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14ARM: dts: stm32h7-pinctrl: add _a suffix to u[s]art_pins phandlesDario Binacchi
Allow expanding possible configurations for the same peripheral, consistent with the scheme adopted in Linux. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://lore.kernel.org/r/20250427074404.3278732-2-dario.binacchi@amarulasolutions.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14ARM: dts: st: stm32: Align wifi node name with bindingsKrzysztof Kozlowski
Since commit 3c3606793f7e ("dt-bindings: wireless: bcm4329-fmac: Use wireless-controller.yaml schema"), bindings expect 'wifi' as node name: stm32h750i-art-pi.dtb: bcrmf@1: $nodename:0: 'bcrmf@1' does not match '^wifi(@.*)?$' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250424084706.105049-1-krzysztof.kozlowski@linaro.org Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14ARM: dts: stm32: add low power timer on STM32F746Ben Wolsieffer
Add device tree node for the low power timer on the STM32F746. Signed-off-by: Ben Wolsieffer <ben.wolsieffer@hefring.com> Link: https://lore.kernel.org/r/20250404143514.860126-1-ben.wolsieffer@hefring.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14ARM: dts: stm32: add vrefint support to adc on stm32mp13Olivier Moysan
Set STM32 ADC1&2 as consumers of BSEC, to retrieve vrefint calibration data on STM32MP13x SoCs. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Link: https://lore.kernel.org/r/20250403115954.1061528-3-olivier.moysan@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14ARM: dts: stm32: add vrefint calibration on stm32mp13Olivier Moysan
Describe vrefint calibration cell to be retrieved through bsec, on STM32MP13x SoCs family. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Link: https://lore.kernel.org/r/20250403115954.1061528-2-olivier.moysan@foss.st.com Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
2025-05-14pwm: Tidyup PWM menu for RenesasKuninori Morimoto
Because current PWM Kconfig is sorting by symbol name, it looks strange ordering in menuconfig. => [ ] Renesas R-Car PWM support => [ ] Renesas TPU PWM support [ ] Rockchip PWM support => [ ] Renesas RZ/G2L General PWM Timer support => [ ] Renesas RZ/G2L MTU3a PWM Timer support Let's use common CONFIG_PWM_RENESAS_xxx symbol name for Renesas, and sort it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/877c2mxrrr.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
2025-05-14Merge tag 'renesas-arm-defconfig-for-v6.16-tag2' of ↵Uwe Kleine-König
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into pwm/for-next Renesas ARM defconfig updates for v6.16 (take two) - Enable modular support for the Renesas RZ/G2L GPT and MSIOF sound in the ARM64 defconfig, - Enable more support for RZN1D-DB/EB in shmobile_defconfig. It is merged into the pwm tree due to the next patch renaming PWM_RZG2L_GPT which has a use added in the arm64 defconfig.
generated by cgit (git 2.34.1) at 2025-07-18 18:22:35 +0000