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path: root/drivers/clk/meson
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2017-04-04clk: meson-gxbb: Add GP0 PLL init parametersNeil Armstrong
Tha Amlogic GXBB SoC GP0 PLL needs some vendor provided parameters to be initializated in the the GP0 control registers before configuring the rate with the rate table provided parameters. GXBB GP0 PLL tweaks are also selected to respect the vendor init procedure. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490178747-14837-3-git-send-email-narmstrong@baylibre.com
2017-04-04clk: meson: Add support for parameters for specific PLLsNeil Armstrong
In recent Amlogic GXBB, GXL and GXM SoCs, the GP0 PLL needs some specific parameters in order to initialize and lock correctly. This patch adds an optional PARAM table used to initialize the PLL to a default value with it's parameters in order to achieve to desired frequency. The GP0 PLL in GXBB, GXL/GXM also needs some tweaks in the initialization steps, and these are exposed along the PARAM table. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490178747-14837-2-git-send-email-narmstrong@baylibre.com
2017-04-04clk: meson-gxbb: Add MALI clocksNeil Armstrong
The Mali is clocked by two identical clock paths behind a glitch free mux to safely change frequency while running. The two "mali_0" and "mali_1" clocks are composed of a mux, divider and gate. Expose these two clocks trees using generic clocks. Finally the glitch free mux is added as "mali" clock. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490177935-9646-3-git-send-email-narmstrong@baylibre.com
2017-04-04clk: meson-gxbb: Expose GP0 dt-bindings clock idNeil Armstrong
This patch exposes the GP0 PLL clock id in the dt bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490178747-14837-5-git-send-email-narmstrong@baylibre.com
2017-04-04clk: meson-gxbb: Add MALI clock IDSNeil Armstrong
Add missing MALI clock IDs and expose the muxes and gates in the dt-bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1490177935-9646-2-git-send-email-narmstrong@baylibre.com
2017-04-04dt-bindings: clk: gxbb: expose i2s output clock gatesJerome Brunet
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-10-jbrunet@baylibre.com
2017-03-27clk: meson: mpll: correct N2 maximum valueJerome Brunet
Gxbb datasheet says N2 maximum value is 127 but the register field is 9 bits wide, the maximum value should 511. Test shows value greater than 127, all the way to 511, works well Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-9-jbrunet@baylibre.com
2017-03-27clk: meson8b: add the mplls clocks 0, 1 and 2Jerome Brunet
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-8-jbrunet@baylibre.com
2017-03-27clk: meson: gxbb: mpll: use rw operationJerome Brunet
Use read/write operations for the mpll clocks instead of the read-only ones. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-7-jbrunet@baylibre.com
2017-03-27clk: meson: mpll: add rw operationJerome Brunet
This patch adds new callbacks to the meson-mpll driver to control and set the pll rate. For this, we also need to add the enable bit and sdm enable bit. The corresponding parameters are added to mpll data structure. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-6-jbrunet@baylibre.com
2017-03-27clk: gxbb: put dividers and muxes in tablesJerome Brunet
Until now, there was only 2 dividers and 2 muxes declared for the gxbb platform. With the ongoing work on various subsystem, including audio, this is about to change. Use the same approach as gates for dividers and muxes, putting them in tables to fix the register address at runtime. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-5-jbrunet@baylibre.com
2017-03-27clk: meson8b: put dividers and muxes in tablesJerome Brunet
Until now, there was only 1 divider and 1 mux declared for the meson8b platform. With the ongoing work on various system, including audio, this is about to change. Use the same approach as gates for dividers and muxes, putting them in tables to fix the register address at runtime. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-4-jbrunet@baylibre.com
2017-03-27clk: meson: add missing const qualifiers on gate arraysJerome Brunet
Reported-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-3-jbrunet@baylibre.com
2017-03-27clk: meson: fix SET_PARM macroJerome Brunet
parameter val is not enclosed in parenthesis which is buggy when given an expression instead of a simple value Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20170309104154.28295-2-jbrunet@baylibre.com
2017-03-16clk: meson-gxbb: expose clock CLKID_RNG0Heiner Kallweit
Expose clock CLKID_RNG0 which is needed for the HW random number generator. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-03-03Merge tag 'armsoc-late' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late DT updates from Arnd Bergmann: "These updates have been kept in a separate branch mostly because they rely on updates to the respective clk drivers to keep the shared header files in sync. This includes two branches for arm64 dt updates, both following up on earlier changes for the same platforms that are already merged: Samsung: - add USB3 support in Exynos7 - minor PM related updates Amlogic: - new machines: WeTek Set-top-boxes - various devices added to DT There are also a couple of bugfixes that trickled in since the start of the merge window: - The moxart_defconfig was not building the intended platform - CPU-hotplug was broken on ux500 - Coresight was broken on Juno (never worked)" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits) ARM: deconfig: fix the moxart defconfig ARM: ux500: resume the second core properly arm64: dts: juno: update definition for programmable replicator arm64: dts: exynos: Add regulators for Vbus and Vbus-Boost arm64: dts: exynos: Add USB 3.0 controller node for Exynos7 arm64: dts: exynos: Use macros for pinctrl configuration on Exynos7 pinctrl: dt-bindings: samsung: Add Exynos7 specific pinctrl macro definitions arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e ARM64: dts: meson-gxbb-p200: add ADC laddered keys ARM64: dts: meson: meson-gx: add the SAR ADC ARM64: dts: meson-gxl: add the pwm_ao_b pin ARM64: dts: meson-gx: add the missing pwm_AO_ab node clk: gxbb: fix CLKID_ETH defined twice ARM64: dts: meson-gxl: rename Nexbox A95x for consistency clk: gxbb: add the SAR ADC clocks and expose them dt-bindings: amlogic: Add WeTek boards ARM64: dts: meson-gxbb: Add support for WeTek Hub and Play dt-bindings: vendor-prefix: Add wetek vendor prefix ARM64: dts: meson-gxm: Rename q200 and q201 DT files for consistency ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodes ...
2017-01-27clk: gxbb: fix CLKID_ETH defined twicejbrunet
CLKID_ETH is define in the dt-bindings but has not be commented out in the clock driver. Just do it now. Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-26clk: meson8b: fix clk81 register addressJerome Brunet
During meson8b clock probe, clk81 register address is fixed twice. First using the meson8b_clk_gates array, then by directly changing meson8b_clk81 register. As a result meson8b_clk81.reg = HHI_MPEG_CLK_CNTL + clk_base + clk_base. Fixed by just removing the second fixup. Fixes: e31a1900c1ff ("meson: clk: Add support for clock gates") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-01-23clk: gxbb: add the SAR ADC clocks and expose themMartin Blumenstingl
The HHI_SAR_CLK_CNTL contains three SAR ADC specific clocks: - a mux clock to choose between different ADC reference clocks (this is 2-bit wide, but the datasheet only lists the parents for the first bit) - a divider for the input/reference clock - a gate which enables the ADC clock Additionally this exposes the ADC core clock (CLKID_SAR_ADC) and CLKID_SANA (which seems to enable the analog inputs, but unfortunately there is no documentation for this - we just mimic what the vendor driver does). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-18clk: meson-gxbb: Export HDMI clocksNeil Armstrong
Export HDMI clock from internal to dt-bindings. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-10-07Merge tag 'armsoc-late' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late DT updates from Arnd Bergmann: "These updates have been kept in a separate branch mostly because they rely on updates to the respective clk drivers to keep the shared header files in sync. - The Renesas r8a7796 (R-Car M3-W) platform gets added, this is an automotive SoC similar to the ⅹ8a7795 chip we already support, but the dts changes rely on a clock driver change that has been merged for v4.9 through the clk tree. - The Amlogic meson-gxbb (S905) platform gains support for a few drivers merged through our tree, in particular the network and usb driver changes are required and included here, and also the clk tree changes. - The Allwinner platforms have seen a large-scale change to their clk drivers and the dts file updates must come after that. This includes the newly added Nextthing GR8 platform, which is derived from sun5i/A13. - Some integrator (arm32) changes rely on clk driver changes. - A single patch for lpc32xx has no such dependency but wasn't added until just before the merge window" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits) ARM: dts: lpc32xx: add device node for IRAM on-chip memory ARM: dts: sun8i: Add accelerometer to polaroid-mid2407pxe03 ARM: dts: sun8i: enable UART1 for iNet D978 Rev2 board ARM: dts: sun8i: add pinmux for UART1 at PG dts: sun8i-h3: add I2C0-2 peripherals to H3 SOC dts: sun8i-h3: add pinmux definitions for I2C0-2 dts: sun8i-h3: associate exposed UARTs on Orange Pi Boards dts: sun8i-h3: split off RTS/CTS for UART1 in seperate pinmux dts: sun8i-h3: add pinmux definitions for UART2-3 ARM: dts: sun9i: a80-optimus: Disable EHCI1 ARM: dts: sun9i: cubieboard4: Add AXP806 PMIC device node and regulators ARM: dts: sun9i: a80-optimus: Add AXP806 PMIC device node and regulators ARM: dts: sun9i: cubieboard4: Declare AXP809 SW regulator as unused ARM: dts: sun9i: a80-optimus: Declare AXP809 SW regulator as unused ARM: dts: sun8i: Add touchscreen node for sun8i-a33-ga10h ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2809pxe04 ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2407pxe03 ARM: dts: sun8i: Add touchscreen node for sun8i-a23-inet86dz ARM: dts: sun8i: Add touchscreen node for sun8i-a23-gt90h ARM64: dts: meson-gxbb-vega-s95: Enable USB Nodes ...
2016-09-14clk: gxbb: expose i2c clocksJerome Brunet
I2C and AO_I2C clocks are needed for the i2c driver, expose to DT (and comment out in clk driver) Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-14clk: gxbb: expose USB clocksMartin Blumenstingl
USB0_DDR_BRIDGE and USB1_DDR_BRIDGE1 are needed for the related dwc2 usb controller. USB, USB0 and USB1 are needed for the PHYs. Expose these clocks to DT and comment out in clk driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-14clk: gxbb: expose spifc clockJerome Brunet
SPI clock is needed for the spifc driver, expose to DT (and comment out in the clk driver) Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-14clk: gxbb: expose MPLL2 clock for use by DTMartin Blumenstingl
This exposes the MPLL2 clock as this is one of the input clocks of the ethernet controller's internal mux. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2016-09-14clk: meson: fix CLKID_GCLK_VENCI_INT typoArnd Bergmann
The addition of many gate clocks added two entries in an array for the same value: drivers/clk/meson/meson8b.c:479:10: error: initialized field overwritten [-Werror=override-init] [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw, [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_vencp_int.hw, This was clearly an accident, and since all other identifiers are listed in the order in which they are defined, I'm changing the first one to CLKID_GCLK_VENCI_INT0, making it all consistent again. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: e31a1900c1ff ("meson: clk: Add support for clock gates") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-14meson: clk: Use builtin_platform_driver to simplify the codeWei Yongjun
Use the builtin_platform_driver() macro to make the code simpler. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-09-02Merge branch 'clk-meson-gxbb' into clk-nextMichael Turquette
2016-09-02clk: meson-gxbb: Export PWM related clocks for DTNeil Armstrong
Add the PWM related clocks in order to be referenced as PWM source clocks. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1471870177-10609-1-git-send-email-narmstrong@baylibre.com
2016-09-01meson: clk: Add support for clock gatesAlexander Müller
This patch adds support for the meson8b clock gates. Most of them are disabled by Amlogic U-Boot, but need to be enabled for ethernet, USB and many other components. Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-7-git-send-email-serveralex@gmail.com
2016-09-01gxbb: clk: Adjust MESON_GATE macro to be shared with meson8bAlexander Müller
The macro used gxbb_ prefix for clock definitions. In order to share the macro between gxbb and meson8b, the prefix must be moved to gxbb.c. Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-6-git-send-email-serveralex@gmail.com
2016-09-01clk: meson: Copy meson8b CLKID defines to private header fileAlexander Müller
Only expose future CLKID constants if necessary. This patch removes CLK_NR_CLKS from the DT bindings but leaves all previously defined CLKIDs there to keep backward compatibility. Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-5-git-send-email-serveralex@gmail.com
2016-09-01meson: clk: Rename register names according to Amlogic datasheetAlexander Müller
Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-4-git-send-email-serveralex@gmail.com
2016-09-01meson: clk: Move register definitions to meson8b.hAlexander Müller
Move the register definitions into a separate header file to reflect the gxbb implementation. Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-3-git-send-email-serveralex@gmail.com
2016-09-01clk: meson: Rename meson8b-clkc.c to reflect gxbb naming conventionAlexander Müller
Signed-off-by: Alexander Müller <serveralex@gmail.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/1472319654-59048-2-git-send-email-serveralex@gmail.com
2016-09-01Merge remote-tracking branch 'clk/clk-meson-gxbb-ao' into clk-meson-gxbbMichael Turquette
2016-08-24Merge branch 'clk-meson-gxbb-ao' into clk-nextStephen Boyd
* clk-meson-gxbb-ao: clk: meson: Fix invalid use of sizeof in gxbb_aoclkc_probe()
2016-08-24clk: meson: Fix invalid use of sizeof in gxbb_aoclkc_probe()Wei Yongjun
sizeof() when applied to a pointer typed expression gives the size of the pointer, not that of the pointed data. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Fixes: f8c11f79912d ("clk: meson: Add GXBB AO Clock and Reset controller driver") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-19Merge branch 'clk-meson-gxbb-ao' into clk-nextStephen Boyd
* clk-meson-gxbb-ao: clk: meson: Add GXBB AO Clock and Reset controller driver dt-bindings: clock: reset: Add GXBB AO Clock and Reset Bindings
2016-08-19clk: meson: Add GXBB AO Clock and Reset controller driverNeil Armstrong
Adds a Clock and Reset controller driver for the Always-On part of the Amlogic Meson GXBB SoC. It exports paired Clocks and Resets lines that will be used by peripherals in the Always-On subsystem. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-15Merge branch 'clk-meson-gxbb' into clk-nextStephen Boyd
* clk-meson-gxbb: clk: gxbb: add MMC gate clocks, and expose for DT
2016-08-15clk: gxbb: add MMC gate clocks, and expose for DTKevin Hilman
Add the SD/eMMC gate clocks and expose them for use by DT. While at it, also explose FCLK_DIV2 since this is one of the input clocks to the mux internal to each of the SD/eMMC blocks. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-08-15clk: gxbb: use builtin_platform_driver to simplify the codeWei Yongjun
Use the builtin_platform_driver() macro to make the code simpler. Signed-off-by: Wei Yongjun <weiyj.lk@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-07-15Merge branch 'clk-s905' into clk-nextMichael Turquette
2016-07-15Revert "clk: gxbb: expose CLKID_MMC_PCLK"Michael Turquette
This reverts commit e16fb2e6355c1c1b41623af9e01ada196e2af098. Updated documentation from the chip vendor reveals that this clock is not required for correct operation of the MMC controller. As such, do not expose it to DT. Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-07-07Merge branch 'clk-s905' into clk-nextMichael Turquette
2016-07-07clk: gxbb: expose CLKID_MMC_PCLKKevin Hilman
The MMC_PCLK is needed for the SD/eMMC driver, expose to DT (and comment out in clk driver) Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160707033837.20029-1-khilman@baylibre.com
2016-07-06clk: meson: make gxbb explicitly non-modularPaul Gortmaker
The Kconfig currently controlling compilation of this code is: drivers/clk/meson/Kconfig:config COMMON_CLK_GXBB drivers/clk/meson/Kconfig: bool ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE and ALIAS are no-op for non-modules. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Carlo Caione <carlo@caione.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: linux-clk@vger.kernel.org Cc: linux-amlogic@lists.infradead.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160704211220.5685-3-paul.gortmaker@windriver.com
2016-07-06clk: meson8b: make it explicitly non-modularPaul Gortmaker
The Kconfig currently controlling compilation of this code is: drivers/clk/meson/Kconfig:config COMMON_CLK_MESON8B drivers/clk/meson/Kconfig: bool ...meaning that it currently is not being built as a module by anyone. However a recent commit added a bunch of modular boilerplate to this driver. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. Also note that MODULE DEVICE_TABLE/ALIAS are no-op when non-modular. We also delete the MODULE_LICENSE tag etc. since all that information was (or is now) contained at the top of the file in the comments. Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Carlo Caione <carlo@caione.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: linux-clk@vger.kernel.org Cc: linux-amlogic@lists.infradead.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160704211220.5685-2-paul.gortmaker@windriver.com
2016-06-22clk: gxbb: add AmLogic GXBB clk controller driverMichael Turquette
The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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