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path: root/drivers/gpu/drm/i915
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2025-03-05drm/i915/display: fbdev: Move custom restore code to new callbackThomas Zimmermann
i915's fbdev contains code for restoring the client's framebuffer. It is specific to i195 and cannot be ported to the common fbdev client. Introduce the callback struct drm_fb_helper.fb_restore and implement it for i915. The fbdev helpers invoke the callback after restoring the fbdev client. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241212170913.185939-6-tzimmermann@suse.de Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
2025-03-05drm/i915/display: Remove fbdev suspend and hotplug trackingThomas Zimmermann
The DRM client code already tracks suspend status and hotplug events for each client. Remove similar code from i915's fbdev client. Allows for the removal of all hdp_* fields form struct intel_fbdev. Calls to intel_fbdev_output_poll_changed() are reduced the shared helper drm_fb_helper_hotplug_event(). Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241212170913.185939-5-tzimmermann@suse.de Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
2025-03-05drm/{i915, xe}: Suspend/resume fbdev emulation via client interfacesThomas Zimmermann
Implement drm_client_dev_suspend() and drm_client_dev_resume() for i915's fbdev emulation and call the helper via DRM client interfaces. This is required to convert i915 and xe to DRM's generic fbdev client. No functional changes. Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241212170913.185939-2-tzimmermann@suse.de Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
2025-03-05drm/i915/display: convert intel_display.c to struct intel_displayJani Nikula
Going forward, struct intel_display is the main display device data pointer. Convert as much as possible of intel_display.c to struct intel_display. This exposes a couple of outside issues that need to be fixed as well, in a register macro and a DSI PLL stub. Reviewed-by: Nemesa Garg <nemesa.garg@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1c0bafcb978d1cf4f4d54be2f497386f5302f7c8.1741084010.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-03-05drm/i915/display: remove dupe intel_update_watermarks() declarationJani Nikula
intel_wm.h already has intel_update_watermarks() declaration. Remove the dupe. Reviewed-by: Nemesa Garg <nemesa.garg@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/67eeebff3ec9459f7854fbc56cfd7f2aa8c1fdc6.1741084010.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-03-05drm/i915/display: convert intel_has_pending_fb_unpin() to struct intel_displayJani Nikula
Going forward, struct intel_display is the main display device data pointer. The intel_display.[ch] files are too big to convert in one go. Convert intel_has_pending_fb_unpin() to struct intel_display. Reviewed-by: Nemesa Garg <nemesa.garg@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/d70ad8f9cbba5ee32d985b76047b56996ad4b31e.1741084010.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-03-05drm/i915/display: convert some intel_display.[ch] functions to struct ↵Jani Nikula
intel_display Going forward, struct intel_display is the main display device data pointer. The intel_display.[ch] files are too big to convert in one go. Convert the interface towards intel_display_driver.c to struct intel_display. Reviewed-by: Nemesa Garg <nemesa.garg@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ee8b108420763cbf47ee77fa35b782a7293f9cfe.1741084010.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-03-05drm/i915/display: convert various port/phy helpers to struct intel_displayJani Nikula
Going forward, struct intel_display is the main display device data pointer. The intel_display.[ch] files are too big to convert in one go. Convert the various port/phy helpers to struct intel_display. Reviewed-by: Nemesa Garg <nemesa.garg@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/e28e53bad5014ba3ef17431557b517f1b8530963.1741084010.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-03-05drm/i915/reset: add modeset_stuck callback to intel_display_reset_prepare()Jani Nikula
Drop the dependency on gt by providing a callback for trying to unbreak stuck modeset. Do intel_gt_set_wedged() via the callback. It's by no means pretty, but this is perhaps the most straightforward alternative. Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/d322e20927326afa47c0df8a4d4776ee77010e6d.1741001054.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-03-05drm/i915/reset: pass test only parameter to intel_display_reset_finish()Jani Nikula
Deduplicate the gpu_reset_clobbers_display() part by passing the information in from gt side. Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/a36481db334fedcde50ae0e66c4d57825cae8cb7.1741001054.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-03-05drm/i915/reset: decide whether display reset is needed on gt sideJani Nikula
Move the checks for whether display reset is needed at all to gt side of things. This way, we can decide to skip the display calls altogether if display reset is not required. Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/c32a88f292f516ec702bd07001ac609b8acc2888.1741001054.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-03-05drm/i915/reset: remove I915_RESET_MODESET flagJani Nikula
Since commit d59cf7bb73f3 ("drm/i915/display: Use dma_fence interfaces instead of i915_sw_fence") we don't have anyone waiting on the I915_RESET_MODESET bit, and there's no need for its semantics. Instead, simply return true from intel_display_reset_prepare() to indicate that intel_display_reset_finish() should be called. Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/294690db3fae8fec7f356edf467e79882ed494db.1741001054.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-03-05drm/i915/reset: add intel_display_reset_test()Jani Nikula
Add a helper for checking if we want to test display reset regardless of whether it's strictly necessary. This will come in handy in follow-up work where we want to check this from gt reset side. v2: Drop superfluous newline Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/487dec72f753302cd565c3a8164afa7fc1e12ed7.1741001054.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-03-05drm/i915/reset: add intel_gt_gpu_reset_clobbers_display() helperJani Nikula
Add a helper for checking the gpu_reset_clobbers_display flag to make it easier to relocate the flag later. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/434d5db7675ed9717b3beae1389008b68a961855.1741001054.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-03-05drm/i915: move pending_fb_pin to struct intel_displayJani Nikula
pending_fb_pin is more about display than GPU reset. Move it to struct intel_display. The restore sub-struct already contains reset related members, so move it there. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ff779ae318610e6f6813474bcaa53851ffff909d.1741001054.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-03-05drm/i915/display: convert display reset to struct intel_display *Jani Nikula
Going forward, struct intel_display will be the main display device structure. Convert display reset to it as much as possible. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/060c309189f1c084e012521822f4a0247f64528e.1741001054.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-03-04drm/i915/mst: update max stream count to match number of pipesJani Nikula
We create the stream encoders and attach connectors for each pipe we have. As the number of pipes has increased, we've failed to update the topology manager maximum number of payloads to match that. Bump up the max stream count to match number of pipes, enabling the fourth stream on platforms that support four pipes. Cc: stable@vger.kernel.org Cc: Imre Deak <imre.deak@intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250226135626.1956012-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com> (cherry picked from commit 15bccbfb78d63a2a621b30caff8b9424160c6c89) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2025-03-04drm/i915: Reoder gen9+ timestamp freq register bitsVille Syrjälä
We customarily define the bits of a register in big endian order. Reorder the gen9+ timestamp freq register bits to match. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-13-ville.syrjala@linux.intel.com
2025-03-04drm/i915: Use REG_BIT() & co. for gen9+ timestamp freq registersVille Syrjälä
Convert the gen9+ timestamo frequency related registers to the modern REG_BIT()/etc. style. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-12-ville.syrjala@linux.intel.com
2025-03-04drm/i915: Reoder BDW+ EU/slice fuse bitsVille Syrjälä
We customarily define the bits of a register in big endian order. Reorder the BDW+ fuse bits to match. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-11-ville.syrjala@linux.intel.com
2025-03-04drm/i915: Use REG_BIT() & co. for BDW+ EU/slice fuse bitsVille Syrjälä
Convert the BDW+ EU/slice fuse bits to the modern REG_BIT()/etc. style. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-10-ville.syrjala@linux.intel.com
2025-03-04drm/i915: Reoder CHV EU/slice fuse bitsVille Syrjälä
We customarily define the bits of a register in big endian order. Reorder the CHV fuse bits to match. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-9-ville.syrjala@linux.intel.com
2025-03-04drm/i915: Use REG_BIT() & co. for CHV EU/slice fuse bitsVille Syrjälä
Convert the CHV EU/slice fuse bits to the modern REG_BIT()/etc. style. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-8-ville.syrjala@linux.intel.com
2025-03-04drm/i915: Extract gen8_report_fault()Ville Syrjälä
gen8_check_faults() and xehp_check_faults() are nearly identical. Refactor the common bits into gen8_report_fault(). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-7-ville.syrjala@linux.intel.com
2025-03-04drm/i915: Introduce RING_FAULT_VADDR_MASKVille Syrjälä
Add a proper bitmask definition for the pre-bdw fault virtual address bits insted of abusing PAGE_MASK. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-6-ville.syrjala@linux.intel.com
2025-03-04drm/i915: Document which RING_FAULT bits apply to which platformsVille Syrjälä
The RING_FAULT bits have change a bit over the years. Document which platforms use which bits. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-5-ville.syrjala@linux.intel.com
2025-03-04drm/i915: Use REG_BIT() & co. for ring fault registersVille Syrjälä
Update the ring fault registers to use the modern REG_BIT() stuff. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-4-ville.syrjala@linux.intel.com
2025-03-04drm/i915: Relocate RING_FAULT bitsVille Syrjälä
We share the bit definitions between the older RING_FAULT registers and their various gen12+ counterparts. Currently the bits are defined next to the new registers which isn't what we typically do. Move the bit definitions next the older register offsets, and leave breadcrumbs around the gen12+ registers to make it easier to find the right bits. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-3-ville.syrjala@linux.intel.com
2025-03-04drm/i915: Bump RING_FAULT engine ID bitsVille Syrjälä
The fault engine ID field has been 5 bits since icl. Bump our define to match. The extra bits were unused before icl so we should be able to use the larger mask unconditionally. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-2-ville.syrjala@linux.intel.com
2025-03-03drm/i915/fbc: handle dirty rect coords for the first frameVinod Govindapillai
During enabling FBC, for the very first frame, the prepare dirty rect routine wouldnt have executed as at that time the plane reference in the fbc_state would be NULL. So this could make driver program some invalid entries as the damage area. Though fbc hw ignores the dirty rect values programmed for the first frame after enabling FBC, driver must ensure that valid dirty rect coords are programmed. So ensure that for the first frame correct dirty rect coords are updated to the HW. Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250228093802.27091-10-vinod.govindapillai@intel.com
2025-03-03drm/i915/fbc: disable FBC if PSR2 selective fetch is enabledVinod Govindapillai
It is not recommended to have both FBC dirty rect and PSR2 selective fetch be enabled at the same time. Mark FBC as not possible, if PSR2 selective fetch is enabled. v2: fix the condition to disable FBC if PSR2 enabled (Jani) v3: use HAS_FBC_DIRTY_RECT() v4: Update to patch description Bspec: 68881 Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250228093802.27091-9-vinod.govindapillai@intel.com
2025-03-03drm/i915/fbc: dirty rect support for FBCVinod Govindapillai
Dirty rectangle feature allows FBC to recompress a subsection of a frame. When this feature is enabled, display will read the scan lines between dirty rectangle start line and dirty rectangle end line in subsequent frames. Use the merged damage clip stored in the plane state to configure the FBC dirty rect areas. v2: - Move dirty rect handling to fbc state (Ville) v3: - Use intel_fbc_dirty_rect_update_noarm (Ville) - Split plane damage collection and dirty rect preparation - Handle case where dirty rect fall outside the visible region v4: - A state variable to check if we need to update dirty rect registers in case intel_fbc_can_flip_nuke() (Ville) v5: - No need to use a separate valid flag, updates to the conditions for prepare damage rect (Ville) - Usage of locks in fbc dirty rect related functions (Ville) v6: - updates dirty rect handling (Ville) v7: - Loop through all planes in atomic state is good enough (Ville) Bspec: 68881, 71675, 73424 Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250228093802.27091-8-vinod.govindapillai@intel.com
2025-03-03drm/i915/fbc: avoid calling fbc activate if fbc is activeVinod Govindapillai
If FBC is already active, we don't need to call FBC activate routine again unless there are changes to the fences. So skip this on all platforms that don't have fences. Any FBC register updates done after enabling the dirty rect support in xe3 will trigger nuke by FBC which is counter productive to the fbc dirty rect feature. The front buffer rendering sequence will call intel_fbc_flush() and which will call intel_fbc_nuke() or intel_fbc_activate() based on FBC status explicitly and won't get impacted by this change. v2: use HAS_FBC_DIRTY_RECT() move this functionality within intel_fbc_activate() v3: update to intel_fbc_activate logic (Ville) update to the patch description Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250228093802.27091-7-vinod.govindapillai@intel.com
2025-03-03drm/i915/fbc: introduce HAS_FBC_DIRTY_RECT() for FBC dirty rect supportVinod Govindapillai
Introduce a macro to check if the platform supports FBC dirty rect capability. v2: - update to the patch subject Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250228093802.27091-6-vinod.govindapillai@intel.com
2025-03-03drm/i915/fbc: add register definitions for fbc dirty rect supportVinod Govindapillai
Register definitions for FBC dirty rect support v2: - update to the patch subject Bspec: 71675, 73424 Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250228093802.27091-5-vinod.govindapillai@intel.com
2025-03-03drm/i915/display: update and store the plane damage clipsVinod Govindapillai
Userspace can pass damage area clips per plane to track changes in a plane and some display components can utilze these damage clips for efficiently handling use cases like FBC, PSR etc. A merged damage area is generated and its coordinates are updated relative to viewport and HW and stored in the plane_state. This merged damage areas will be used for FBC dirty rect support in xe3 in the follow-up patch. Big thanks to Ville Syrjala for his contribuitions in shaping up of this series. v1: - Move damage_merged helper to cover bigjoiner case and use the correct plane state for damage find helper (Ville) - Damage handling code under HAS_FBC_DIRTY_RECT() so the the related part will be executed only for xe3+ - Changed dev_priv to i915 in one of the functions v2: - damage reported is stored in the plane state after coords adjustmentments irrespective of fbc dirty rect support. - Damage to be empty in case of plane not visible (Ville) - Handle fb could be NULL and plane not visible cases (Ville) v3: - No need to empty damage in case disp ver < 12 (Ville) - update to the patch subject Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250228093802.27091-4-vinod.govindapillai@intel.com
2025-03-03drm/i915/fbc: remove one duplicate forward declarationVinod Govindapillai
Remove the duplicate "intel_display"declaration from intel_fbc.h Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Mika Kahola <mika.kahola@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250228093802.27091-2-vinod.govindapillai@intel.com
2025-03-03drm/i915: split out i915_gtt_view_types.h from i915_vma_types.hJani Nikula
In the interest of limiting the display dependencies on i915 core headers, split out i915_gtt_view_types.h from i915_vma_types.h, and only include the new header from intel_display_types.h. Reuse the new header from xe compat code too, failing build if partial view is used in display code. Side note: Why would we ever have set enum i915_gtt_view_type values to size of each type?! What an insane hack. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/bb31885c32dbddad76d634c6fdb98a73b546b42e.1740412806.git.jani.nikula@intel.com
2025-03-03drm/i915: relocate intel_plane_ggtt_offset() to intel_atomic_plane.cJani Nikula
With the primary goal of removing #include "i915_vma.h" from intel_display_types.h, move intel_plane_ggtt_offset() to a proper function in intel_atomic_plane.c. This reveals tons of implicit dependencies all over the place that we pulled in via i915_vma.h. Fix the fallout. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/70ac6d19518f355abf37ac8c4b0f1d18878be28c.1740412806.git.jani.nikula@intel.com
2025-03-03drm/i915/pxp & drm/xe/pxp: Figure out pxp instance from the gem objectJani Nikula
It's undesirable to have to figure out the pxp pointer in display code. For one thing, its type is different for i915 and xe. Since we can figure the pxp pointer out in the pxp code from the gem object, offload it there. v2: Rebase Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250228114527.3091620-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-03-03drm/i915/hdcp: add hdcp sub-struct to struct intel_digital_portJani Nikula
Move hdcp_mutex, num_hdcp_streams, hdcp_auth_status, hdcp_port_data, and hdcp_mst_type1_capable members of struct intel_digital_port under an hdcp sub-struct to group hdcp related things together. Rename them mutex, num_streams, auth_status, port_data, and mst_type1_capable for clarity. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/9da4be57b068acd06dec8b93977f0a70627103d4.1740746939.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-03-03drm/i915/mst: add mst sub-struct to struct intel_connectorJani Nikula
Move port and mst_port members of struct intel_connector under an mst sub-struct to group mst related things together. Rename the latter dp for clarity. Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/e2afaf4595ae8e3241aaca1c1bb4d6356b07e44a.1740746939.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-03-03drm/i915/mst: add mst sub-struct to struct intel_dpJani Nikula
Move active_mst_links, mst_encoders[], and mst_mgr members of struct intel_dp under an mst sub-struct to group mst related things together. Rename them active_links, stream_encoders[] and mgr for clarity. Note that is_mst and mst_detect are not included, as they're also relevant for non-mst. The sub-struct is for active mst. Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/6f282f90bfe2dd9162e2dee8f681c84313971992.1740746939.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-02-28drm/i915/display: Make POWER_DOMAIN_*() always result in enum ↵Gustavo Sousa
intel_display_power_domain In the hope of contributing to type safety in our code, let's ensure that the type returned by the POWER_DOMAIN_*() macros is always of type enum intel_display_power_domain. v2: - Remove accidental +1 in definition of POWER_DOMAIN_PIPE(). (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250227-improve-type-safey-power-domain-macros-v3-2-b6eaa00f9c33@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
2025-02-28drm/i915/display: Use explicit base values in POWER_DOMAIN_*() macrosGustavo Sousa
Although we have comments in intel_display_limits.h saying that the code expects PIPE_A and TRANSCODER_A to be zero, it doesn't hurt to add them as explicit base values for calculating the power domain offset in POWER_DOMAIN_*() macros. On the plus side, we have that this: * Fixes a warning reported by kernel test robot <lkp@intel.com> about doing arithmetic with two different enum types. * Makes the code arguably more robust (in the unlikely event of those bases becoming non-zero). v2: - Prefer using explicit base values instead of simply casting the macro argument to int. (Ville) - Update commit message to match the new approach (for reference, the old message subject was "drm/i915/display: Use explicit cast in POWER_DOMAIN_*() macros"). Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202502120809.XfmcqkBD-lkp@intel.com/ Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250227-improve-type-safey-power-domain-macros-v3-1-b6eaa00f9c33@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
2025-02-28drm/i915/audio: Extend Wa_14020863754 to Xe3_LPDGustavo Sousa
Workaround Wa_14020863754 also applies to Xe3_LPD. Update needs_wa_14020863754() accordingly. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250227-xe3lpd-wa-14020863754-v2-2-92b35de1c563@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
2025-02-28drm/i915/display: Use IP version check for Wa_14020863754Gustavo Sousa
Wa_14020863754 applies to the display IP, so we should be checking on display IP version instead of platform. So, let's replace display->platform.battlemage with the proper IP version check (14.01 for Xe2_HPD). Furthermore, for workarounds, we should be checking on full IP versions to avoid applying the workaround to some variant of the IP that could theoretically appear in the future (which is likely to have a different minor release number), since the issue addressed by the workaround could be fixed in such new release. Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250227-xe3lpd-wa-14020863754-v2-1-92b35de1c563@intel.com Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
2025-02-28Merge drm/drm-next into drm-intel-nextJani Nikula
Sync to fix conlicts between drm-xe-next and drm-intel-next. Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-02-28Merge tag 'drm-misc-next-2025-02-27' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for v6.15: Cross-subsystem Changes: bus: - mhi: Avoid access to uninitialized field Core Changes: - Fix docmentation dp: - Add helpers for LTTPR transparent mode sched: - Improve job peek/pop operations - Optimize layout of struct drm_sched_job Driver Changes: arc: - Convert to devm_platform_ioremap_resource() aspeed: - Convert to devm_platform_ioremap_resource() bridge: - ti-sn65dsi86: Support CONFIG_PWM tristate i915: - dp: Use helpers for LTTPR transparent mode mediatek: - Convert to devm_platform_ioremap_resource() msm: - dp: Use helpers for LTTPR transparent mode nouveau: - dp: Use helpers for LTTPR transparent mode panel: - raydium-rm67200: Add driver for Raydium RM67200 - simple: Add support for BOE AV123Z7M-N17, BOE AV123Z7M-N17 - sony-td4353-jdi: Use MIPI-DSI multi-func interface - summit: Add driver for Apple Summit display panel - visionox-rm692e5: Add driver for Visionox RM692E5 repaper: - Fix integer overflows stm: - Convert to devm_platform_ioremap_resource() vc4: - Convert to devm_platform_ioremap_resource() Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/20250227094041.GA114623@linux.fritz.box
2025-02-27drm/i915/dsb: Allow DSB based commits when scalers are in useVille Syrjälä
Have DSB perform plane scaler programming as well. Changes to pfit/pipe scaler are not being done on the dsb since those take the fastset path. However we do now allow DSB based plane updates when the pfit/pipe scaler is currently enabled (the pfit/pipe scaler just won't be touched by the DSB). Fortunately the hardware issue where some scaler registers are latched at frame start and some at start of vblank has been fixed on icl+ (IIRC), and since DSB is tgl+ only we don't have to do any changes to the DSB vblank evasion. Not that we handle that hardware issue correctly in the CPU vblank evasion either... Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250218205850.1422-4-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar <uma.shakar@intel.com>
generated by cgit (git 2.34.1) at 2025-07-18 22:26:33 +0000