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path: root/drivers/gpu/drm/i915
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2025-05-02drm/i915/hdcp: pass the context to the HDCP GSC message interfaceJani Nikula
The opaque HDCP GSC context nicely abstracts the differences between drivers. Pass that instead of struct drm_i915_private or struct xe_device to intel_hdcp_gsc_msg_send(). We can store the driver specific data in the context. This lets us drop the dependency on i915_drv.h from intel_hdcp_gsc_message.c. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/df1653212f9014e717701b017e78e0017884b870.1745524803.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-02drm/i915/hdcp: rename HDCP GSC context alloc/free functionsJani Nikula
Name the functions intel_hdcp_gsc_context_alloc() and intel_hdcp_gsc_context_free() for consistency. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/c6e25686ed20b5fdea9a59faf6a64a7312a075b0.1745524803.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-02drm/i915/hdcp: rename struct intel_hdcp_gsc_message to intel_hdcp_gsc_contextJani Nikula
It's really about the context more than about the message. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/ca0a802a81ba4e96e7c40646a32386d4351d6ff4.1745524803.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-02drm/i915/hdcp: split HDCP GSC message alloc/save responsibilitiesJani Nikula
Allocate and initialize the HDCP GSC message in intel_hdcp_gsc_hdcp2_init() as before, but store the pointer to display->hdcp.hdcp_message in the caller. Similarly, pass in the pointer to intel_hdcp_gsc_free_message(). Cc: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/a74fcc941126bf92d12115b5faf4f75099e26242.1745524803.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-02drm/i915/hdcp: deduplicate and refactor HDCP GSC ops initializationJani Nikula
The gsc_hdcp_ops is duplicated and initialized exactly the same way in two different places (for i915 and xe), and requires forward declarations for all the hooks. Deduplicate, and make the functions static. There are slight differences in the i915 and xe implementations of intel_hdcp_gsc_init() and intel_hdcp_gsc_fini(). Take the best of both, and improve. We need to expose intel_hdcp_gsc_hdcp2_init() and intel_hdcp_gsc_free_message() for this, and create the latter for xe. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/21e7871b35d4c7d13f016b5ecb4f10e5be72c531.1745524803.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-02drm/i915/hdcp: remove duplicate declarationsJani Nikula
intel_hdcp_gsc_msg_send() and intel_hdcp_gsc_check_status() are declared in intel_hdcp_gsc.h. Cc: Suraj Kandpal <suraj.kandpal@intel.com> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/f300d7cdb2af681291df938194f575f05c2c41bc.1745524803.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-02drm/i915/display: Implement wa_14024400148Nemesa Garg
Workaround recommend use polling method for pm_demand to finish as to avoid timeout. v2: Add polling method within pmdemand_wait. Update error message[Jani] Signed-off-by: Nemesa Garg <nemesa.garg@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://lore.kernel.org/r/20250416152044.2668249-1-nemesa.garg@intel.com
2025-05-02drm/i915/error: drop dmesg suggestion to file bugs on GPU hangsJani Nikula
We haven't updated the DRIVER_TIMESTAMP since commit 3570bd989acc ("drm/i915: Update DRIVER_DATE to 20230929") 1½ years ago. Before then, the previous update was commit 139caf7ca286 ("drm/i915: Update DRIVER_DATE to 20201103") 4+ years ago. The DRIVER_DATE has also been removed altogether. We've used the DRIVER_TIMESTAMP to log suggestions to file bugs on GPU hangs when they happen on a driver less than six months old. Combined with the sporadic DRIVER_TIMESTAMP updates, we really haven't logged the suggestions for years. Just stop logging the suggestion to file bugs altogether, and remove DRIVER_TIMESTAMP. This doesn't really change anything wrt to logging GPU errors or how we handle bugs. And effectively we already stopped logging the message a year ago when we stopped updating DRIVER_TIMESTAMP. Instead, add an unconditional message about the GPU error state location. Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tursulin@ursulin.net> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Link: https://lore.kernel.org/r/20250429115055.2133143-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-02drm/i915/backlight: drop dmesg suggestion to file bugsJani Nikula
Drop the FDO_BUG_URL from the source, and stop suggesting to file bugs on DPCD backlight issues. We don't do this anywhere else in display, this isn't a special snowflake. As a consequence, also drop the dependency on i915_utils.h from intel_dp_aux_backlight.c. Acked-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Link: https://lore.kernel.org/r/20250429112534.2121656-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-05-02Merge tag 'v6.15-rc4' into x86/msr, to pick up fixes and resolve conflictsIngo Molnar
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2025-05-01drm/i915/slpc: Balance the inc/dec for num_waitersVinay Belgaumkar
As seen in some recent failures, SLPC num_waiters value is < 0. This happens because the inc/dec are not balanced. We should skip decrement for the same conditions as the increment. Currently, we do that for power saving profile mode. This patch also ensures that num_waiters is incremented in the case min_softlimit is at boost freq. It ensures that we don't reduce the frequency while this request is in flight. v2: Add Fixes tags Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13598 Fixes: f864a29afc32 ("drm/i915/slpc: Optmize waitboost for SLPC") Fixes: 4a82ceb04ad4 ("drm/i915/slpc: Add sysfs for SLPC power profiles") Cc: Sk Anirban <sk.anirban@intel.com> Reviewed-by: Sk Anirban <sk.anirban@intel.com> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://lore.kernel.org/r/20250428183555.3250021-1-vinay.belgaumkar@intel.com
2025-04-30drm/i915/display: move min_hblank from dp_mst.c to dp.cArun R Murthy
Minimum HBlank is programmed to address jitter for high resolutions with high refresh rates that have small Hblank, specifically where Hblank is smaller than one MTP. TODO: Add the min_hblank calculation for hdmi as well. v2: move from intel_audio.c to intel_dp.c some correction in link_bpp_x16 (Imre) v3: min_hblank for 8b/10b MST and 128b/132b SST/MST handle error for intel_dp_mst_dsc_get_slice_count reset min_hblank before disabling transcoder (Imre) v4: compute link_bpp_x16 within compute_min_hblank, return error in case of compute failure call compute_min_hblank() before vrr_compute_config (Imre) v5: readout MIN_HBLAN reg for Xe3+ Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250424-hblank-v7-2-8b002f1506cc@intel.com
2025-04-29drm/i915/pch: fix warning for coffeelake on SunrisePoint PCHJiajia Liu
i915/pch reports a warning on a mini PC which has a CoffeeLake-S GT2 [UHD Graphics 630] [8086:3e92] and an ISA bridge - H110 LPC Controller [8086:a143]. [5.608723] i915 0000:00:02.0: [drm] Found coffeelake (device ID 3e92) integrated display version 9.00 stepping N/A [5.608969] ------------[ cut here ]------------ [5.608972] i915 0000:00:02.0: [drm] drm_WARN_ON(!display->platform.skylake && !display->platform.kabylake) [5.608995] WARNING: CPU: 3 PID: 440 at drivers/gpu/drm/i915/display/intel_pch.c:126 intel_pch_type+0x1af/0xae0 [i915] [5.609317] CPU: 3 UID: 0 PID: 440 Comm: (udev-worker) Not tainted 6.15.0-rc3-drm-tip-2fa6469c618d #3 PREEMPT(voluntary) Signed-off-by: Jiajia Liu <liujiajia@kylinos.cn> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://lore.kernel.org/r/20250423073730.585181-1-liujiajia@kylinos.cn Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2025-04-29drm/i915/gt: Add delay to let engine resumes properlyNitin Gote
Sometimes engine reset fails because the engine resumes from an incorrect RING_HEAD. Engine head failed to set to zero even after writing into it. This is a timing issue and we experimented different values and found out that 20ms delay works best based on testing. So, add a 20ms delay to let engine resumes from correct RING_HEAD. Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13968 Signed-off-by: Nitin Gote <nitin.r.gote@intel.com> Reviewed-by: Sebastian Brzezinka <sebastian.brzezinka@intel.com> Reviewed-by: Krzysztof Karas <krzysztof.karas@intel.com> Link: https://lore.kernel.org/r/20250416103640.212269-1-nitin.r.gote@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
2025-04-29drm/i915/hdmi: Use an intel_connector pointer everywhereImre Deak
Following the convention, convert intel_hdmi.c to use an intel_connector pointer everywhere, calling this pointer connector. If the intel connector must be casted from a drm_connector, call this pointer _connector and use this pointer only for the casting. v2: Use for_each_new_intel_connector_in_state(). (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250428134716.3396802-3-imre.deak@intel.com
2025-04-29drm/i915/dp: Use an intel_connector pointer everywhereImre Deak
Following the convention, convert intel_dp.c to use an intel_connector pointer everywhere, calling this pointer connector. If the intel connector must be casted from a drm_connector, call this pointer _connector and use this pointer only for the casting. v2: Use for_each_intel_connector_iter(). (Jani) Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://lore.kernel.org/r/20250428134716.3396802-2-imre.deak@intel.com
2025-04-28drm/i915/psr: Move PSR workaround to intel_psr.cJouni Högander
Logical place for PSR workaround needing vblank delay is in intel_psr_min_vblank_delay. Move it there. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://lore.kernel.org/r/20250423102704.1368310-2-jouni.hogander@intel.com
2025-04-28drm/i915/display: Ensure enough lines between delayed VBlank and VBlankJouni Högander
To deterministically capture the transition of the state machine going from SRDOFFACK to IDLE, the delayed V. Blank should be at least one line after the non-delayed V. Blank. Ensure this by adding new interface into intel_psr to query number of lines needed for vblank delay and call it from intel_crtc_vblank_delay. v3: use existing intel_crtc_vblank_delay mechanism v2: apply limits only when needed (VRR TG vs. Legacy TG) Bspec: 69897 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com> Link: https://lore.kernel.org/r/20250423102704.1368310-1-jouni.hogander@intel.com
2025-04-28drm/i915/alpm: Check for alpm support before accessing alpm registerAnimesh Manna
Currently, only EDP supports alpm. So, check for alpm support and prevent the DP connector from accessing the alpm register if doing so is unsupported. Fixes: acff6d6bded3 ("drm/i915/lobf: Add mutex for alpm update") Signed-off-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Link: https://lore.kernel.org/r/20250425132107.2926759-1-animesh.manna@intel.com
2025-04-25drm/i915/vga: Consolidate intel_vga_disable() callsVille Syrjälä
Currently we disable the VGA plane from various places, sometimes multiple times in the same init/resume sequence. Get rid of all this mess and do it just once. The most correct place seems to be just after intel_early_display_was() as that one applies various workarounds that need to be in place before we touch any planes (including the VGA plane). Actually, we do still have a second caller in vlv_display_power_well_init(). I think we still need that as the reset value of VGACNTR is 0x0 and thus technically the VGA plane will be (at least partially) enabled after the power well has been toggled. In both cases we have the necessary power reference already held (INIT power domain for load/resume case, and the display power well itself being what we need for vlv_display_power_well_init()). Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250417114454.12836-7-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2025-04-25drm/i915/vga: Nuke vga_redisable_power_on()Ville Syrjälä
Now that intel_vga_disable() itself will print a debug message, intel_vga_redisable_power_on() is completely redundant. Get rid of it. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250417114454.12836-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2025-04-25drm/i915/vga: Include the current pipe in the VGA disable debug messageVille Syrjälä
Add some debugs to the VGA plane disable so that we can at least see from the logs when it happens (and on which pipe). I was curious about this at some point when I was seeing some random underruns near the time when we disable the VGA plane, but I think in the end that turned out to be a red herring. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250417114454.12836-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2025-04-25drm/i915/vga: Extract intel_vga_regs.hVille Syrjälä
Extract the VGACNTR register definitions into their own header file, to declutter i915_reg.h a bit. v2: Group the register offst definitions together (Jani) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250417114454.12836-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2025-04-25drm/i915/vga: Add more VGACNTRL bitsVille Syrjälä
Define a pile of extra VGACNTRL bits. We don't really have any real use for most of these but nicer to have them all in one place rather than trawling the specs when one wants to know what's in there. I will have some real use for the CHV pipe select bits later. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250417114454.12836-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2025-04-25drm/i915/vga: Clean up VGACNTRL bitsVille Syrjälä
Use REG_BIT() & co. for the VGACNTRL register bits. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250417114454.12836-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2025-04-24scripts/kernel-doc.py: don't create *.pyc filesMauro Carvalho Chehab
As reported by Andy, kernel-doc.py is creating a __pycache__ directory at build time. Disable creation of __pycache__ for the libraries used by kernel-doc.py, when excecuted via the build system or via scripts/find-unused-docs.sh. Reported-by: Andy Shevchenko <andriy.shevchenko@intel.com> Closes: https://lore.kernel.org/linux-doc/Z_zYXAJcTD-c3xTe@black.fi.intel.com/ Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Message-ID: <158b962ed7cd104f7bbfe69f499ec1cc378864db.1745453655.git.mchehab+huawei@kernel.org>
2025-04-24drm/i915/display: Disintegrate sink alpm enable from psr with lobfAnimesh Manna
Make a generic alpm enable function for sink which can be used for PSR2/PR/Lobf. v1: Initial version. v2: Move code comment to intel_psr_needs_alpm(). [Jouni] Signed-off-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://lore.kernel.org/r/20250423092334.2294483-12-animesh.manna@intel.com
2025-04-24drm/i915/alpm: Add intel_psr_need_alpm() to simplify alpm checkAnimesh Manna
Simplify the alpm check which will be used multiple places like source configuration, sink enablement etc. Signed-off-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://lore.kernel.org/r/20250423092334.2294483-11-animesh.manna@intel.com
2025-04-24drm/i915/lobf: Check for sink error and disable LOBFAnimesh Manna
Disable LOBF/ALPM for any erroneous condition from sink side. v1: Initial version. v2: Add centralized alpm error handling. [Jouni] v3: Improve debug print. [Jouni] v4: Disable alpm permanently for sink error. [Jouni] Signed-off-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://lore.kernel.org/r/20250423092334.2294483-10-animesh.manna@intel.com
2025-04-24drm/i915/lobf: Add mutex for alpm updateAnimesh Manna
The ALPM_CTL can be updated from different context, so add mutex to sychonize the update. Signed-off-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://lore.kernel.org/r/20250423092334.2294483-9-animesh.manna@intel.com
2025-04-24drm/i915/lobf: Add debug interface for lobfAnimesh Manna
Add an interface in debugfs which will help in debugging LOBF feature. v1: Initial version. v2: - Remove FORCE_EN flag. [Jouni] - Change prefix from I915 to INTEL. [Jani] - Use u8 instead of bool for lobf-debug flag. [Jani] v3: - Use intel_connector instead of display. [Jani] - Remove edp connector check as it was already present in caller function. [Jani] - Remove loop of searching edp encoder which is directly accessible from intel_connector. [Jani] v4: - Simplify alpm debug to bool instead of bit-mask. [Jani] v5: - Remove READ_ONCE(). [Jani] - Modify variable name to *_disable_*. [Jouni] v6: Improved debug print. [Jouni] Signed-off-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://lore.kernel.org/r/20250423092334.2294483-8-animesh.manna@intel.com
2025-04-24drm/i915/lobf: Update lobf if any change in dependent parametersAnimesh Manna
For every commit the dependent condition for LOBF is checked and accordingly update has_lobf flag which will be used to update the ALPM_CTL register during commit. v1: Initial version. v2: Avoid reading h/w register without has_lobf check. [Jani] v3: Update LOBF in post plane update instead of separate function. [Jouni] v4: - Add lobf disable print. [Jouni] - Simplify condition check for enabling/disabling lobf. [Jouni] v5: Disable LOBF in pre_plane_update(). [Jouni] v6: use lobf flag of old_crtc_state and write 0 into ALPM_CTL. [Jouni] Signed-off-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://lore.kernel.org/r/20250423092334.2294483-7-animesh.manna@intel.com
2025-04-24drm/i915/lobf: Add fixed refresh rate check in compute_config()Animesh Manna
LOBF can be enabled with vrr fixed rate mode, so add check if vmin = vmax = flipline in compute_config(). Signed-off-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://lore.kernel.org/r/20250423092334.2294483-6-animesh.manna@intel.com
2025-04-24drm/i915/lobf: Disintegrate alpm_disable from psr_disableAnimesh Manna
Currently clearing of alpm registers is done through psr_disable() which is always not correct, without psr also alpm can exist. So dis-integrate alpm_disable() from psr_disable(). v1: Initial version. v2: - Remove h/w register read from alpm_disable(). [Jani] Signed-off-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://lore.kernel.org/r/20250423092334.2294483-5-animesh.manna@intel.com
2025-04-24drm/i915/lobf: Add debug print for LOBFAnimesh Manna
Lobf is enabled part of ALPM configuration and if has_lobf is set to true respective bit for LOBF will be set. Add debug print while setting the bitfield of LOBF. Signed-off-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://lore.kernel.org/r/20250423092334.2294483-4-animesh.manna@intel.com
2025-04-24drm/i915/lobf: Add lobf enablement in post plane updateAnimesh Manna
Enablement of LOBF is added in post plane update whenever has_lobf flag is set. As LOBF can be enabled in non-psr case as well so adding in post plane update. There is no change of configuring alpm with psr path. v1: Initial version. v2: Use encoder-mask to find the associated encoder from crtc-state. [Jani] v3: Remove alpm_configure from intel_psr.c. [Jouni] Signed-off-by: Animesh Manna <animesh.manna@intel.com> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> Link: https://lore.kernel.org/r/20250423092334.2294483-3-animesh.manna@intel.com
2025-04-24drm/i915/alpm: use variable from intel_crtc_state instead of intel_psrJouni Högander
Currently code is making assumption that PSR is enabled when intel_alpm_configure is called. This doesn't work if alpm is configured before PSR is enabled. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Animesh Manna <animesh.manna@intel.com> Signed-off-by: Animesh Manna <animesh.manna@intel.com> Link: https://lore.kernel.org/r/20250423092334.2294483-2-animesh.manna@intel.com
2025-04-24drm/i915/reg: Add/remove some extra blank linesJani Nikula
Add/remove some blank lines to/from i915_reg.h primarily to help the scripted refactoring coming up, separating unrelated registers and keeping the comments together. v2: Also add some extra blank lines Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> # v1 Link: https://lore.kernel.org/r/20250423100213.720585-2-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-24drm/i915/reg: use REG_BIT and friends to define DP registersJani Nikula
Define the DP register contents using the REG_BIT, REG_GENMASK, etc. macros. Ditch the unhelpful comments. Rename eDP related register content macros to have EDP_ prefix. Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250423100213.720585-1-jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-04-23drm/i915/display: Rename vblank DC workaround functions and variablesJouni Högander
We have extended using vblank DC workaround mechanism for Wa_16025596647. Rename related functions and variables: vblank_wa_num_pipes -> vblank_enable_count vblank_dc_work -> vblank_notify_work intel_display_vblank_dc_work -> intel_display_vblank_notify_work Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-14-jouni.hogander@intel.com
2025-04-23drm/i915/display: Rename intel_psr_needs_block_dc_vblankJouni Högander
Scope of intel_psr_needs_block_dc_vblank has changed now. Rename it as intel_psr_needs_vblank_notification. Also rename intel_crtc::block_dc_for_vblank as intel_crtc:vblank_psr_notify Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-13-jouni.hogander@intel.com
2025-04-23drm/i915/psr: Apply underrun on PSR idle workaroundJouni Högander
This patch is applying workaround for underrun on idle PSR HW issue (Wa_16025596647) when PSR is getting enabled. It uses vblank enable/disable status, DC5/6 enabled disabled and enabled pipes count information made available. This patch is also adding calls to dc5/dc6, vblank enable/disable and pipe enable/disable notification functions as needed. intel_psr_needs_block_dc_vblank is modified to get vblank enable/disable notification on PSR capable system. v2: use intel_dmc interface instead of directly writing dmc register Bspec: 74151 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-12-jouni.hogander@intel.com
2025-04-23drm/i915/dmc: Add interface to control start of PKG C-state exitJouni Högander
Add interface to control if package C exit starts at the start of the undelayed vblank. This is needed to implement workaround for underrun on idle PSR HW issue (Wa_16025596647). Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-11-jouni.hogander@intel.com
2025-04-23drm/i915/psr: Add interface to notify PSR of vblank enable/disableJouni Högander
To implement Wa_16025596647 we need to get notification of vblank interrupt enable/disable. Add new interface to PSR code for this notification. Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-10-jouni.hogander@intel.com
2025-04-23drm/i915/psr: Add mechanism to notify PSR of DC5/6 enable disableJouni Högander
We need to apply/remove workaround for underrun on idle PSR HW issue (Wa_16025596647) when DC5/6 is enabled/disabled. This patch implements mechanism to notify PSR about DC5/6 enable/disable and applies/removes the workaround using this notification. Bspec: 74115 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-9-jouni.hogander@intel.com
2025-04-23drm/i915/psr: Add mechanism to notify PSR of pipe enable/disableJouni Högander
We need to apply/remove workaround for underrun on idle PSR HW issue (Wa_16025596647) when new pipe is enabled or pipe is getting disabled. This patch implements mechanism to notify PSR about pipe enable/disable and applies/removes the workaround using this notification. Bspec: 74151 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-8-jouni.hogander@intel.com
2025-04-23drm/i915/psr: Block PKG C-State when enabling PSRJouni Högander
Block PKG C-State when enabling PSR when enabling PSR as described in workaround for underrun on idle PSR HW issue (Wa_16025596647). v2: use intel_dmc_block_pkgc instead of directly writing dmc register Bspec: 74151 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-7-jouni.hogander@intel.com
2025-04-23drm/i915/dmc: Add interface to block PKG C-stateJouni Högander
Add interface to block PKG C-state. This is needed to implement workaround for underrun on idle PSR HW issue (Wa_16025596647). Bspec: 74151 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-6-jouni.hogander@intel.com
2025-04-23drm/i915/dmc: Add PIPEDMC_BLOCK_PKGC_SW definitionsJouni Högander
We need PIPEDMC_BLOCK_PKGC_SW definitions to implement workaround for underrun on idle PSR HW issue (Wa_16025596647). Add PIPEDMC_BLOCK_PKGC_SW register definitions. Bspec: 71265 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-5-jouni.hogander@intel.com
2025-04-23drm/i915/dmc: Add PIPEDMC_EVT_CTL register definitionJouni Högander
To implement workaround for underrun on idle PSR HW issue (Wa_16025596647) we need PIPEDMC_EVT_CTL_4 register. Add PIPEDMC_EVT_CTL_4 register definitions. Bspec: 67576 Signed-off-by: Jouni Högander <jouni.hogander@intel.com> Reviewed-by: Mika Kahola <mika.kahola@intel.com> Link: https://lore.kernel.org/r/20250414100508.1208774-4-jouni.hogander@intel.com
generated by cgit (git 2.34.1) at 2025-07-16 10:26:37 +0000