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2025-05-13gpu: nova-core: fix layout of NV_PMC_BOOT_0Alexandre Courbot
The layout of NV_PMC_BOOT_0 has two small issues: - The "chipset" field, while useful to identify a chip, is actually an aggregate of two distinct fields named "architecture" and "implementation". - The "architecture" field is split, with its MSB being at a different location than the rest of its bits. Redefine the register layout to match its actual definition as provided by OpenRM and expose the fully-constructed "architecture" field through our own "Architecture" type. The "chipset" pseudo-field is also useful to have, so keep providing it. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Link: https://lore.kernel.org/r/20250507-nova-frts-v3-6-fcb02749754d@nvidia.com [ Use Result from kernel::prelude. - Danilo ] Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2025-05-13gpu: nova-core: define registers layout using helper macroAlexandre Courbot
Add the register!() macro, which defines a given register's layout and provide bit-field accessors with a way to convert them to a given type. This macro will allow us to make clear definitions of the registers and manipulate their fields safely. The long-term goal is to eventually move it to the kernel crate so it can be used by other drivers as well, but it was agreed to first land it into nova-core and make it mature there. To illustrate its usage, use it to define the layout for the Boot0 (renamed to NV_PMC_BOOT_0 to match OpenRM's naming scheme) and take advantage of its accessors. Suggested-by: Danilo Krummrich <dakr@kernel.org> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Link: https://lore.kernel.org/r/20250507-nova-frts-v3-5-fcb02749754d@nvidia.com [ Fix typo in commit message. - Danilo ] Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2025-05-13gpu: nova-core: take bound device in Gpu::newAlexandre Courbot
We will need to perform things like allocating DMA memory during device creation, so make sure to take the device context that will allow us to perform these actions. This also allows us to use Devres::access to obtain the BAR without holding a RCU lock. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Link: https://lore.kernel.org/r/20250507-nova-frts-v3-4-fcb02749754d@nvidia.com Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2025-05-13gpu: nova-core: add missing GA100 definitionAlexandre Courbot
linux-firmware contains a directory for GA100, and it is a defined chipset in Nouveau. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Link: https://lore.kernel.org/r/20250507-nova-frts-v3-3-fcb02749754d@nvidia.com Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2025-05-13gpu: nova-core: derive useful traits for ChipsetAlexandre Courbot
We will commonly need to compare chipset versions, so derive the ordering traits to make that possible. Also derive Copy and Clone since passing Chipset by value will be more efficient than by reference. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Link: https://lore.kernel.org/r/20250507-nova-frts-v3-2-fcb02749754d@nvidia.com Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2025-05-13PM: sleep: Introduce pm_suspend_in_progress()Rafael J. Wysocki
Introduce pm_suspend_in_progress() to be used for checking if a system- wide suspend or resume transition is in progress, instead of comparing pm_suspend_target_state directly to PM_SUSPEND_ON, and use it where applicable. No intentional functional impact. Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> Link: https://patch.msgid.link/2020901.PYKUYFuaPT@rjwysocki.net
2025-05-13Merge branch 'x86/msr' into x86/core, to resolve conflictsIngo Molnar
Conflicts: arch/x86/boot/startup/sme.c arch/x86/coco/sev/core.c arch/x86/kernel/fpu/core.c arch/x86/kernel/fpu/xstate.c Semantic conflict: arch/x86/include/asm/sev-internal.h Signed-off-by: Ingo Molnar <mingo@kernel.org>
2025-05-12drm: nova-drm: add initial driver skeletonDanilo Krummrich
Add the initial nova-drm driver skeleton. nova-drm is connected to nova-core through the auxiliary bus and implements the DRM parts of the nova driver stack. For now, it implements the fundamental DRM abstractions, i.e. creates a DRM device and registers it, exposing a three sample IOCTLs. DRM_IOCTL_NOVA_GETPARAM - provides the PCI bar size from the bar that maps the GPUs VRAM from nova-core DRM_IOCTL_NOVA_GEM_CREATE - creates a new dummy DRM GEM object and returns a handle DRM_IOCTL_NOVA_GEM_INFO - provides metadata for the DRM GEM object behind a given handle I implemented a small userspace test suite [1] that utilizes this interface. Link: https://gitlab.freedesktop.org/dakr/drm-test [1] Reviewed-by: Maxime Ripard <mripard@kernel.org> Acked-by: Dave Airlie <airlied@redhat.com> Link: https://lore.kernel.org/r/20250424160452.8070-3-dakr@kernel.org [ Kconfig: depend on DRM=y rather than just DRM. - Danilo ] Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2025-05-12gpu: nova-core: register auxiliary device for nova-drmDanilo Krummrich
Register an auxiliary device for nova-drm. For now always use zero for the auxiliary device's ID; we don't use it yet anyways. However, once it lands, we should switch to XArray. Acked-by: Dave Airlie <airlied@redhat.com> Link: https://lore.kernel.org/r/20250424160452.8070-2-dakr@kernel.org Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2025-05-12drm/msm/dp: Introduce link training per-segment for LTTPRsAleksandrs Vinarskis
DisplayPort requires per-segment link training when LTTPR are switched to non-transparent mode, starting with LTTPR closest to the source. Only when each segment is trained individually, source can link train to sink. Implement per-segment link traning when LTTPR(s) are detected, to support external docking stations. On higher level, changes are: * Pass phy being trained down to all required helpers * Run CR, EQ link training per phy * Set voltage swing, pre-emphasis levels per phy Since at least some LTTPRs (eg. Parade PS8830) do not correctly report voltage-swing, pre-emphasis level 3 support, always assume level 3 is supported. This is permitted under DP 2.1(a) section 3.6.7.2 stating that LTTPR shall set its transmitter levels as close as possible to those requested by the DPTX, if the DPTX sets the voltage swing or pre-emphasis to a level that the LTTPR does not support. It shall be noted that LTTPR’s level choosing is implementation-specific. This ensures successful link training both when connected directly to the monitor (single LTTPR onboard most X1E laptops) and via the docking station (at least two LTTPRs). Fixes: 72d0af4accd9 ("drm/msm/dp: Add support for LTTPR handling") Tested-by: Jessica Zhang <quic_jesszhan@quicinc.com> # SA8775P Tested-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Rob Clark <robdclark@gmail.com> Tested-by: Stefan Schmidt <stefan.schmidt@linaro.org> Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/652305/ Link: https://lore.kernel.org/r/20250507230113.14270-5-alex.vinarskis@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/dp: Prepare for link training per-segment for LTTPRsAleksandrs Vinarskis
Per-segment link training requires knowing the number of LTTPRs (if any) present. Store the count during LTTPRs' initialization. Fixes: 72d0af4accd9 ("drm/msm/dp: Add support for LTTPR handling") Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Tested-by: Jessica Zhang <quic_jesszhan@quicinc.com> # SA8775P Tested-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Rob Clark <robdclark@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/652306/ Link: https://lore.kernel.org/r/20250507230113.14270-4-alex.vinarskis@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/dp: Account for LTTPRs capabilitiesAleksandrs Vinarskis
Take into account LTTPR capabilities when selecting maximum allowed link rate, number of data lines. Fixes: 72d0af4accd9 ("drm/msm/dp: Add support for LTTPR handling") Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Tested-by: Jessica Zhang <quic_jesszhan@quicinc.com> # SA8775P Tested-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Rob Clark <robdclark@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/652302/ Link: https://lore.kernel.org/r/20250507230113.14270-3-alex.vinarskis@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/dp: Fix support of LTTPR initializationAleksandrs Vinarskis
Initialize LTTPR before msm_dp_panel_read_sink_caps, as DPTX shall (re)read DPRX caps after LTTPR detection, as required by DP 2.1a, Section 3.6.7.6.1. Fixes: 72d0af4accd9 ("drm/msm/dp: Add support for LTTPR handling") Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Tested-by: Jessica Zhang <quic_jesszhan@quicinc.com> # SA8775P Tested-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Rob Clark <robdclark@gmail.com> Patchwork: https://patchwork.freedesktop.org/patch/652301/ Link: https://lore.kernel.org/r/20250507230113.14270-2-alex.vinarskis@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/dpu: remove DPU_CTL_SPLIT_DISPLAY from SAR2130P CTL blocksDmitry Baryshkov
Follow the changes in the commit a2649952f66e ("drm/msm/dpu: remove DPU_CTL_SPLIT_DISPLAY from CTL blocks on DPU >= 5.0") and remove DPU_CTL_SPLIT_DISPLAY from the CTL blocks on the SAR2130P platform. Single CTL is used for all interfaces used by a single path Fixes: 178575173472 ("drm/msm/dpu: add catalog entry for SAR2130P") Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/651883/ Link: https://lore.kernel.org/r/20250506-dpu-sar2130p-no-split-display-v1-1-b619c0fddea5@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/dpu: Add handling of LM_6 and LM_7 bits in pending flush maskKrzysztof Kozlowski
MDSS/MDP v12 comes with new bits in flush registers (e.g. MDP_CTL_0_FLUSH) for Layer Mixer 6 and 7. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651260/ Link: https://lore.kernel.org/r/20250430-b4-sm8750-display-v5-13-8cab30c3e4df@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/dpu: Add LM_7, DSC_[67], PP_[67] and MERGE_3D_5Krzysztof Kozlowski
Add IDs for new blocks present in MDSS/MDP v12 for LM, DSC, PINGPONG and MERGE_3D blocks. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651262/ Link: https://lore.kernel.org/r/20250430-b4-sm8750-display-v5-12-8cab30c3e4df@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/dpu: Drop useless commentsKrzysztof Kozlowski
Drop comments about SoC before each 'struct dpu_lm_sub_blks' for given SoC because it's duplicating the actual name of structure. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651251/ Link: https://lore.kernel.org/r/20250430-b4-sm8750-display-v5-11-8cab30c3e4df@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/dpu: Clear CTL_FETCH_PIPE_ACTIVE before blend setupKrzysztof Kozlowski
Before blend setup, all existing blend stages are cleared, so shall be active fetch pipes. Fixes: b3652e87c03c ("drm/msm/disp/dpu1: add support to program fetch active in ctl path") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651263/ Link: https://lore.kernel.org/r/20250430-b4-sm8750-display-v5-10-8cab30c3e4df@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/dpu: Clear CTL_FETCH_PIPE_ACTIVE on ctl_path resetKrzysztof Kozlowski
Resetting entire CTL path should also include resetting active fetch pipes. Fixes: e1a950eec256 ("drm/msm/dpu: add reset_intf_cfg operation for dpu_hw_ctl") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651252/ Link: https://lore.kernel.org/r/20250430-b4-sm8750-display-v5-9-8cab30c3e4df@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/dpu: Clear CTL_FETCH_PIPE_ACTIVE on mixer resetKrzysztof Kozlowski
Resetting mixers should also include resetting active fetch pipes. Fixes: ae4d721ce100 ("drm/msm/dpu: add an API to reset the encoder related hw blocks") Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651246/ Link: https://lore.kernel.org/r/20250430-b4-sm8750-display-v5-8-8cab30c3e4df@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/dpu: Add missing "fetch" name to set_active_pipes()Krzysztof Kozlowski
The set_active_pipes() callback configures CTL_FETCH_PIPE_ACTIVE and newer DPU v12.0 comes with CTL_PIPE_ACTIVE, thus rename it to set_active_fetch_pipes() to better match the purpose. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651261/ Link: https://lore.kernel.org/r/20250430-b4-sm8750-display-v5-7-8cab30c3e4df@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/hdmi: wire in hpd_enable/hpd_disable bridge opsDmitry Baryshkov
The HDMI driver already has msm_hdmi_hpd_enable() and msm_hdmi_hpd_disable() functions. Wire them into the msm_hdmi_bridge_funcs, so that HPD can be enabled and disabled dynamically rather than always having HPD events generation enabled. Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250505-fd-hdmi-hpd-v5-13-48541f76318c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/hdmi: ensure that HDMI is up if HPD is requestedDmitry Baryshkov
The HDMI block needs to be enabled to properly generate HPD events. Make sure it is not turned off in the disable paths if HPD delivery is enabled. Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651722/ Link: https://lore.kernel.org/r/20250505-fd-hdmi-hpd-v5-12-48541f76318c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/hdmi: expand the HDMI_CFG macroDmitry Baryshkov
Expand the HDMI_CFG() macro in HDMI config description. It has no added value other than hiding some boilerplate declarations. Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651724/ Link: https://lore.kernel.org/r/20250505-fd-hdmi-hpd-v5-11-48541f76318c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/hdmi: rename hpd_clks to pwr_clksDmitry Baryshkov
As these clocks are now used in the runtime PM callbacks, they have no connection to 'HPD'. Rename corresponding fields to follow clocks purpose, to power up the HDMI controller. Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651720/ Link: https://lore.kernel.org/r/20250505-fd-hdmi-hpd-v5-10-48541f76318c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/hdmi: implement proper runtime PM handlingDmitry Baryshkov
It is completely not obvious, but the so-called 'hpd' clocks and regulators are required for the HDMI host to function properly. Merge pwr and hpd regulators. Use regulators, clocks and pinctrl to implement proper runtime PM callbacks. Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651715/ Link: https://lore.kernel.org/r/20250505-fd-hdmi-hpd-v5-9-48541f76318c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/hdmi: add runtime PM calls to DDC transfer functionDmitry Baryshkov
We must be sure that the HDMI controller is powered on, while performing the DDC transfer. Add corresponding runtime PM calls to msm_hdmi_i2c_xfer(). Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651727/ Link: https://lore.kernel.org/r/20250505-fd-hdmi-hpd-v5-8-48541f76318c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/hdmi: switch to pm_runtime_resume_and_get()Dmitry Baryshkov
The pm_runtime_get_sync() function is a bad choise for runtime power management. Switch HDMI driver to pm_runtime_resume_and_get() and add proper error handling, while we are at it. Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651713/ Link: https://lore.kernel.org/r/20250505-fd-hdmi-hpd-v5-7-48541f76318c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/hdmi: switch to clk_bulk APIDmitry Baryshkov
The last platform using legacy clock names for HDMI block (APQ8064) switched to new clock names in 5.16. It's time to stop caring about old DT, drop hand-coded helpers and switch to clk_bulk_* API. Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651716/ Link: https://lore.kernel.org/r/20250505-fd-hdmi-hpd-v5-6-48541f76318c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/hdmi: drop clock frequency assignmentDmitry Baryshkov
The only clock which has frequency being set through hpd_freqs is the "core" aka MDSS_HDMI_CLK clock. It always has the specified frequency, so we can drop corresponding clk_set_rate() call together with the hpd_freq infrastructure. Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651717/ Link: https://lore.kernel.org/r/20250505-fd-hdmi-hpd-v5-5-48541f76318c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/hdmi: simplify extp clock handlingDmitry Baryshkov
With the extp being the only "power" clock left, remove the surrounding loops and handle the extp clock directly. Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651710/ Link: https://lore.kernel.org/r/20250505-fd-hdmi-hpd-v5-4-48541f76318c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/hdmi: move the alt_iface clock to the hpd listDmitry Baryshkov
According to the vendor kernel [1] , the alt_iface clock should be enabled together with the rest of HPD clocks, to make HPD to work properly. [1] https://git.codelinaro.org/clo/la/kernel/msm-3.18/-/commit/e07a5487e521e57f76083c0a6e2f995414ac6d03 Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/651709/ Link: https://lore.kernel.org/r/20250505-fd-hdmi-hpd-v5-3-48541f76318c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/msm/hdmi: convert clock and regulator arrays to const arraysDmitry Baryshkov
As a preparation to the next patches convert 'static const char *' arrays to 'static const char * const', as required by the checkpatch.pl Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/651705/ Link: https://lore.kernel.org/r/20250505-fd-hdmi-hpd-v5-2-48541f76318c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-12drm/sitronix: move tiny Sitronix drivers to their own subdirMarcus Folkesson
We start to have support many Sitronix displays in the tiny directory, and we expect more to come. Move them to their own subdirectory. Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Suggested-by: Javier Martinez Canillas <javierm@redhat.com> Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com> Acked-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://lore.kernel.org/r/20250512-sitronix-v3-1-bbf6cc413698@gmail.com Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
2025-05-12drm/tiny: panel-mipi-dbi: Use drm_client_setup_with_fourcc()Fabio Estevam
Since commit 559358282e5b ("drm/fb-helper: Don't use the preferred depth for the BPP default"), RGB565 displays such as the CFAF240320X no longer render correctly: colors are distorted and the content is shown twice horizontally. This regression is due to the fbdev emulation layer defaulting to 32 bits per pixel, whereas the display expects 16 bpp (RGB565). As a result, the framebuffer data is incorrectly interpreted by the panel. Fix the issue by calling drm_client_setup_with_fourcc() with a format explicitly selected based on the display's bits-per-pixel value. For 16 bpp, use DRM_FORMAT_RGB565; for other values, fall back to the previous behavior. This ensures that the allocated framebuffer format matches the hardware expectations, avoiding color and layout corruption. Tested on a CFAF240320X display with an RGB565 configuration, confirming correct colors and layout after applying this patch. Cc: stable@vger.kernel.org Fixes: 559358282e5b ("drm/fb-helper: Don't use the preferred depth for the BPP default") Signed-off-by: Fabio Estevam <festevam@denx.de> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://lore.kernel.org/r/20250417103458.2496790-1-festevam@gmail.com
2025-05-12Merge tag 'amd-drm-next-6.16-2025-05-09' of ↵Dave Airlie
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-6.16-2025-05-09: amdgpu: - IPS fixes - DSC cleanup - DC Scaling updates - DC FP fixes - Fused I2C-over-AUX updates - SubVP fixes - Freesync fix - DMUB AUX fixes - VCN fix - Hibernation fixes - HDP fixes - DCN 2.1 fixes - DPIA fixes - DMUB updates - Use drm_file_err in amdgpu - Enforce isolation updates - Use new dma_fence helpers - USERQ fixes - Documentation updates - Misc code cleanups - SR-IOV updates - RAS updates - PSP 12 cleanups amdkfd: - Update error messages for SDMA - Userptr updates drm: - Add drm_file_err function dma-buf: - Add a helper to sort and deduplicate dma_fence arrays From: Alex Deucher <alexander.deucher@amd.com> Link: https://lore.kernel.org/r/20250509230951.3871914-1-alexander.deucher@amd.com Signed-off-by: Dave Airlie <airlied@redhat.com>
2025-05-10drm/msm/adreno: Remove MODULE_FIRMWARE()'sRob Clark
The driver handles the case where gpu fw is not in the initrd. OTOH it doesn't always handle the case where _some_ fw is in the initrd, but others are not. In particular the zap fw tends to be signed with an OEM specific key, so the paths/names differ across devices with the same SoC/GPU, so we cannot sanely list them with MODULE_FIRMWARE(). So MODULE_FIRMWARE() just ends up causing problems without actually solving anything. Remove them! Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/652195/
2025-05-10drm/msm/a6xx: Disable rgb565_predicator on Adreno 7c3Konrad Dybcio
This feature is supposed to be enabled with UBWC v4 or later. Implementations of this SKU feature an effective UBWC version of 3, so disable it, in line with the BSP kernel. Reported-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com> Fixes: 192f4ee3e408 ("drm/msm/a6xx: Add support for Adreno 7c Gen 3 gpu") Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/651759/ Signed-off-by: Rob Clark <robdclark@chromium.org>
2025-05-10Merge tag 'drm-misc-next-2025-05-08' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/misc/kernel into drm-next drm-misc-next for v6.16-rc1: Cross-subsystem Changes: - Change vsprintf %p4cn to %p4chR, remove %p4cn. Core Changes: - Documentation updates (fb rendering, actual_brightness) Driver Changes: - Small fixes to appletbdrm, panthor, st7571-i2c, rockchip, renesas, panic handler, gpusvm, vkms, panel timings. - Add AUO B140QAN08.H, BOE NE140WUM-N6S, CSW MNE007QS3-8, BOE TD4320 panels. - Convert rk3066_hdmi to bridge driver. - Improve HPD on anx7625. - Speed up loading tegra firmware, and other small fixes to tegra & host1x. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://lore.kernel.org/r/5428be12-fc08-4e28-8c5f-85d73b8a7e04@linux.intel.com
2025-05-09Merge tag 'rust-fixes-6.15-2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/ojeda/linux Pull rust fixes from Miguel Ojeda: - Make CFI_AUTO_DEFAULT depend on !RUST or Rust >= 1.88.0 - Clean Rust (and Clippy) lints for the upcoming Rust 1.87.0 and 1.88.0 releases - Clean objtool warning for the upcoming Rust 1.87.0 release by adding one more noreturn function * tag 'rust-fixes-6.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/ojeda/linux: x86/Kconfig: make CFI_AUTO_DEFAULT depend on !RUST or Rust >= 1.88 rust: clean Rust 1.88.0's `clippy::uninlined_format_args` lint rust: clean Rust 1.88.0's warning about `clippy::disallowed_macros` configuration rust: clean Rust 1.88.0's `unnecessary_transmutes` lint rust: allow Rust 1.87.0's `clippy::ptr_eq` lint objtool/rust: add one more `noreturn` Rust function for Rust 1.87.0
2025-05-10Merge tag 'drm-intel-next-2025-05-08' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/i915/kernel into drm-next Non-display related: - Fix undefined reference to `intel_pxp_gsccs_is_ready_for_sessions' Display related: - More work towards display separation (Jani) - Stop writing VRR_CTL_IGN_MAX_SHIFT for MTL onwards (Jouni) - DSC checks for 3 engines (Ankit) - Add link rate and lane count to i915_display_info (Khaled) - PSR fixes and workaround for underrun on idle (Jouni) - LOBF enablement and ALMP fixes (Animesh) - Clean up VGA plane handling (Ville) - Use an intel_connector pointer everywhere (Imre) - Fix warning for coffeelake on SunrisePoint PCH (Jiajia) - Rework/Correction on minimum hblank calculation (Arun) - Dmesg clean up (Jani) - Add a couple of simple display workarounds (Ankit, Vinod) - Refactor HDCP GSC (Jani) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://lore.kernel.org/r/aByyL3bEufPu79OM@intel.com
2025-05-10Merge tag 'drm-xe-next-2025-05-08' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/xe/kernel into drm-next UAPI Changes: - Expose PCIe link downgrade attributes (Raag) Cross-subsystem Changes: Core Changes: - gpusvm has_dma_mapping fix (Dafna) Driver Changes: - Forcewake hold fix (Tejas) - Fix guc_info debugfs for VFs (Daniele) - Fix devcoredump chunk alignment calculation (Arnd) - Don't print timedout job message on killed exec queues (Matt Brost) - Don't flush the GSC worker from the reset path (Daniele) - Use copy_from_user() instead of __copy_from_user() (Harish) - Only flush SVM garbage collector if CONFIG_DRM_XE_GPUSVM (Shuicheng) - Fix forcewake vs runtime pm ref release ordering (Shuicheng) - Move xe_device_sysfs_init() to xe_device_probe() (Raag) - Append PCIe Gen5 limitations to xe_firmware document (Raag) Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thomas Hellstrom <thomas.hellstrom@linux.intel.com> Link: https://lore.kernel.org/r/aBzUwbzCzz7Qo7fA@fedora
2025-05-10Merge tag 'drm-intel-fixes-2025-05-09' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/i915/kernel into drm-fixes drm/i915 fixes for v6.15-rc6: - Fix oops on resume after disconnecting DP MST sinks during suspend - Fix SPLC num_waiters refcounting Signed-off-by: Dave Airlie <airlied@redhat.com> From: Jani Nikula <jani.nikula@intel.com> Link: https://lore.kernel.org/r/87tt5umeaw.fsf@intel.com
2025-05-10Merge tag 'drm-xe-fixes-2025-05-09' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/xe/kernel into drm-fixes Driver Changes: - Prevent PF queue overflow - Hold all forcewake during mocs test - Remove GSC flush on reset path - Fix forcewake put on error path - Fix runtime warning when building without svm Signed-off-by: Dave Airlie <airlied@redhat.com> From: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://lore.kernel.org/r/jffqa56f2zp4i5ztz677cdspgxhnw7qfop3dd3l2epykfpfvza@q2nw6wapsphz
2025-05-09drm/meson: Use 1000ULL when operating with mode->clockI Hsin Cheng
Coverity scan reported the usage of "mode->clock * 1000" may lead to integer overflow. Use "1000ULL" instead of "1000" when utilizing it to avoid potential integer overflow issue. Link: https://scan5.scan.coverity.com/#/project-view/10074/10063?selectedIssue=1646759 Signed-off-by: I Hsin Cheng <richard120310@gmail.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Fixes: 1017560164b6 ("drm/meson: use unsigned long long / Hz for frequency types") Link: https://lore.kernel.org/r/20250505184338.678540-1-richard120310@gmail.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2025-05-09drm/i915/display: Indexed 8bit format does not support async flipArun R Murthy
Async flip is not supported with Indexed 8 bit format as it depends on LUT and can't be updated atomically. Note: This may change the alignment for C8 framebuffers on some platforms. Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250407-asyn-v13-5-b93ef83076c5@intel.com
2025-05-09drm/i915/display: Add i915 hook for format_mod_supported_asyncArun R Murthy
Hook up the newly added plane function pointer format_mod_supported_async to populate the modifiers/formats supported by asynchronous flips. v5: Correct the if condition for modifier support check (Chaitanya) v6: Replace uint32_t/uint64_t with u32/u64 (Jani) v7: Move plannar check from intel_async_flip_check_hw() to intel_plane_format_mod_supported_async() (Ville) v8: In case of error print format/modifier (Chaitanya) v9: Exclude C8 format as its not supported by hardware v10: filter only planar formats move changes in can_async_flip to new patch (Ville) Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250407-asyn-v13-4-b93ef83076c5@intel.com
2025-05-09drm/i915/display: Acomodate format check in intel_plane_can_async_flip()Arun R Murthy
The function intel_plane_can_async_flip() checks for async supported modifier, add format support check also in the same function. Note: on ADL the surface base addr is required to be 16k aligned and if not might generate DMAR and GGTT faults leading to glitches. This patch changes the 16k alignment to 4k for planar formats. v11: Move filtering Indexed 8bit to a separate patch (Ville) v12: correct the commit msg and remove unwanted debug print (Ville) Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250407-asyn-v13-3-b93ef83076c5@intel.com
2025-05-09drm/plane: modify create_in_formats to acommodate asyncArun R Murthy
create_in_formats creates the list of supported format/modifiers for synchronous flips, modify the same function so as to take the format_mod_supported as argument and create list of format/modifier for async as well. v5: create_in_formats can return -ve value in failure case, correct the if condition to check the creation of blob <Chaitanya> Dont add the modifier for which none of the formats is not supported. v6: Remove the code for masking the unsupported modifiers as UMD can leave with it. (Naveen/Chaitanya) v7: Retain the unsupported modifiers, userspace should have no impact, return pointer to blob instead of blob_id(Ville) Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Acked-by: Xaver Hugl <xaver.hugl@kde.org> Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Naveen Kumar <naveen1.kumar@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250407-asyn-v13-2-b93ef83076c5@intel.com
2025-05-09drm/plane: Add new plane property IN_FORMATS_ASYNCArun R Murthy
There exists a property IN_FORMATS which exposes the plane supported modifiers/formats to the user. In some platforms when asynchronous flip are used all of modifiers/formats mentioned in IN_FORMATS are not supported. This patch adds a new plane property IN_FORMATS_ASYNC to expose the async flip supported modifiers/formats so that user can use this information ahead and do flip with unsupported formats/modifiers. This will save flip failures. Add a new function pointer similar to format_mod_supported specifically for asynchronous flip. v2: Remove async variable from drm_plane (Ville) v3: Add new function pointer for async (Ville) v5: Typo corrected in commit message & some correction in the kernel documentation. (Chaitanya) v7: Place IN_FORMATS_ASYNC next to IN_FORMATS (Ville) v8: replace uint32_t with u32 and uint64_t with u64 (Chaitanya) Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com> Acked-by: Xaver Hugl <xaver.hugl@kde.org> Acked-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Tested-by: Naveen Kumar <naveen1.kumar@intel.com> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com> Link: https://lore.kernel.org/r/20250407-asyn-v13-1-b93ef83076c5@intel.com
generated by cgit (git 2.34.1) at 2025-07-16 02:08:49 +0000