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path: root/drivers/net/phy
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2024-11-11net: phylink: move MLO_AN_FIXED resolve handling to if() statementRussell King (Oracle)
The switch() statement doesn't sit very well with the preceeding if() statements, and results in excessive indentation that spoils code readability. Begin cleaning this up by converting the MLO_AN_FIXED case to an if() statement. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://patch.msgid.link/E1t9RQk-002Fen-1A@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-11-11net: phylink: move manual flow control settingRussell King (Oracle)
Move the handling of manual flow control configuration to a common location during resolve. We currently evaluate this for all but fixed links. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://patch.msgid.link/E1t9RQe-002Feh-T1@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-11-11net: phy: aquantia: Add mdix config and reportingPaul Davey
Add support for configuring MDI-X state of PHY. Add reporting of resolved MDI-X state in status information. Tested on AQR113C. Signed-off-by: Paul Davey <paul.davey@alliedtelesis.co.nz> Link: https://patch.msgid.link/20241106222057.3965379-1-paul.davey@alliedtelesis.co.nz Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-11-07net: phy: remove genphy_config_eee_advertHeiner Kallweit
bcm_config_lre_aneg() doesn't use genphy_config_eee_advert() any longer. As this was the only user, we can remove genphy_config_eee_advert() now. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://patch.msgid.link/37da7f3e-b883-4c07-9881-b8c0516822b7@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-11-07net: phy: broadcom: use genphy_c45_an_config_eee_aneg in bcm_config_lre_anegHeiner Kallweit
bcm_config_lre_aneg() is the only user of genphy_config_eee_advert(), therefore use genphy_c45_an_config_eee_aneg() instead. The resulting functionality is equivalent, and bcm_config_lre_aneg() follows the structure of __genphy_config_aneg(). In a follow-up step genphy_config_eee_advert() can be removed. Note: We preserve the current behavior to ignore errors. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://patch.msgid.link/6e5cd4ab-28bb-4d82-b449-fec85f3d1e8a@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-11-07net: phy: export genphy_c45_an_config_eee_anegHeiner Kallweit
We'll use this function in bcm_config_lre_aneg(), therefore export it. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://patch.msgid.link/02bd7c39-7413-4433-bafc-a276089bd292@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-11-07net: phy: make genphy_c45_write_eee_adv() staticHeiner Kallweit
genphy_c45_write_eee_adv() isn't used outside phy-c45.c, so make it static. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://patch.msgid.link/d23bd784-44e6-4a15-af3a-b37379156521@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-11-07Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski
Cross-merge networking fixes after downstream PR (net-6.12-rc7). Conflicts: drivers/net/ethernet/freescale/enetc/enetc_pf.c e15c5506dd39 ("net: enetc: allocate vf_state during PF probes") 3774409fd4c6 ("net: enetc: build enetc_pf_common.c as a separate module") https://lore.kernel.org/20241105114100.118bd35e@canb.auug.org.au Adjacent changes: drivers/net/ethernet/ti/am65-cpsw-nuss.c de794169cf17 ("net: ethernet: ti: am65-cpsw: Fix multi queue Rx on J7") 4a7b2ba94a59 ("net: ethernet: ti: am65-cpsw: Use tstats instead of open coded version") Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-11-06net: broadcom: use ethtool string helpersRosen Penev
The latter is the preferred way to copy ethtool strings. Avoids manually incrementing the pointer. Cleans up the code quite well. Signed-off-by: Rosen Penev <rosenp@gmail.com> Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://patch.msgid.link/20241104205317.306140-1-rosenp@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-11-06net: phy: respect cached advertising when re-enabling EEEHeiner Kallweit
If we remove modes from EEE advertisement and disable / re-enable EEE, then advertisement is set to all supported modes. I don't think this is what the user expects. So respect the cached advertisement and just fall back to all supported modes if cached advertisement is empty. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Link: https://patch.msgid.link/c75f7f8b-5571-429f-abd3-ce682d178a4b@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-11-05net: phy: ti: add PHY_RST_AFTER_CLK_EN flagDiogo Silva
DP83848 datasheet (section 4.7.2) indicates that the reset pin should be toggled after the clocks are running. Add the PHY_RST_AFTER_CLK_EN to make sure that this indication is respected. In my experience not having this flag enabled would lead to, on some boots, the wrong MII mode being selected if the PHY was initialized on the bootloader and was receiving data during Linux boot. Signed-off-by: Diogo Silva <diogompaissilva@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Fixes: 34e45ad9378c ("net: phy: dp83848: Add TI DP83848 Ethernet PHY") Link: https://patch.msgid.link/20241102151504.811306-1-paissilva@ld-100007.ds1.internal Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-11-03net: phy: use ethtool string helpersRosen Penev
These are the preferred way to copy ethtool strings. Avoids incrementing pointers all over the place. Signed-off-by: Rosen Penev <rosenp@gmail.com> Link: https://patch.msgid.link/20241029234641.11448-1-rosenp@gmail.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-31net: phy: dp83822: Configure RMII mode on DP83825 devicesErik Schumacher
Like the DP83826, the DP83825 can also be configured as an RMII master or slave via a control register. The existing function responsible for this configuration is renamed to a general dp8382x function. The DP83825 only supports RMII so nothing more needs to be configured. With this change, the dp83822_driver list is reorganized according to the device name. Signed-off-by: Erik Schumacher <erik.schumacher@iris-sensing.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/aa62d081804f44b5af0e8de2372ae6bfe1affd34.camel@iris-sensing.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-29net: phylink: simplify how SFP PHYs are attachedRussell King (Oracle)
There are a few issues with how SFP PHYs are attached: a) The phylink_sfp_connect_phy() and phylink_sfp_config_phy() code validates the configuration three times: 1. To discover the support/advertising masks that the PHY/PCS/MAC can support in order to select an interface. 2. To validate the selected interface. 3. When the PHY is brought up after being attached, another validation is done. This is needlessly complex. b) The configuration is set prior to the PHY being attached, which means we don't have the PHY available in phylink_major_config() for phylink_pcs_neg_mode() to make decisions upon. We have already added an extra step to validate the selected interface, so we can now move the attachment and bringup of the PHY earlier, inside phylink_sfp_config_phy(). This results in the validation at step 2 above becoming entirely unnecessary, so remove that too. Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Tested-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://patch.msgid.link/E1t3bcb-000c8H-3e@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-29net: phylink: validate sfp_select_interface() returned interfaceRussell King (Oracle)
Validate that the returned interface from sfp_select_interface() is supportable by the MAC/PCS. If it isn't, print an error and return the NA interface type. This is a preparatory step to reorganising how a PHY on a SFP module is handled. Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Tested-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://patch.msgid.link/E1t3bcV-000c8B-Vz@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-29net: phylink: add common validation for sfp_select_interface()Russell King (Oracle)
Whenever we call sfp_select_interface(), we check the returned value and print an error. There are two cases where this happens with the same message. Provide a common function to do this. Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Tested-by: Maxime Chevallier <maxime.chevallier@bootlin.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://patch.msgid.link/E1t3bcQ-000c85-S4@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-29net: phylink: simplify phylink_parse_fixedlink()Russell King (Oracle)
phylink_parse_fixedlink() wants to preserve the pause, asym_pause and autoneg bits in pl->supported. Rather than reading the bits into separate bools, zeroing pl->supported, and then setting them if they were previously set, use a mask and linkmode_and() to achieve the same result. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Simon Horman <horms@kernel.org> Link: https://patch.msgid.link/E1t3Fh5-000aQi-Nk@rmk-PC.armlinux.org.uk Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-25Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netPaolo Abeni
Cross-merge networking fixes after downstream PR. No conflicts and no adjacent changes. Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-22net: phy: marvell: Add mdix status reportingPaul Davey
Report MDI-X resolved state after link up. Tested on Linkstreet 88E6193X internal PHYs. Signed-off-by: Paul Davey <paul.davey@alliedtelesis.co.nz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20241017015026.255224-1-paul.davey@alliedtelesis.co.nz Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net: sfp: change quirks for Alcatel Lucent G-010S-PShengyu Qu
Seems Alcatel Lucent G-010S-P also have the same problem that it uses TX_FAULT pin for SOC uart. So apply sfp_fixup_ignore_tx_fault to it. Signed-off-by: Shengyu Qu <wiagn233@outlook.com> Link: https://patch.msgid.link/TYCPR01MB84373677E45A7BFA5A28232C98792@TYCPR01MB8437.jpnprd01.prod.outlook.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-20net: phy: realtek: add RTL8125D-internal PHYHeiner Kallweit
The first boards show up with Realtek's RTL8125D. This MAC/PHY chip comes with an integrated 2.5Gbps PHY with ID 0x001cc841. It's not clear yet whether there's an external version of this PHY and how Realtek calls it, therefore use the numeric id for now. Link: https://lore.kernel.org/netdev/2ada65e1-5dfa-456c-9334-2bc51272e9da@gmail.com/T/ Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Message-ID: <7d2924de-053b-44d2-a479-870dc3878170@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-20net: phy: mediatek-ge-soc: Propagate error code correctly in cal_cycle()SkyLake.Huang
This patch propagates error code correctly in cal_cycle() and improve with FIELD_GET(). Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> Reviewed-by: Simon Horman <horms@kernel.org> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-20net: phy: mediatek-ge-soc: Shrink line wrapping to 80 charactersSkyLake.Huang
This patch shrinks line wrapping to 80 chars. Also, in tx_amp_fill_result(), use FIELD_PREP() to prettify code. Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> Reviewed-by: Simon Horman <horms@kernel.org> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-20net: phy: mediatek-ge-soc: Fix coding styleSkyLake.Huang
This patch fixes spelling errors, re-arrange vars with reverse Xmas tree and remove unnecessary parens in mediatek-ge-soc.c. Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> Reviewed-by: Simon Horman <horms@kernel.org> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-19net: phy: dp83822: Fix reset pin definitionsMichel Alex
This change fixes a rare issue where the PHY fails to detect a link due to incorrect reset behavior. The SW_RESET definition was incorrectly assigned to bit 14, which is the Digital Restart bit according to the datasheet. This commit corrects SW_RESET to bit 15 and assigns DIG_RESTART to bit 14 as per the datasheet specifications. The SW_RESET define is only used in the phy_reset function, which fully re-initializes the PHY after the reset is performed. The change in the bit definitions should not have any negative impact on the functionality of the PHY. v2: - added Fixes tag - improved commit message Cc: stable@vger.kernel.org Fixes: 5dc39fd5ef35 ("net: phy: DP83822: Add ability to advertise Fiber connection") Signed-off-by: Alex Michel <alex.michel@wiedemann-group.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Message-ID: <AS1P250MB0608A798661549BF83C4B43EA9462@AS1P250MB0608.EURP250.PROD.OUTLOOK.COM> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-17net: phylink: remove "using_mac_select_pcs"Russell King (Oracle)
With DSA's implementation of the mac_select_pcs() method removed, we can now remove the detection of mac_select_pcs() implementation. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-17net: phylink: remove use of pl->pcs in phylink_validate_mac_and_pcs()Russell King (Oracle)
When the mac_select_pcs() method is not implemented, there is no way for pl->pcs to be set to a non-NULL value. This was here to support the old phylink_set_pcs() method which has been removed a few years ago. Simplify the code in phylink_validate_mac_and_pcs(). Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-17net: phylink: allow mac_select_pcs() to remove a PCSRussell King (Oracle)
phylink has historically not permitted a PCS to be removed. An attempt to permit this with phylink_set_pcs() resulted in comments indicating that there was no need for this. This behaviour has been propagated forward to the mac_select_pcs() approach as it was believed from these comments that changing this would be NAK'd. However, with mac_select_pcs(), it takes more code and thus complexity to maintain this behaviour, which can - and in this case has - resulted in a bug. If mac_select_pcs() returns NULL for a particular interface type, but there is already a PCS in-use, then we skip the pcs_validate() method, but continue using the old PCS. Also, it wouldn't be expected behaviour by implementers of mac_select_pcs(). Allow this by removing this old unnecessary restriction. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-17net: phy: realtek: merge the drivers for internal NBase-T PHY'sHeiner Kallweit
The Realtek RTL8125/RTL8126 NBase-T MAC/PHY chips have internal PHY's which are register-compatible, at least for the registers we use here. So let's use just one PHY driver to support all of them. These internal PHY's exist also as external C45 PHY's, but on the internal PHY's no access to MMD registers is possible. This can be used to differentiate between the internal and external version. As a side effect the drivers for two now external-only drivers don't require read_mmd/write_mmd hooks any longer. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Link: https://patch.msgid.link/c57081a6-811f-4571-ab35-34f4ca6de9af@gmail.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-17net: phy: realtek: clear 1000Base-T link partner advertisementDaniel Golle
Clear 1000Base-T link partner advertisement bits in Clause-45 read_status() function in case auto-negotiation is disabled or has not been completed. Signed-off-by: Daniel Golle <daniel@makrotopia.org> Link: https://patch.msgid.link/9dc9b47b2d675708afef3ad366bfd78eb584d958.1728565530.git.daniel@makrotopia.org Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-17net: phy: realtek: change order of calls in C22 read_status()Daniel Golle
Always call rtlgen_read_status() first, so genphy_read_status() which is called by it clears bits in case auto-negotiation has not completed. Also clear 10GBT link-partner advertisement bits in case auto-negotiation is disabled or has not completed. Suggested-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Golle <daniel@makrotopia.org> Link: https://patch.msgid.link/b15929a41621d215c6b2b57393368086589569ec.1728565530.git.daniel@makrotopia.org Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-17net: phy: realtek: read duplex and gbit master from PHYSR registerDaniel Golle
The PHYSR MMD register is present and defined equally for all RTL82xx Ethernet PHYs. Read duplex and Gbit master bits from rtlgen_decode_speed() and rename it to rtlgen_decode_physr(). Signed-off-by: Daniel Golle <daniel@makrotopia.org> Link: https://patch.msgid.link/b9a76341da851a18c985bc4774fa295babec79bb.1728565530.git.daniel@makrotopia.org Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-15net: phy: aquantia: fix return value check in aqr107_config_mdi()Daniel Golle
of_property_read_u32() returns -EINVAL in case the property cannot be found rather than -ENOENT. Fix the check to not abort probing in case of the property being missing, and also in case CONFIG_OF is not set which will result in -ENOSYS. Fixes: a2e1ba275eae ("net: phy: aquantia: allow forcing order of MDI pairs") Reported-by: Jon Hunter <jonathanh@nvidia.com> Closes: https://lore.kernel.org/all/114b4c03-5d16-42ed-945d-cf78eabea12b@nvidia.com/ Suggested-by: Hans-Frieder Vogt <hfdevel@gmx.net> Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Link: https://patch.msgid.link/f8282e2fc6a5ac91fe91491edc7f1ca8f4a65a0d.1728825323.git.daniel@makrotopia.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-15net: phy: intel-xway: add support for PHY LEDsDaniel Golle
The intel-xway PHY driver predates the PHY LED framework and currently initializes all LED pins to equal default values. Add PHY LED functions to the drivers and don't set default values if LEDs are defined in device tree. According the datasheets 3 LEDs are supported on all Intel XWAY PHYs. Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/81f4717ab9acf38f3239727a4540ae96fd01109b.1728558223.git.daniel@makrotopia.org Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-15net: phy: mxl-gpy: correctly describe LED polarityDaniel Golle
According the datasheet covering the LED (0x1b) register: 0B Active High LEDx pin driven high when activated 1B Active Low LEDx pin driven low when activated Make use of the now available 'active-high' property and correctly reflect the polarity setting which was previously inverted. Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/180ccafa837f09908b852a8a874a3808c5ecd2d0.1728558223.git.daniel@makrotopia.org Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-15net: phy: aquantia: correctly describe LED polarity overrideDaniel Golle
Use newly defined 'active-high' property to set the VEND1_GLOBAL_LED_DRIVE_VDD bit and let 'active-low' clear that bit. This reflects the technical reality which was inverted in the previous description in which the 'active-low' property was used to actually set the VEND1_GLOBAL_LED_DRIVE_VDD bit, which means that VDD (ie. supply voltage) of the LED is driven rather than GND. Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/86a413b4387c42dcb54f587cc2433a06f16aae83.1728558223.git.daniel@makrotopia.org Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-15net: phy: support 'active-high' property for PHY LEDsDaniel Golle
In addition to 'active-low' and 'inactive-high-impedance' also support 'active-high' property for PHY LED pin configuration. As only either 'active-high' or 'active-low' can be set at the same time, WARN and return an error in case both are set. Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/91598487773d768f254d5faf06cf65b13e972f0e.1728558223.git.daniel@makrotopia.org Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-15net: phy: c45-tja11xx: add support for outputting RMII reference clockWei Fang
For TJA11xx PHYs, they have the capability to output 50MHz reference clock on REF_CLK pin in RMII mode, which is called "revRMII" mode in the PHY data sheet. Signed-off-by: Wei Fang <wei.fang@nxp.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-14net: phylink: allow half-duplex modes with RATE_MATCH_PAUSEDaniel Golle
PHYs performing rate-matching using MAC-side flow-control always perform duplex-matching as well in case they are supporting half-duplex modes at all. No longer remove half-duplex modes from their capabilities. Suggested-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Link: https://patch.msgid.link/b157c0c289cfba024039a96e635d037f9d946745.1728617993.git.daniel@makrotopia.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-11net: phy: microchip_t1s: configure collision detection based on PLCA modeParthiban Veerasooran
As per LAN8650/1 Rev.B0/B1 AN1760 (Revision F (DS60001760G - June 2024)) and LAN8670/1/2 Rev.C1/C2 AN1699 (Revision E (DS60001699F - June 2024)), under normal operation, the device should be operated in PLCA mode. Disabling collision detection is recommended to allow the device to operate in noisy environments or when reflections and other inherent transmission line distortion cause poor signal quality. Collision detection must be re-enabled if the device is configured to operate in CSMA/CD mode. Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com> Link: https://patch.msgid.link/20241010082205.221493-8-parthiban.veerasooran@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-11net: phy: microchip_t1s: add support for Microchip's LAN867X Rev.C2Parthiban Veerasooran
Add support for LAN8670/1/2 Rev.C2 as per the latest configuration note AN1699 released (Revision E (DS60001699F - June 2024)) for Rev.C1 is also applicable for Rev.C2. Refer hardware revisions list in the latest AN1699 Revision E (DS60001699F - June 2024). https://www.microchip.com/en-us/application-notes/an1699 Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com> Link: https://patch.msgid.link/20241010082205.221493-7-parthiban.veerasooran@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-11net: phy: microchip_t1s: add support for Microchip's LAN867X Rev.C1Parthiban Veerasooran
Add support for LAN8670/1/2 Rev.C1 as per the latest configuration note AN1699 released (Revision E (DS60001699F - June 2024)). https://www.microchip.com/en-us/application-notes/an1699 Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com> Link: https://patch.msgid.link/20241010082205.221493-6-parthiban.veerasooran@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-11net: phy: microchip_t1s: move LAN867X reset handling to a new functionParthiban Veerasooran
Move LAN867X reset handling code to a new function called lan867x_check_reset_complete() which will be useful for the next patch which also uses the same code to handle the reset functionality. Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com> Link: https://patch.msgid.link/20241010082205.221493-5-parthiban.veerasooran@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-11net: phy: microchip_t1s: add support for Microchip's LAN865X Rev.B1Parthiban Veerasooran
Add support for LAN8650/1 Rev.B1. As per the latest configuration note AN1760 released (Revision F (DS60001760G - June 2024)) for Rev.B0 is also applicable for Rev.B1. Refer hardware revisions list in the latest AN1760 Revision F (DS60001760G - June 2024). https://www.microchip.com/en-us/application-notes/an1760 Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com> Link: https://patch.msgid.link/20241010082205.221493-4-parthiban.veerasooran@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-11net: phy: microchip_t1s: update new initial settings for LAN865X Rev.B0Parthiban Veerasooran
Update the new/improved initial settings from the latest configuration application note AN1760 released for LAN8650/1 Rev.B0 Revision F (DS60001760G - June 2024). https://www.microchip.com/en-us/application-notes/an1760 Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com> Link: https://patch.msgid.link/20241010082205.221493-3-parthiban.veerasooran@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-11net: phy: microchip_t1s: restructure cfg read/write functions argumentsParthiban Veerasooran
Restructure lan865x_write_cfg_params() and lan865x_read_cfg_params() functions arguments to more generic which will be useful for the next patch which updates the improved initial configuration for LAN8650/1 Rev.B0 published in the Configuration Note. Signed-off-by: Parthiban Veerasooran <parthiban.veerasooran@microchip.com> Link: https://patch.msgid.link/20241010082205.221493-2-parthiban.veerasooran@microchip.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-11net: phy: aquantia: poll status registerAryan Srivastava
The system interface connection status register is not immediately correct upon line side link up. This results in the status being read as OFF and then transitioning to the correct host side link mode with a short delay. This causes the phylink framework passing the OFF status down to all MAC config drivers, resulting in the host side link being misconfigured, which in turn can lead to link flapping or complete packet loss in some cases. Mitigate this by periodically polling the register until it not showing the OFF state. This will be done every 1ms for 10ms, using the same poll/timeout as the processor intensive operation reads. If the phy is still expressing the OFF state after the timeout, then set the link to false and pass the NA interface mode onto the phylink framework. Signed-off-by: Aryan Srivastava <aryan.srivastava@alliedtelesis.co.nz> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20241010004935.1774601-1-aryan.srivastava@alliedtelesis.co.nz Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-10Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski
Cross-merge networking fixes after downstream PR (net-6.12-rc3). No conflicts and no adjacent changes. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-10-10net: phy: Validate PHY LED OPs presence before registeringChristian Marangi
Validate PHY LED OPs presence before registering and parsing them. Defining LED nodes for a PHY driver that actually doesn't supports them is redundant and useless. It's also the case with Generic PHY driver used and a DT having LEDs node for the specific PHY. Skip it and report the error with debug print enabled. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://patch.msgid.link/20241008194718.9682-1-ansuelsmth@gmail.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-09net: phy: realtek: Fix MMD access on RTL8126A-integrated PHYHeiner Kallweit
All MMD reads return 0 for the RTL8126A-integrated PHY. Therefore phylib assumes it doesn't support EEE, what results in higher power consumption, and a significantly higher chip temperature in my case. To fix this split out the PHY driver for the RTL8126A-integrated PHY and set the read_mmd/write_mmd callbacks to read from vendor-specific registers. Fixes: 5befa3728b85 ("net: phy: realtek: add support for RTL8126A-integrated 5Gbps PHY") Cc: stable@vger.kernel.org Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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