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path: root/drivers/pinctrl
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2019-11-01pinctrl: sh-pfc: Rename PINCTRL_PFC_R8A7796 to PINCTRL_PFC_R8A77960Geert Uytterhoeven
Rename CONFIG_PINCTRL_PFC_R8A7796 for R-Car M3-W (R8A77960) to CONFIG_PINCTRL_PFC_R8A77960, to avoid confusion with R-Car M3-W+ (R8A77961), which will use CONFIG_PINCTRL_PFC_R8A77961. Extend the dependency of CONFIG_PINCTRL_PFC_R8A77960 from CONFIG_ARCH_R8A7796 to CONFIG_ARCH_R8A77960, to relax dependencies for a future rename of the SoC configuration symbol. Rename r8a7796_pinmux_info to r8a77960_pinmux_info, as it contains an r8a77960-based name. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191023122955.12420-3-geert+renesas@glider.be
2019-11-01pinctrl: sh-pfc: Do not use platform_get_irq() to count interruptsGeert Uytterhoeven
As platform_get_irq() now prints an error when the interrupt does not exist, counting interrupts by looping until failure causes the printing of scary messages like: sh-pfc e6060000.pin-controller: IRQ index 0 not found Fix this by using the platform_irq_count() helper instead. Fixes: 7723f4c5ecdb8d83 ("driver core: platform: Add an error message to platform_get_irq*()") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20191016142601.28255-1-geert+renesas@glider.be
2019-10-30pinctrl: intel: Add Intel Tiger Lake pin controller supportAndy Shevchenko
This driver adds pinctrl/GPIO support for Intel Tiger Lake SoC. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-10-30pinctrl: intel: Use helper to restore register values on ->resume()Andy Shevchenko
We can restore only values that had been changed and do not spam kernel log with unnecessary messages. Convert intel_gpio_update_pad_mode() to a helper function that will be used across few callers. Suggested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30pinctrl: intel: Drop level from warning to debug in intel_restore_hostown()Andy Shevchenko
Since we didn't get any new reports from users about wrong settings of pad ownership, there is no point to spam kernel log with it. Thus, drop level from warning to debug. Also, modify format to be in align with the rest restore helpers. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30pinctrl: intel: Introduce intel_restore_intmask() helperAndy Shevchenko
Refactor restoring GPI_IE registers by using an introduced helper. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30pinctrl: intel: Introduce intel_restore_hostown() helperAndy Shevchenko
Refactor restoring HOSTSW_OWN registers by using an introduced helper. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30pinctrl: intel: Introduce intel_restore_padcfg() helperAndy Shevchenko
Deduplicate restoring PADCFGx registers by using a common helper. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30pinctrl: cherryview: Allocate IRQ chip dynamicAndy Shevchenko
Keeping the IRQ chip definition static shares it with multiple instances of the GPIO chip in the system. This is bad and now we get this warning from GPIO library: "detected irqchip that is shared with multiple gpiochips: please fix the driver." Hence, move the IRQ chip definition from being driver static into the struct intel_pinctrl. So a unique IRQ chip is used for each GPIO chip instance. This patch is heavily based on the attachment to the bug by Christoph Marz. BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=202543 Fixes: 6e08d6bbebeb ("pinctrl: Add Intel Cherryview/Braswell pin controller support") Depends-on: 83b9dc11312f ("pinctrl: cherryview: Associate IRQ descriptors to irqdomain") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30pinctrl: cherryview: Fix spelling mistake in the commentAndy Shevchenko
One spelling mistake is being fixed: benerate -> generate. It is a complimentary fix to the commit 505485a83c55 ("pinctrl: cherryview fixed typo in comment"). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30pinctrl: cherryview: Fix irq_valid_mask calculationHans de Goede
Commit 03c4749dd6c7 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation") has made the cherryview gpio numbers sparse, to get a 1:1 mapping between ACPI pin numbers and gpio numbers in Linux. This has greatly simplified things, but the code setting the irq_valid_mask was not updated for this, so the valid mask is still in the old "compressed" numbering with the gaps in the pin numbers skipped, which is wrong as irq_valid_mask needs to be expressed in gpio numbers. This results in the following error on devices using pin 24 (0x0018) on the north GPIO controller as an ACPI event source: [ 0.422452] cherryview-pinctrl INT33FF:01: Failed to translate GPIO to IRQ This has been reported (by email) to be happening on a Caterpillar CAT T20 tablet and I've reproduced this myself on a Medion Akoya e2215t 2-in-1. This commit uses the pin number instead of the compressed index into community->pins to clear the correct bits in irq_valid_mask for GPIOs using GPEs for interrupts, fixing these errors and in case of the Medion Akoya e2215t also fixing the LID switch not working. Cc: stable@vger.kernel.org Fixes: 03c4749dd6c7 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation") Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2019-10-30pinctrl: intel: Avoid potential glitches if pin is in GPIO modeAndy Shevchenko
When consumer requests a pin, in order to be on the safest side, we switch it first to GPIO mode followed by immediate transition to the input state. Due to posted writes it's luckily to be a single I/O transaction. However, if firmware or boot loader already configures the pin to the GPIO mode, user expects no glitches for the requested pin. We may check if the pin is pre-configured and leave it as is till the actual consumer toggles its state to avoid glitches. Fixes: 7981c0015af2 ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support") Depends-on: f5a26acf0162 ("pinctrl: intel: Initialize GPIO properly when used through irqchip") Cc: stable@vger.kernel.org Cc: fei.yang@intel.com Reported-by: Oliver Barta <oliver.barta@aptiv.com> Reported-by: Malin Jonsson <malin.jonsson@ericsson.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-30Merge tag 'intel-pinctrl-fixes-v5.4-2' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into fixes intel-pinctrl fixes for v5.4 part 2 A couple more fixes for Intel pinctrl drivers: - Try to avoid glitches when pin is in GPIO mode - Fix cherryview irq_valid_mask calculation - Allocate cherryview IRQ chip dynamically to avoid triggering warning from GPIO core
2019-10-25pinctrl: cherryview: Allocate IRQ chip dynamicAndy Shevchenko
Keeping the IRQ chip definition static shares it with multiple instances of the GPIO chip in the system. This is bad and now we get this warning from GPIO library: "detected irqchip that is shared with multiple gpiochips: please fix the driver." Hence, move the IRQ chip definition from being driver static into the struct intel_pinctrl. So a unique IRQ chip is used for each GPIO chip instance. This patch is heavily based on the attachment to the bug by Christoph Marz. BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=202543 Fixes: 6e08d6bbebeb ("pinctrl: Add Intel Cherryview/Braswell pin controller support") Depends-on: 83b9dc11312f ("pinctrl: cherryview: Associate IRQ descriptors to irqdomain") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-25Merge tag 'sh-pfc-for-v5.5-tag1' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v5.5 - Add support for the new RZ/G2N (r8a774b1) SoC, - Small fixes and cleanups.
2019-10-24pinctrl: mvebu: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20191016141217.21520-1-yuehaibing@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-24pinctrl: mediatek: use devm_platform_ioremap_resource() to simplify codeYueHaibing
Use devm_platform_ioremap_resource() to simplify the code a bit. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lore.kernel.org/r/20191016141053.23740-1-yuehaibing@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-21pinctrl: cherryview: Fix irq_valid_mask calculationHans de Goede
Commit 03c4749dd6c7 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation") has made the cherryview gpio numbers sparse, to get a 1:1 mapping between ACPI pin numbers and gpio numbers in Linux. This has greatly simplified things, but the code setting the irq_valid_mask was not updated for this, so the valid mask is still in the old "compressed" numbering with the gaps in the pin numbers skipped, which is wrong as irq_valid_mask needs to be expressed in gpio numbers. This results in the following error on devices using pin 24 (0x0018) on the north GPIO controller as an ACPI event source: [ 0.422452] cherryview-pinctrl INT33FF:01: Failed to translate GPIO to IRQ This has been reported (by email) to be happening on a Caterpillar CAT T20 tablet and I've reproduced this myself on a Medion Akoya e2215t 2-in-1. This commit uses the pin number instead of the compressed index into community->pins to clear the correct bits in irq_valid_mask for GPIOs using GPEs for interrupts, fixing these errors and in case of the Medion Akoya e2215t also fixing the LID switch not working. Cc: stable@vger.kernel.org Fixes: 03c4749dd6c7 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation") Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-21pinctrl: intel: Avoid potential glitches if pin is in GPIO modeAndy Shevchenko
When consumer requests a pin, in order to be on the safest side, we switch it first to GPIO mode followed by immediate transition to the input state. Due to posted writes it's luckily to be a single I/O transaction. However, if firmware or boot loader already configures the pin to the GPIO mode, user expects no glitches for the requested pin. We may check if the pin is pre-configured and leave it as is till the actual consumer toggles its state to avoid glitches. Fixes: 7981c0015af2 ("pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support") Depends-on: f5a26acf0162 ("pinctrl: intel: Initialize GPIO properly when used through irqchip") Cc: stable@vger.kernel.org Cc: fei.yang@intel.com Reported-by: Oliver Barta <oliver.barta@aptiv.com> Reported-by: Malin Jonsson <malin.jonsson@ericsson.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2019-10-16pinctrl: sprd: Add CM4 sleep mode supportBruce Chen
For the new Spreadtrum pin controller, it expands 6bits to describe the pin sleep mode with adding one CM4_SLEEP mode, which means the pin sleep related configuration will be loaded automatically by hardware when the CM4 system goes into deep sleep mode. Signed-off-by: Bruce Chen <bruce.chen@unisoc.com> Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Link: https://lore.kernel.org/r/8ae52263b0625c416461821c457e6789b67170b6.1571228451.git.baolin.wang@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16pinctrl: aspeed-g6: Rename SD3 to EMMC and rework pin groupsJohnny Huang
AST2600 EMMC support 3 types DAT bus sizes (1, 4 and 8-bit), corresponding to 3 groups: EMMCG1, EMMCG4 and EMMCG8 Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191008044153.12734-8-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16pinctrl: aspeed-g6: Fix UART13 group pinmuxJohnny Huang
When UART13G1 is set the pinmux configuration in SCU4B8 for UART13G0 should be cleared. Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> [AJ: Tweak commit message] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191008044153.12734-7-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16pinctrl: aspeed-g6: Make SIG_DESC_CLEAR() behave intuitivelyAndrew Jeffery
Signal descriptors can represent multi-bit bitfields and so have explicit "enable" and "disable" states. However many descriptor instances only describe a single bit, and so the SIG_DESC_SET() macro is provides an abstraction for the single-bit cases: Its expansion configures the "enable" state to set the bit and "disable" to clear. SIG_DESC_CLEAR() was introduced to provide a similar single-bit abstraction for for descriptors to clear the bit of interest. However its behaviour was defined as the literal inverse of SIG_DESC_SET() - the impact is the bit of interest is set in the disable path. This behaviour isn't intuitive and doesn't align with how we want to use the macro in practice, so make it clear the bit for both the enable and disable paths. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191008044153.12734-6-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16pinctrl: aspeed-g6: Fix I3C3/I3C4 pinmux configurationJohnny Huang
The documentation to configure I3C3/FSI1 and I3C4/FSI2 was initially unclear. Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Johnny Huang <johnny_huang@aspeedtech.com> [AJ: Tweak commit message, resolve rebase conflicts] Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191008044153.12734-5-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16pinctrl: aspeed-g6: Fix I2C14 SDA descriptionAndrew Jeffery
The I2C function the pin participated in was incorrectly named SDA14 which lead to a failure to mux: [ 6.884344] No function I2C14 found on pin 7 (7). Found signal(s) MACLINK4, SDA14, GPIOA7 for function(s) MACLINK4, SDA14, GPIOA7 Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191008044153.12734-4-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16pinctrl: aspeed-g6: Sort pins for sanityAndrew Jeffery
Some pins crept in that weren't ordered in the list. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20191008044153.12734-3-andrew@aj.id.au Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16pinctrl: nomadik: Simplify interrupt handlerLinus Walleij
The inner interrupt handler was for the latent IRQ handling, and that will never be used, inline the unnecessary function. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191014111154.9731-3-linus.walleij@linaro.org
2019-10-16pinctrl: nomadik: Pass irqchip when adding gpiochipLinus Walleij
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191014111154.9731-2-linus.walleij@linaro.org
2019-10-16pinctrl: nomadik: Drop support for latent IRQLinus Walleij
The latent IRQs are IRQs that have occurred when the system was down in deep sleep and the GPIO block was powered off. The PRCMU (power reset and control unit) knows which GPIO line offset fired an IRQ to wake the system up (if so desired) and this second IRQ was used to replay the action when the system came back online after suspend(). This is now known to be the wrong approach to solve this problem: in a patch series Lina Iyer has suggested to instead make it possible to model the IRQs as hierarchical with double parents. Also the current device trees do not contain the right information to make this code work, the latent IRQ is not specified nowadays giving noise like this in the console: [ 0.612168] gpio 8012e000.gpio: IRQ index 1 not found [ 0.622523] gpio 8012e080.gpio: IRQ index 1 not found Let's delete the latent IRQ code and reimplement it properly when we need it. Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191014111154.9731-1-linus.walleij@linaro.org
2019-10-16pinctrl: rockchip: add rk3308 SoC supportJianqun Xu
This patch do support pinctrl for RK3308 SoCs. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Link: https://lore.kernel.org/r/20191015091708.7934-3-jay.xu@rock-chips.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16pinctrl: sprd: Add PIN_CONFIG_BIAS_DISABLE configuration supportBaolin Wang
Add PIN_CONFIG_BIAS_DISABLE configuration support for Spreadtrum pin controller. Signed-off-by: Baolin Wang <baolin.wang@linaro.org> Link: https://lore.kernel.org/r/66d373ddee61e8be2fcef49aac5e80bd58f14915.1570596606.git.baolin.wang@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16pinctrl: stmfx: add irq_request/release_resources callbacksAmelie Delaunay
When an STMFX IO is used as interrupt through the interrupt-controller binding, the STMFX driver should configure this IO as input. Default value of STMFX IO direction is input, but if the IO is used as output before the interrupt use, it will not work without these callbacks. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Link: https://lore.kernel.org/r/20191009091606.17283-1-amelie.delaunay@st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16pinctrl: qcom: Add a pinctrl driver for MSM8976 and 8956AngeloGioacchino Del Regno
Add the pinctrl driver to support pin configuration with the pinctrl framework on MSM8976, MSM8956, APQ8056, APQ8076. Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com> Link: https://lore.kernel.org/r/20191005105936.31216-2-kholk11@gmail.com Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16pinctrl: ingenic: Pass irqchip when adding gpiochipLinus Walleij
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Thierry Reding <thierry.reding@gmail.com> Acked-by: Zhou Yanjie <zhouyanjie@zoho.com> Acked-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191001133209.17164-1-linus.walleij@linaro.org
2019-10-16dt-bindings: pinctrl: qcom-pmic-gpio: Add support for pm6150/pm6150lKiran Gunda
Add support for the PM6150 and PM6150L GPIO support to the Qualcomm PMIC GPIO binding. Signed-off-by: Kiran Gunda <kgunda@codeaurora.org> Link: https://lore.kernel.org/r/1570188039-22122-1-git-send-email-kgunda@codeaurora.org Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16pinctrl: pistachio: Pass irqchip when adding gpiochipLinus Walleij
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Andrew Bresticker <abrestic@chromium.org> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: James Hartley <james.hartley@sondrel.com> Link: https://lore.kernel.org/r/20191001214536.18477-1-linus.walleij@linaro.org
2019-10-16pinctrl: armada-37xx: Pass irqchip when adding gpiochipLinus Walleij
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Gregory CLEMENT <gregory.clement@bootlin.com> Cc: Marek Behún <marek.behun@nic.cz> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191002121550.16104-1-linus.walleij@linaro.org
2019-10-16pinctrl: ocelot: Pass irqchip when adding gpiochipLinus Walleij
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/20191002114454.9684-1-linus.walleij@linaro.org
2019-10-16pinctrl: berlin: as370: fix a typo s/spififib/spdifibJisheng Zhang
The function should be spdifib, fix this typo. Fixes: 423ddc580b13 ("pinctrl: berlin: add the as370 SoC pinctrl driver") Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Link: https://lore.kernel.org/r/20191011154321.44f08f9a@xhacker.debian Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-10-16pinctrl: oxnas: Pass irqchip when adding gpiochipLinus Walleij
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion. Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191002113819.4927-1-linus.walleij@linaro.org
2019-10-16pinctrl: st: Pass irqchip when adding gpiochipLinus Walleij
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion: the ST pin controller errors out of adding a irqchip if the interrupt is invalid or missing or if the irqmux is not present: the irqchip should not be added if either of these errors happen, so rewrite the code to deal with that. Keep the exit path where the gpio_chip is added no matter what the status of the irq is. Cc: Benjamin Gaignard <benjamin.gaignard@st.com> Cc: Amelie Delaunay <amelie.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20191001135147.29416-1-linus.walleij@linaro.org
2019-10-16pinctrl: at91: Pass irqchip when adding gpiochipLinus Walleij
We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For more info see drivers/gpio/TODO. For chained irqchips this is a pretty straight-forward conversion: at91 is a little bit special since it registers up to 3 gpio_chips with the same parent handler, but just passing girq->parent_handler and the parent on the first of them should cut it. Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Alexandre Belloni <alexandre.belloni@bootlin.com> Cc: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com> Link: https://lore.kernel.org/r/20191001130645.8350-1-linus.walleij@linaro.org
2019-10-14pinctrl: sh-pfc: pfc-r8a77965: Fix typo in pinmux macro for SCL3Keiya Nobuta
SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro. Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com> Link: https://lore.kernel.org/r/20191008060619.30237-4-nobuta.keiya@fujitsu.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-14pinctrl: sh-pfc: pfc-r8a7796: Fix typo in pinmux macro for SCL3Keiya Nobuta
SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro. Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com> Link: https://lore.kernel.org/r/20191008060619.30237-3-nobuta.keiya@fujitsu.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-14pinctrl: sh-pfc: pfc-r8a7795-es1: Fix typo in pinmux macro for SCL3Keiya Nobuta
SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro. Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com> Link: https://lore.kernel.org/r/20191008060619.30237-2-nobuta.keiya@fujitsu.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-14pinctrl: sh-pfc: pfc-r8a7795: Fix typo in pinmux macro for SCL3Keiya Nobuta
SCL3 is assigned to GPSR2 bit7 referred by IP1_23_20 macro. Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com> Link: https://lore.kernel.org/r/20191008060619.30237-1-nobuta.keiya@fujitsu.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-14pinctrl: sh-pfc: Fix PINMUX_IPSR_PHYS() to set GPSRKeiya Nobuta
This patch allows PINMUX_IPSR_PHYS() to set bits in GPSR. When assigning function to pin, GPSR should be set to peripheral function. For example when using SCL3, GPSR2 bit7 (PWM1_A pin) should be set to peripheral function. Signed-off-by: Keiya Nobuta <nobuta.keiya@fujitsu.com> Link: https://lore.kernel.org/r/20191008060112.29819-1-nobuta.keiya@fujitsu.com Fixes: 50d1ba1764b3e00a ("pinctrl: sh-pfc: Add physical pin multiplexing helper macros") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-14pinctrl: rzn1: Make array reg_drive static, makes object smallerColin Ian King
Don't populate the array reg_drive on the stack but instead make it static. Makes the object code smaller by 32 bytes. Before: text data bss dec hex filename 31991 15696 0 47687 ba47 drivers/pinctrl/pinctrl-rzn1.o After: text data bss dec hex filename 31863 15792 0 47655 ba27 drivers/pinctrl/pinctrl-rzn1.o (gcc version 9.2.1, amd64) Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20191007140559.11840-1-colin.king@canonical.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-11Merge tag 'intel-pinctrl-fixes-v5.4' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into fixes intel-pinctrl fixes for v5.4 This includes two fixes for Intel pinctrl drivers: - Fix warning about shared irqchip - Restore Strago DMI workaround for all versions
2019-10-09pinctrl: armada-37xx: swap polarity on LED groupPatrick Williams
The configuration registers for the LED group have inverted polarity, which puts the GPIO into open-drain state when used in GPIO mode. Switch to '0' for GPIO and '1' for LED modes. Fixes: 87466ccd9401 ("pinctrl: armada-37xx: Add pin controller support for Armada 37xx") Signed-off-by: Patrick Williams <alpawi@amazon.com> Cc: <stable@vger.kernel.org> Link: https://lore.kernel.org/r/20191001155154.99710-1-alpawi@amazon.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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