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path: root/drivers/pinctrl
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2025-03-18pinctrl: PINCTRL_AMDISP should depend on DRM_AMD_ISPGeert Uytterhoeven
The AMD Image Signal Processor GPIO pin control functionality is only present on AMD platforms with ISP support, and its platform device is instantiated by the AMD ISP driver. Hence add a dependency on DRM_AMD_ISP, to prevent asking the user about this driver when configuring a kernel that does not support the AMD ISP. Fixes: e97435ab09f3ad7b ("pinctrl: amd: isp411: Add amdisp GPIO pinctrl") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/3685561e8e3cd1d94bce220eeb6001d659da615c.1742306024.git.geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-18pinctrl: spacemit: PINCTRL_SPACEMIT_K1 should not default to y unconditionallyGeert Uytterhoeven
Merely enabling compile-testing should not enable additional functionality. Fixes: 7ff4faba63571c51 ("pinctrl: spacemit: enable config option") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yixun Lan <dlan@gentoo.org> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Tested-by: Alex Elder <elder@riscstar.com> Reviewed-by: Alex Elder <elder@riscstar.com> Link: https://lore.kernel.org/6881b8d1ad74ac780af8a974e604b5ef3f5d4aad.1742198691.git.geert+renesas@glider.be Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-18Merge tag 'samsung-pinctrl-6.15' of ↵Linus Walleij
https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v6.15 1. Add pin controller drivers for newly usptreamed Samsung Exynos2200 and Exynos7870. 2. Correct filter configuration offset of some of Google GS101 SoC pin banks, which later is supposed to be used during system suspend/resume. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-17pinctrl: qcom: sa8775p: Enable egpio functionWasim Nazir
Egpio feature allows IsLand Domain IOs to be reused as TLMM GPIOs. sa8775p supports egpio feature for GPIOs ranging from 126 to 148. Signed-off-by: Wasim Nazir <quic_wasimn@quicinc.com> Reviewed-by: Dmitry Baryshkov <lumag@kernel.org> Link: https://lore.kernel.org/20250312072509.3247885-3-quic_wasimn@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-17pinctrl: qcom: tlmm-test: Validate irq_enable delivers edge irqsBjorn Andersson
In commit 'cf9d052aa600 ("pinctrl: qcom: Don't clear pending interrupts when enabling")' Doug establishes an expectation that edge interrupts occurring while an interrupt is disabled should be delivered once the interrupt is enabled again. Implement a test to validate that this is the case. Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Link: https://lore.kernel.org/20250313-tlmm-test-disabled-irq-delivered-v1-1-f0be903732ac@oss.qualcomm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-17pinctrl: qcom: Clear latched interrupt status when changing IRQ typeStephan Gerhold
When submitting the TLMM test driver, Bjorn reported that some of the test cases are failing for GPIOs that not are backed by PDC (i.e. "non-wakeup" GPIOs that are handled directly in pinctrl-msm). Basically, lingering latched interrupt state is still being delivered at IRQ request time, e.g.: ok 1 tlmm_test_silent_rising tlmm_test_silent_falling: ASSERTION FAILED at drivers/pinctrl/qcom/tlmm-test.c:178 Expected atomic_read(&priv->intr_count) == 0, but atomic_read(&priv->intr_count) == 1 (0x1) not ok 2 tlmm_test_silent_falling tlmm_test_silent_low: ASSERTION FAILED at drivers/pinctrl/qcom/tlmm-test.c:178 Expected atomic_read(&priv->intr_count) == 0, but atomic_read(&priv->intr_count) == 1 (0x1) not ok 3 tlmm_test_silent_low ok 4 tlmm_test_silent_high Whether to report interrupts that came in while the IRQ was unclaimed doesn't seem to be well-defined in the Linux IRQ API. However, looking closer at these specific cases, we're actually reporting events that do not match the interrupt type requested by the driver: 1. After "ok 1 tlmm_test_silent_rising", the GPIO is in low state and configured for IRQF_TRIGGER_RISING. 2. (a) In preparation for "tlmm_test_silent_falling", the GPIO is switched to high state. The rising interrupt gets latched. (b) The GPIO is re-configured for IRQF_TRIGGER_FALLING, but the latched interrupt isn't cleared. (c) The IRQ handler is called for the latched interrupt, but there wasn't any falling edge. 3. (a) For "tlmm_test_silent_low", the GPIO remains in high state. (b) The GPIO is re-configured for IRQF_TRIGGER_LOW. This seems to result in a phantom interrupt that gets latched. (c) The IRQ handler is called for the latched interrupt, but the GPIO isn't in low state. 4. (a) For "tlmm_test_silent_high", the GPIO is switched to low state. (b) This doesn't result in a latched interrupt, because RAW_STATUS_EN was cleared when masking the level-triggered interrupt. Fix this by clearing the interrupt state whenever making any changes to the interrupt configuration. This includes previously disabled interrupts, but also any changes to interrupt polarity or detection type. With this change, all 16 test cases are now passing for the non-wakeup GPIOs in the TLMM. Cc: stable@vger.kernel.org Fixes: cf9d052aa600 ("pinctrl: qcom: Don't clear pending interrupts when enabling") Reported-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Closes: https://lore.kernel.org/r/20250227-tlmm-test-v1-1-d18877b4a5db@oss.qualcomm.com/ Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Tested-by: Bjorn Andersson <andersson@kernel.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/20250312-pinctrl-msm-type-latch-v1-1-ce87c561d3d7@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-17pinctrl: bcm281xx: Add missing assignment in bcm21664_pinctrl_lock_all()Dan Carpenter
The next line checks if this regmap_write() failed, but it doesn't work because the assignment was accidentally left out. Add the assignment. Fixes: 60d69769c851 ("pinctrl: bcm281xx: Add support for BCM21664 pinmux") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Acked-by: Artur Weber <aweber.kernel@gmail.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/dfc15d59-7fa9-4f96-aacb-37c3df6d420d@stanley.mountain Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-17pinctrl: amd: isp411: Fix IS_ERR() vs NULL check in probe()Dan Carpenter
The platform_get_resource() returns NULL on error. It doesn't return error pointers. Fix the error checking to match. Fixes: e97435ab09f3 ("pinctrl: amd: isp411: Add amdisp GPIO pinctrl") Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org> Reviewed-by: Pratap Nirujogi <pratap.nirujogi@amd.com> Link: https://lore.kernel.org/617f4c77-7837-4e24-9f4d-620ecfedf924@stanley.mountain Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-17pinctrl: tegra: Set SFIO mode to Mux RegisterPrathamesh Shete
Tegra devices have an 'sfsel' bit field that determines whether a pin operates in SFIO (Special Function I/O) or GPIO mode. Currently, tegra_pinctrl_gpio_disable_free() sets this bit when releasing a GPIO. However, tegra_pinctrl_set_mux() can be called independently in certain code paths where gpio_disable_free() is not invoked. In such cases, failing to set the SFIO mode could lead to incorrect pin configurations, resulting in functional issues for peripherals relying on SFIO. This patch ensures that whenever set_mux() is called, the SFIO mode is correctly set in the Mux Register if the 'sfsel' bit is present. This prevents situations where the pin remains in GPIO mode despite being configured for SFIO use. Fixes: 971dac7123c7 ("pinctrl: add a driver for NVIDIA Tegra") Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Link: https://lore.kernel.org/20250306050542.16335-1-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-14pinctrl-tegra: Restore SFSEL bit when freeing pinsPrathamesh Shete
Each pin can be configured as a Special Function IO (SFIO) or GPIO, where the SFIO enables the pin to operate in alternative modes such as I2C, SPI, etc. The current implementation sets all the pins back to SFIO mode even if they were initially in GPIO mode. This can cause glitches on the pins when pinctrl_gpio_free() is called. Avoid these undesired glitches by storing the pin's SFIO/GPIO state on GPIO request and restoring it on GPIO free. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Link: https://lore.kernel.org/20250305104939.15168-2-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-14pinctrl: tegra: Add descriptions for SoC data fieldsPrathamesh Shete
Add detailed descriptions for the remaining fields in the tegra_pinctrl_soc_data structure. This improves code documentation and clarifies the purpose of each field, particularly for the pin-specific configuration options. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Link: https://lore.kernel.org/20250305104939.15168-1-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-14pinctrl: spacemit: destroy mutex at driver detachBartosz Golaszewski
The mutex initialized in probe() is never cleaned up. Use devm_mutex_init() to destroy it automatically. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/20250305102710.52762-1-brgl@bgdev.pl Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-14pinctrl: ingenic: jz4730: add pinmux for I2S interfaceH. Nikolaus Schaller
I2S is used for the sound codec of the Alpha400. Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Link: https://lore.kernel.org/7e79b16be569fb0f501032b2b6ec726e4a09411f.1740823241.git.hns@goldelico.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-14pinctrl: ingenic: jz4730: add pinmux for MIIH. Nikolaus Schaller
The MII interface is used for the Ethernet connection of the Alpha400. Reviewed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Link: https://lore.kernel.org/972b31e1fce03808745e53df17315b29e2bcf696.1740823241.git.hns@goldelico.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-14pinctrl: ingenic: add x1600 supportPaul Boddie
Add support for the Lumissil/Ingenic X1600 SoC. It uses shadow registers to commit changes to multiple pinctrl registers in parallel. Define specific Chip ID, register offsets, pin tables etc. Handling the unique X1600_GPIO_PU only for the x1600 but not for x1830 and above must be carefully taken into account. Reviewed-by: Paul Cercueil <paul@crapouillou.net> Co-authored-by: Andreas Kemnade <andreas@kemnade.info> Co-authored-by: H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by: Paul Boddie <paul@boddie.org.uk> Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Link: https://lore.kernel.org/84477ec9cb9ed13bf4f6f87d5fb3b55542d31097.1740823241.git.hns@goldelico.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-13pinctrl: sunxi: Add support for the secondary A523 GPIO portsAndre Przywara
As most other Allwinner SoCs before, the A523 chip contains a second GPIO controller, managing banks PL and PM. Use the newly introduced DT based pinctrl driver to describe just the generic pinctrl properties, so advertise the number of pins per bank and the interrupt capabilities. The actual function/mux assignment is taken from the devicetree. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/20250306235827.4895-9-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-13pinctrl: sunxi: Add support for the Allwinner A523Andre Przywara
The Allwinner A523 contains pins in 10 out of the 11 possible pin banks; it just skips port A. Use the newly introduced DT based pinctrl driver to describe just the generic pinctrl properties, so advertise the number of pins per bank and the interrupt capabilities. The actual function/mux assignment is taken from the devicetree. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/20250306235827.4895-8-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-13pinctrl: sunxi: allow reading mux values from DTAndre Przywara
So far every Allwinner SoC needs a large table in the kernel code, to describe the mapping between the pinctrl function names ("uart") and the actual pincontroller mux value to be written into the registers. This adds a lot of data into a single image kernel, and also looks somewhat weird, as the DT can easily store the mux value. Add some code that allows to avoid that table: the struct that describes the existing pins will be build at *runtime*, based on very basic information provided by the respective SoC's pinctrl driver. This consists of the number of pins per bank, plus information which bank provides IRQ support, along with the mux value to use for that. The code will then iterate over all children of the pincontroller DT node (which describe each pin group), and populate that struct with the mapping between function names and mux values. The only thing that needs adding in the DT is a property with that value, per pin group. When this table is built, it will be handed over to the existing sunxi pinctrl driver, which cannot tell a difference between a hardcoded struct and this new one built at runtime. It will take care of registering the pinctrl device with the pinctrl subsystem. All a new SoC driver would need to do is to provide two arrays, and then call the sunxi_pinctrl_dt_table_init() function. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/20250306235827.4895-6-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-13pinctrl: sunxi: support moved power configuration registersAndre Przywara
The Allwinner pincontroller IP features some registers to control the withstand voltage of each pin group. So far those registers were always located at the same offset, but the A523 SoC has moved them (probably to accommodate all eleven pin banks). Add a flag to note this feature, and use that to program the registers either at offset 0x340 or 0x380. So far no pincontroller driver uses this flag, but we need it for the upcoming A523 support. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/20250306235827.4895-5-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-13pinctrl: sunxi: move bank K register offsetAndre Przywara
The Allwinner pincontroller register layout used to allow for at least 11 banks per controller, any more banks would reside at a second controller instance. When the per-bank register map size was increased with the D1, it turned out that the last bank (port K) of those maximum 11 banks actually would not fit anymore in the 512 bytes reserved for the pincontroller registers. On new SoCs Allwinner thus moved the last bank beyond the existing registers, at offset 0x500. So far SoCs never used more than 9 banks per controller, but the new Allwinner A523 actually uses all 11 banks. Since that SoC also uses the extended layout, its PortK needs to be programmed at offset 0x500. Factor out the bank offset calculation into a new function, and handle the case for the last bank separately. Since none of the older SoCs ever used PortK, we can ignore this case, and just always use offset 0x500 for the last bank. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/20250306235827.4895-4-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-13pinctrl: sunxi: increase number of GPIO bank regulatorsAndre Przywara
By design, the Allwinner pinctrl IP always supported up to 11 GPIO banks, though no SoC ever used more than 9 banks so far. The Allwinner A523 has pins in all 11 banks, which exceeds the number of per-bank regulators that we currently support, as this was set to 9. Increase the size of the array to hold up to 11 regulator structs, to support pins in bank J and K as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Link: https://lore.kernel.org/20250306235827.4895-3-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-13pinctrl: sunxi: refactor pinctrl variants into flagsAndre Przywara
For some Allwinner SoCs we have one pinctrl driver caring for multiple very similar chips, and are tagging certain pins with a variant bitmask. The Allwinner D1 introduced a slightly extended register layout, and we were abusing this variant mask to convey this bit of information into the common code part. Now there will be more pinctrl device properties to consider (has PortF voltage switch, for instance), so shoehorning this into the variant bitmask will not fly anymore. Refactor the "variant" field into a more generic "flags" field. It turns out that we don't need the variant bits to be unique across all SoCs, but only among those SoCs that share one driver (table), of which there are at most three variants at the moment. So the actual variant field can be limited to say 8 bits, and the other bits in the flag register can be re-purposed to hold other information, like this extended register layout. As a side effect we can move the variant definition into the per-SoC pinctrl driver file, which makes it more obvious that this is just a private definition, only relevant for this particular table. This also changes the artificial sun20i-d1 "variant" into the actual flag bit that we are after. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/20250306235827.4895-2-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-13Merge tag 'intel-pinctrl-v6.15-1' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v6.15-1 * Introduce devm_kmemdup_array() and convert Intel pin control drivers * Update PWM handling for the cases when it's provided by Intel pin control * Miscellaneous fixes, updates, and cleanups The following is an automated git shortlog grouped by driver: baytrail: - copy communities using devm_kmemdup_array() - Use dedicated helpers for chained IRQ handlers cherryview: - use devm_kmemdup_array() devres: - Introduce devm_kmemdup_array() driver core: - Split devres APIs to device/devres.h err.h: - move IOMEM_ERR_PTR() to err.h iio: - adc: xilinx-xadc-core: use devm_kmemdup_array() - imu: st_lsm9ds0: Replace device.h with what is needed input: - ipaq-micro-keys: use devm_kmemdup_array() - sparse-keymap: use devm_kmemdup_array() intel: - drop repeated config dependency - copy communities using devm_kmemdup_array() - Fix wrong bypass assignment in intel_pinctrl_probe_pwm() - Import PWM_LPSS namespace for devm_pwm_lpss_probe() lynxpoint: - Use dedicated helpers for chained IRQ handlers MAINTAINERS: - Add pin control and GPIO to the Intel MID record pwm: - lpss: Clarify the bypass member semantics in struct pwm_lpss_boardinfo - lpss: Actually use a module namespace by defining the namespace earlier pxa2xx: - use devm_kmemdup_array() tangier: - use devm_kmemdup_array() Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-13Merge tag 'renesas-pinctrl-for-v6.15-tag2' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.15 (take two) - Add missing of_node_put() calls. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-11pinctrl: samsung: add support for eint_fltcon_offsetPeter Griffin
On gs101 SoC the fltcon0 (filter configuration 0) offset isn't at a fixed offset like previous SoCs as the fltcon1 register only exists when there are more than 4 pins in the bank. Add a eint_fltcon_offset and new GS101_PIN_BANK_EINT* macros that take an additional fltcon_offs variable. This can then be used in suspend/resume callbacks to save and restore the fltcon0 and fltcon1 registers. Fixes: 4a8be01a1a7a ("pinctrl: samsung: Add gs101 SoC pinctrl configuration") Cc: stable@vger.kernel.org Reviewed-by: André Draszik <andre.draszik@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250307-pinctrl-fltcon-suspend-v4-1-2d775e486036@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-03-06pinctrl: renesas: rza2: Fix missing of_node_put() callFabrizio Castro
of_parse_phandle_with_fixed_args() requires its caller to call into of_node_put() on the node pointer from the output structure, but such a call is currently missing. Call into of_node_put() to rectify that. Fixes: b59d0e782706 ("pinctrl: Add RZ/A2 pin and gpio controller") Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250305163753.34913-5-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-03-06pinctrl: renesas: rzv2m: Fix missing of_node_put() callFabrizio Castro
of_parse_phandle_with_fixed_args() requires its caller to call into of_node_put() on the node pointer from the output structure, but such a call is currently missing. Call into of_node_put() to rectify that. Fixes: 92a9b8252576 ("pinctrl: renesas: Add RZ/V2M pin and gpio controller driver") Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250305163753.34913-4-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-03-06pinctrl: renesas: rzg2l: Fix missing of_node_put() callFabrizio Castro
of_parse_phandle_with_fixed_args() requires its caller to call into of_node_put() on the node pointer from the output structure, but such a call is currently missing. Call into of_node_put() to rectify that. Fixes: c4c4637eb57f ("pinctrl: renesas: Add RZ/G2L pin and gpio controller driver") Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250305163753.34913-3-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-03-05pinctrl: bcm281xx: Add support for BCM21664 pinmuxArtur Weber
BCM21664 is another chip from the Kona line of Broadcom SoCs, and its pinmux shares a lot of similarities with the BCM281xx pinmux. Add support for the BCM21664 pinmux controller to the BCM281xx driver. This also enables pinmux support for the BCM23550, which has an identical pinmux config to the BCM21664 (hence they can share a single compatible, brcm,bcm21664-pinctrl). Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/20250303-bcm21664-pinctrl-v3-4-5f8b80e4ab51@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-05pinctrl: bcm281xx: Provide pinctrl device info as OF platform dataArtur Weber
Introduce a new struct type, "bcm281xx_pinctrl_info", that holds information about the pins, pin functions and regmap config for a pin control chip. Create such a struct for the BCM218xx and pass it as device data for the OF compatible match. This is done in preparation for introducing additional chip types to the driver. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/20250303-bcm21664-pinctrl-v3-3-5f8b80e4ab51@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-05pinctrl: bcm281xx: Use "unsigned int" instead of bare "unsigned"Artur Weber
Replace uses of bare "unsigned" with "unsigned int" to fix checkpatch warnings. No functional change. Signed-off-by: Artur Weber <aweber.kernel@gmail.com> Link: https://lore.kernel.org/20250303-bcm21664-pinctrl-v3-2-5f8b80e4ab51@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-05pinctrl: amd: isp411: Add amdisp GPIO pinctrlPratap Nirujogi
Add pinctrl driver support for AMD SoC with isp41 hw ip block. Signed-off-by: Pratap Nirujogi <pratap.nirujogi@amd.com> Link: https://lore.kernel.org/20250304232051.2936557-1-pratap.nirujogi@amd.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-04pinctrl: pinconf-generic: Fix spelling mistake "paramers" -> "parameters"Colin Ian King
There is a spelling mistake in a dev_err message. Fix it. Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Link: https://lore.kernel.org/20250303092826.318638-1-colin.i.king@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-04pinctrl: meson: fix pin input property for a4Xianwei Zhao
The register of pin input attribute means the opposite. value of reigster meaning is 1 for input and 0 for output. So fix it. Fixes: 6e9be3abb78c ("pinctrl: Add driver support for Amlogic SoCs") Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/20250303-fix-a4-pinctl-v1-1-6579888b4272@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-04pinctrl: bcm2835: don't -EINVAL on alternate funcs from get_direction()Bartosz Golaszewski
Since commit 9d846b1aebbe ("gpiolib: check the return value of gpio_chip::get_direction()") we check the return value of the get_direction() callback as per its API contract. This driver returns -EINVAL if the pin in question is set to one of the alternative (non-GPIO) functions. This isn't really an error that should be communicated to GPIOLIB so default to returning the "safe" value of INPUT in this case. The GPIO subsystem does not have the notion of "unknown" direction. Fixes: 9d846b1aebbe ("gpiolib: check the return value of gpio_chip::get_direction()") Reported-by: Mark Brown <broonie@kernel.org> Closes: https://lore.kernel.org/all/Z7VFB1nST6lbmBIo@finisterre.sirena.org.uk/ Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Stefan Wahren <wahrenst@gmx.net> Link: https://lore.kernel.org/20250219102750.38519-1-brgl@bgdev.pl Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-04pinctrl: rockchip: Add support for RK3528Steven Liu
Add gpio and pinctrl support for the 5 GPIO banks on RK3528. Signed-off-by: Steven Liu <steven.liu@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/20250228064024.3200000-4-jonas@kwiboo.se Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-03-03pinctrl: intel: drop repeated config dependencyRaag Jadav
We already have ACPI dependency for Intel pinctrl menu. No need to repeat it. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2025-03-03pinctrl: samsung: add support for exynos7870 pinctrlKaustabh Chakraborty
Add support for the Exynos7870 SoC pin-controller in the pinctrl driver. It has 8 GPIO banks, and 3-bit PINCFG_TYPE_DRV width. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Link: https://lore.kernel.org/r/20250301-exynos7870-pinctrl-v3-3-ba1da9d3cd2f@disroot.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-02-28pinctrl: qcom: Add test case for TLMM interrupt handlingBjorn Andersson
While looking at the X1E PDC GPIO interrupts it became clear that we're lacking a convenient and accessible way to validate if the TLMM interrupt code performing as expected. This introduces a kunit-based "hack" that relies on pin bias/pull configuration to tickle the interrupt logic in non-connected pins to allow us to evaluate that an expected number of interrupts are delivered. The bias/pull configuration is done with mmio accesses directly from the test code, to avoid having to programmatically acquire and drive the pinconf interface for the test pin. This limits the scalability of the code to targets with a particular register layout, but serves our needs for now. The pin to be used for testing is specified by the tester using the "tlmm-test.gpio" module parameter. Worth mentioning is that some of the test cases currently fails for GPIOs that is not backed by PDC (i.e. "non-wakeup" GPIOs), as lingering latched interrupt state is being delivered at IRQ request time. Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> Link: https://lore.kernel.org/20250227-tlmm-test-v1-1-d18877b4a5db@oss.qualcomm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-28pinctrl-tegra: Add config property GPIO modePrathamesh Shete
The SFIO/GPIO select bit is a crucial part of Tegra's pin multiplexing system: - When set to 1, the pin operates in SFIO mode, controlled by the pin's assigned special function. - When set to 0, the pin operates as a general-purpose GPIO. This SFIO/GPIO select bit that is set for a given pin is not displayed, adding the support to retrieve this information from the pinmux set for each pin. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Link: https://lore.kernel.org/20241217153249.5712-1-pshete@nvidia.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-28pinctrl: wpcm450: Switch to use for_each_gpiochip_node() helperAndy Shevchenko
Switch the code to use for_each_gpiochip_node() helper. While at it, correct header inclusion as device property APIs are provided in property.h. Reviewed-by: J. Neuschäfer <j.ne@posteo.net> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/20250220155036.2734838-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-28Merge tag 'renesas-pinctrl-for-v6.15-tag1' of ↵Linus Walleij
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v6.15 - Add suspend/resume support for pull up/down on RZ/G3S, - Miscellaneous fixes and improvements. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-28Merge branch 'ib-amlogic-a4' into develLinus Walleij
Merge immutable branch into devel for next. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-28pinctrl: Add driver support for Amlogic SoCsXianwei Zhao
Add a new pinctrl driver for Amlogic SoCs. All future Amlogic SoCs pinctrl drives use this, such A4, A5, S6, S7 etc. To support new Amlogic SoCs, only need to add the corresponding dts file. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/20250212-amlogic-pinctrl-v5-3-282bc2516804@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-28pinctrl: pinconf-generic: Add API for pinmux propertity in DTS fileXianwei Zhao
When describing pin mux func through pinmux propertity, a standard API is added for support. The pinmux contains pin identification and mux values, which can include multiple pins. And groups configuration use other word. DTS such as: func-name { group_alias: group-name{ pinmux= <pin_id << 8 | mux_value)>, <pin_id << 8 | mux_value)>; bias-pull-up; drive-strength-microamp = <4000>; }; }; Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/20250212-amlogic-pinctrl-v5-2-282bc2516804@amlogic.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-27Merge branch 'ib-sophgo' into develLinus Walleij
Pull the immutable branch into devel for next. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-27pinctrl: sophgo: add support for SG2044 SoCInochi Amaoto
SG2044 share the share common control logic with SG2042. So only pin definition is needed. Add pin definition driver for SG2044 SoC. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/20250211051801.470800-8-inochiama@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-27pinctrl: sophgo: add support for SG2042 SoCInochi Amaoto
Add base driver for SG2042 SoC and pin definition. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/20250211051801.470800-7-inochiama@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-27pinctrl: sophgo: introduce generic probe functionInochi Amaoto
Since different series of the Sophgo chip share a common pinctrl data structure. It is necessary to add a common probe function to alloc the this data structure. Add pctrl_init callback to allow soc to perform its own initialization. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/20250211051801.470800-5-inochiama@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2025-02-27pinctrl: sophgo: generalize shareable code of cv18xx pinctrl driverInochi Amaoto
With generic data structure, it is possible to generalize vddio operators and DT parsing code of cv18xx pinctrl driver. Introduce sophgo_cfg_ops callback to allow the driver to adjust the soc logic and share common code. Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Link: https://lore.kernel.org/20250211051801.470800-4-inochiama@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
generated by cgit (git 2.34.1) at 2025-07-15 19:44:29 +0000