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2025-01-09spi: atmel-quadspi: Update to current device naming terminologyAlexander Dahl
For v6.9 the spi subsystem changed the terminology to host and target devices, see commit 99769a52464d ("spi: Update the "master/slave" terminology in documentation") for reference. Support for SAMA7G5 was forward ported recently from an old vendor branch before that terminology change, so naming for the new struct member is adapted to follow the current scheme. Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://patch.msgid.link/20250109094843.36014-1-ada@thorsis.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-01-09spi: fsl-spi: Remove display of virtual addressChristophe Leroy
The following appears in kernel log at boot: fsl_spi b01004c0.spi: at 0x(ptrval) (irq = 51), QE mode This is useless, so remove the display of that virtual address and display the MMIO address instead, just like serial core does. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://patch.msgid.link/8a37a960ff084dfdb9233849c00714e9317ae6a5.1736405336.git.christophe.leroy@csgroup.eu Signed-off-by: Mark Brown <broonie@kernel.org>
2025-01-09spi: Merge up v6.13-rc6Mark Brown
This fixes the i.MX6 and newer Meson platforms in my CI.
2025-01-08treewide: Introduce kthread_run_worker[_on_cpu]()Frederic Weisbecker
kthread_create() creates a kthread without running it yet. kthread_run() creates a kthread and runs it. On the other hand, kthread_create_worker() creates a kthread worker and runs it. This difference in behaviours is confusing. Also there is no way to create a kthread worker and affine it using kthread_bind_mask() or kthread_affine_preferred() before starting it. Consolidate the behaviours and introduce kthread_run_worker[_on_cpu]() that behaves just like kthread_run(). kthread_create_worker[_on_cpu]() will now only create a kthread worker without starting it. Signed-off-by: Frederic Weisbecker <frederic@kernel.org> Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
2025-01-06spi: atmel-quadspi: Use devm_ clock managementBence Csókás
Clean up error handling by using the new devm_ clock handling functions. This should make it easier to add new code, as we can eliminate the "goto ladder" in probe(). Signed-off-by: Bence Csókás <csokas.bence@prolan.hu> Link: https://patch.msgid.link/20241219142851.430959-1-csokas.bence@prolan.hu Signed-off-by: Mark Brown <broonie@kernel.org>
2025-01-06spi: rockchip-sfc: Support sclk_x2 versionJon Lin
SFC after version 8 supports dtr mode, so the IO is the binary output of the controller clock. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Link: https://patch.msgid.link/20241219142216.2123065-1-jon.lin@rock-chips.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-01-06spi: cadence-quadspi: Enable SPI_TX_QUADSanthosh Kumar K
Enable the SPI_TX_QUAD mode bit in the host->mode_bits to support data transmission over four lines to improve the performance. Tested the functionality on AM62Lx EVM (W25N01JW) in 1S-4S-4S mode. Signed-off-by: Santhosh Kumar K <s-k6@ti.com> Link: https://patch.msgid.link/20250102120544.1407152-1-s-k6@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-01-06spi: atmel-qspi: Memory barriers after memory-mapped I/OBence Csókás
The QSPI peripheral control and status registers are accessible via the SoC's APB bus, whereas MMIO transactions' data travels on the AHB bus. Microchip documentation and even sample code from Atmel emphasises the need for a memory barrier before the first MMIO transaction to the AHB-connected QSPI, and before the last write to its registers via APB. This is achieved by the following lines in `atmel_qspi_transfer()`: /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */ (void)atmel_qspi_read(aq, QSPI_IFR); However, the current documentation makes no mention to synchronization requirements in the other direction, i.e. after the last data written via AHB, and before the first register access on APB. In our case, we were facing an issue where the QSPI peripheral would cease to send any new CSR (nCS Rise) interrupts, leading to a timeout in `atmel_qspi_wait_for_completion()` and ultimately this panic in higher levels: ubi0 error: ubi_io_write: error -110 while writing 63108 bytes to PEB 491:128, written 63104 bytes After months of extensive research of the codebase, fiddling around the debugger with kgdb, and back-and-forth with Microchip, we came to the conclusion that the issue is probably that the peripheral is still busy receiving on AHB when the LASTXFER bit is written to its Control Register on APB, therefore this write gets lost, and the peripheral still thinks there is more data to come in the MMIO transfer. This was first formulated when we noticed that doubling the write() of QSPI_CR_LASTXFER seemed to solve the problem. Ultimately, the solution is to introduce memory barriers after the AHB-mapped MMIO transfers, to ensure ordering. Fixes: d5433def3153 ("mtd: spi-nor: atmel-quadspi: Add spi-mem support to atmel-quadspi") Cc: Hari.PrasathGE@microchip.com Cc: Mahesh.Abotula@microchip.com Cc: Marco.Cardellini@microchip.com Cc: stable@vger.kernel.org # c0a0203cf579: ("spi: atmel-quadspi: Create `atmel_qspi_ops`"...) Cc: stable@vger.kernel.org # 6.x.y Signed-off-by: Bence Csókás <csokas.bence@prolan.hu> Link: https://patch.msgid.link/20241219091258.395187-1-csokas.bence@prolan.hu Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-19spi: rockchip-sfc: Using normal memory for dmaJon Lin
Nornal memory CPU copy with cache invalidate is more efficient than uncache memory copy. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Link: https://patch.msgid.link/20241219010557.333327-1-jon.lin@rock-chips.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-18spi: rockchip-sfc: Fix error in remove progressJon Lin
Fix error in remove progress: [ 43.026148] Call trace: [ 43.026370] klist_next+0x1c/0x1d4 [ 43.026671] device_for_each_child+0x48/0xac [ 43.027049] spi_unregister_controller+0x30/0x130 [ 43.027469] rockchip_sfc_remove+0x48/0x80 [spi_rockchip_sfc] Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Link: https://patch.msgid.link/20241218154741.901591-1-jon.lin@rock-chips.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-18spi: atmel-quadspi: Factor out switching to Serial Memory Mode to functionBence Csókás
SAMA7G5 support (that was forward-ported from v6.1) re-introduced a bug that was fixed in v6.12, thankfully only in the codepath of the new SoC. But to prevent similar mistakes in the future, we split out the offending code to a function, and use this, fixed version everywhere. To facilitate this, support function `atmel_qspi_update_config()` also had to be moved upwards. For best viewing experience, use `--color-moved-ws="allow-indentation-change" --color-moved`. Fixes: 5af42209a4d2 ("spi: atmel-quadspi: Add support for sama7g5 QSPI") Reported-by: Alexander Dahl <ada@thorsis.com> Closes: https://lore.kernel.org/linux-spi/20241218-appliance-jaws-90773405977a@thorsis.com/ Signed-off-by: Bence Csókás <csokas.bence@prolan.hu> Link: https://patch.msgid.link/20241218151754.365519-1-csokas.bence@prolan.hu Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-17spi: atmel-quadspi: Refactor to allow supportingMark Brown
Merge series from "Csókás, Bence" <csokas.bence@prolan.hu>: This is based on Tudor Ambarus' submission from 2021, and my refactor of said sumbission from roughly a month ago. Link: https://lore.kernel.org/linux-spi/20211214133404.121739-1-tudor.ambarus@microchip.com/ Link: https://lore.kernel.org/linux-spi/20241030084445.2438750-1-csokas.bence@prolan.hu/ This time, I submit both my refactor and the diff between it and the original submission, rebased on top of Linus' master, namely: commit 7d4050728c83 ("Merge tag 'vfs-6.13-rc1.fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vfs/vfs") Tested on a SAMA5G27C, we'll soon test on a SAMA7G54 we got from Microchip for this purpose.
2024-12-17spi: spidev: Align ordering of spidev_spi_ids[] and spidev_dt_ids[]Uwe Kleine-König
There is a 1:1 correspondance between the list of spi device-ids and the devicetree compatibles. The latter is ordered alphabetically by vendor and device. To simplify keeping the two lists in sync, mention the vendor in a comment for the spi device-ids and order alphabetically, too. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://patch.msgid.link/20241217114226.1223724-2-u.kleine-koenig@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-16spi: rockchip-sfc: Support pm opsJon Lin
Support system_sleep and runtime_pm ops. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Link: https://patch.msgid.link/20241208130311.1324024-1-jon.lin@rock-chips.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-16spi: atmel-quadspi: Add support for sama7g5 QSPITudor Ambarus
The sama7g5 QSPI controller uses dedicated clocks for the QSPI Controller Interface and the QSPI Controller Core, and requires synchronization before accessing registers or bit fields. QSPI_SR.SYNCBSY must be zero before accessing any of the bits: QSPI_CR.QSPIEN, QSPI_CR.QSPIDIS, QSPI_CR.SRFRSH, QSPI_CR.SWRST, QSPI_CR.UPDCFG, QSPI_CR.STTFR, QSPI_CR.RTOUT, QSPI_CR.LASTXFER. Also, the QSPI controller core configuration can be updated by writing the QSPI_CR.UPDCFG bit to ‘1’. This is needed by the following registers: QSPI_MR, QSPI_SCR, QSPI_IAR, QSPI_WICR, QSPI_IFR, QSPI_RICR, QSPI_SMR, QSPI_SKR,QSPI_REFRESH, QSPI_WRACNT QSPI_PCALCFG. The Octal SPI supports frequencies up to 200 MHZ DDR. The need for output impedance calibration arises. To avoid the degradation of the signal quality, a PAD calibration cell is used to adjust the output impedance to the driven I/Os. The transmission flow requires different sequences for setting the configuration and for the actual transfer, than what is in the sama5d2 and sam9x60 versions of the IP. Different interrupts are handled. aq->ops->set_cfg() and aq->ops->transfer() are introduced to help differentiating the flows. Tested single and octal SPI mode with mx66lm1g45g. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20211214133404.121739-1-tudor.ambarus@microchip.com [varshini.rajendran@microchip.com: Fixed conflicts and ported to 6.1.4] Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> [ csokas.bence: Forward-port to master and address feedback ] Signed-off-by: Csókás, Bence <csokas.bence@prolan.hu> Link: https://patch.msgid.link/20241128174316.3209354-3-csokas.bence@prolan.hu Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-16spi: atmel-quadspi: Create `atmel_qspi_ops` to support newer SoC familiesCsókás, Bence
Refactor the code to introduce an ops struct, to prepare for merging support for later SoCs, such as SAMA7G5. This code was based on the vendor's kernel (linux4microchip). Cc'ing original contributors. Signed-off-by: Csókás, Bence <csokas.bence@prolan.hu> Link: https://patch.msgid.link/20241128174316.3209354-2-csokas.bence@prolan.hu Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-10spi: Unify and simplify fwnode related checksMark Brown
Merge series from Andy Shevchenko <andriy.shevchenko@linux.intel.com>: A couple of cleanups on top of recently added change.
2024-12-10spi: Merge up fixesMark Brown
Silly add/add conflict in the Cadence QuadSPI driver.
2024-12-09spi: mxs: support effective_speed_hzStefan Wahren
Setting spi_transfer->effective_speed_hz in transfer_one_message so that SPI client driver can use it. Signed-off-by: Stefan Wahren <wahrenst@gmx.net> Link: https://patch.msgid.link/20241209111316.4767-1-wahrenst@gmx.net Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-09spi: zynq-qspi: Add check for clk_enable()Mingwei Zheng
Add check for the return value of clk_enable() to catch the potential error. Fixes: c618a90dcaf3 ("spi: zynq-qspi: Drop GPIO header") Signed-off-by: Mingwei Zheng <zmw12306@gmail.com> Signed-off-by: Jiasheng Jiang <jiashengjiangcool@gmail.com> Link: https://patch.msgid.link/20241207015206.3689364-1-zmw12306@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-09spi: Deduplicate deferred probe checks in spi_probe()Andy Shevchenko
Deduplicate deferred probe checks in spi_probe() and enable the error message for ACPI case as well. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20241208195635.1271656-3-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-09spi: Unify firmware node type checksAndy Shevchenko
The few functions are using different approaches on how to check for the type of firmware node. Unify them to use a modern way of it. With that in place it becomes obvious that no need to have independent conditionals when they are dependent and hence the code generation can be improved a little bit (clang-18, x86_64): add/remove: 0/0 grow/shrink: 2/2 up/down: 16/-46 (-30) Total: Before=49801, After=49771, chg -0.06% Meanwhile no functional changes intended. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20241208195635.1271656-2-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-09spi: spi-cadence-qspi: Disable STIG mode for Altera SoCFPGA.Niravkumar L Rabara
STIG mode is enabled by default for less than 8 bytes data read/write. STIG mode doesn't work with Altera SocFPGA platform due hardware limitation. Add a quirks to disable STIG mode for Altera SoCFPGA platform. Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com> Link: https://patch.msgid.link/20241204063338.296959-1-niravkumar.l.rabara@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-09spi: rockchip: Fix PM runtime count on no-op csChristian Loehle
The early bail out that caused an out-of-bounds write was removed with commit 5c018e378f91 ("spi: spi-rockchip: Fix out of bounds array access") Unfortunately that caused the PM runtime count to be unbalanced and underflowed on the first call. To fix that reintroduce a no-op check by reading the register directly. Cc: stable@vger.kernel.org Fixes: 5c018e378f91 ("spi: spi-rockchip: Fix out of bounds array access") Signed-off-by: Christian Loehle <christian.loehle@arm.com> Link: https://patch.msgid.link/1f2b3af4-2b7a-4ac8-ab95-c80120ebf44c@arm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-09spi: aspeed: Fix an error handling path in aspeed_spi_[read|write]_user()Christophe JAILLET
A aspeed_spi_start_user() is not balanced by a corresponding aspeed_spi_stop_user(). Add the missing call. Fixes: e3228ed92893 ("spi: spi-mem: Convert Aspeed SMC driver to spi-mem") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://patch.msgid.link/4052aa2f9a9ea342fa6af83fa991b55ce5d5819e.1732051814.git.christophe.jaillet@wanadoo.fr Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-09spi: Merge up v6.12-rc2Mark Brown
This has fixes for several boards which help my testing a lot.
2024-12-06Merge tag 'spi-fix-v6.13-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A few small driver specific fixes and device ID updates for SPI. The Apple change flags the driver as being compatible with the core's GPIO chip select support, fixing support for some systems" * tag 'spi-fix-v6.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: omap2-mcspi: Fix the IS_ERR() bug for devm_clk_get_optional_enabled() spi: intel: Add Panther Lake SPI controller support spi: apple: Set use_gpio_descriptors to true spi: mpc52xx: Add cancel_work_sync before module remove
2024-12-05spi: omap2-mcspi: Fix the IS_ERR() bug for devm_clk_get_optional_enabled()Purushothama Siddaiah
The devm_clk_get_optional_enabled() function returns error pointers(PTR_ERR()). So use IS_ERR() to check it. Verified on K3-J7200 EVM board, without clock node mentioned in the device tree. Signed-off-by: Purushothama Siddaiah <psiddaiah@mvista.com> Reviewed-by: Corey Minyard <cminyard@mvista.com> Link: https://patch.msgid.link/20241205070426.1861048-1-psiddaiah@mvista.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-04spi: spi-kspi2: Add KEBA SPI controller supportGerhard Engleder
The KEBA SPI controller is found in the system FPGA of KEBA PLC devices. It is used to connect the SPI flash chip of the FPGA and some SPI devices. It is a simple SPI controller with configurable speed. The hardware supports only single byte transfers. There are no FIFOs or interrupts. Signed-off-by: Gerhard Engleder <eg@keba.com> Link: https://patch.msgid.link/20241202194003.57679-1-gerhard@engleder-embedded.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-04spi: rockchip-sfc: Optimize the judgment mechanism completed by the controllerJon Lin
There is very little data left in fifo, and the controller will complete the transmission in a short period of time, so use readl_poll_timeout() for busy wait 10us to accelerate response. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Link: https://patch.msgid.link/20241203013513.2628810-1-jon.lin@rock-chips.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-04spi: intel: Add Panther Lake SPI controller supportAapo Vienamo
The Panther Lake SPI controllers are compatible with the Cannon Lake controllers. Add support for following SPI controller device IDs: - H-series: 0xe323 - P-series: 0xe423 - U-series: 0xe423 Signed-off-by: Aapo Vienamo <aapo.vienamo@iki.fi> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Link: https://patch.msgid.link/20241204080208.1036537-1-mika.westerberg@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-02module: Convert symbol namespace to string literalPeter Zijlstra
Clean up the existing export namespace code along the same lines of commit 33def8498fdd ("treewide: Convert macro and uses of __section(foo) to __section("foo")") and for the same reason, it is not desired for the namespace argument to be a macro expansion itself. Scripted using git grep -l -e MODULE_IMPORT_NS -e EXPORT_SYMBOL_NS | while read file; do awk -i inplace ' /^#define EXPORT_SYMBOL_NS/ { gsub(/__stringify\(ns\)/, "ns"); print; next; } /^#define MODULE_IMPORT_NS/ { gsub(/__stringify\(ns\)/, "ns"); print; next; } /MODULE_IMPORT_NS/ { $0 = gensub(/MODULE_IMPORT_NS\(([^)]*)\)/, "MODULE_IMPORT_NS(\"\\1\")", "g"); } /EXPORT_SYMBOL_NS/ { if ($0 ~ /(EXPORT_SYMBOL_NS[^(]*)\(([^,]+),/) { if ($0 !~ /(EXPORT_SYMBOL_NS[^(]*)\(([^,]+), ([^)]+)\)/ && $0 !~ /(EXPORT_SYMBOL_NS[^(]*)\(\)/ && $0 !~ /^my/) { getline line; gsub(/[[:space:]]*\\$/, ""); gsub(/[[:space:]]/, "", line); $0 = $0 " " line; } $0 = gensub(/(EXPORT_SYMBOL_NS[^(]*)\(([^,]+), ([^)]+)\)/, "\\1(\\2, \"\\3\")", "g"); } } { print }' $file; done Requested-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://mail.google.com/mail/u/2/#inbox/FMfcgzQXKWgMmjdFwwdsfgxzKpVHWPlc Acked-by: Greg KH <gregkh@linuxfoundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2024-12-02spi: cadence-quadspi: Add support for device resetMark Brown
Merge series from Srikanth Boyapally <srikanth.boyapally@amd.com>: Add support for device reset via OSPI on Versal Gen 2 platform.
2024-12-02spi: rockchip-sfc: Support ACPIJon Lin
Compatible with ACPI. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Link: https://patch.msgid.link/20241120012208.1193034-1-jon.lin@rock-chips.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-02spi: sc18is602: Switch to generic firmware properties and drop of_match_ptr()Andy Shevchenko
This enables using the driver with other firmware types such as ACPI via PRP0001. Also part of a general attempt to move drivers over to generic properties to avoid opportunities for cut and paste. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://patch.msgid.link/20241114205051.3747458-1-andriy.shevchenko@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-02spi: spidev: Add an entry for lwn,bk4-spiFabio Estevam
Currently, the compatible string used for Liebherr's BK4 external SPI controller device is "lwn,bk4", which is the same as the board compatible string documented at fsl.yaml. This causes several dt-schema warnings: make dtbs_check DT_SCHEMA_FILES=fsl.yaml ... ['lwn,bk4'] is too short 'lwn,bk4' is not one of ['tq,imx8dxp-tqma8xdp-mba8xx'] 'lwn,bk4' is not one of ['tq,imx8qxp-tqma8xqp-mba8xx'] 'lwn,bk4' is not one of ['armadeus,imx1-apf9328', 'fsl,imx1ads'] ... Add a more specific "lwn,bk4-spi" compatible string entry for this device to fix the problem. The original "lwn,bk4" is kept to keep compatibility with old DTBs. Signed-off-by: Fabio Estevam <festevam@denx.de> Link: https://patch.msgid.link/20241023120015.1049008-2-festevam@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-02spi: cadence-quadspi: Support for device reset via OSPI controllerSrikanth Boyapally
Add support for flash device reset via ospi controller, instead of using GPIO, as ospi IP has device reset feature on Versal Gen2 platform. Signed-off-by: Srikanth Boyapally <srikanth.boyapally@amd.com> Link: https://patch.msgid.link/20241120120951.56327-4-srikanth.boyapally@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-02spi: cadence-quadspi: Use quirks to set dma_set_mask instead of compatible ↵Srikanth Boyapally
string for 64-bit DMA support Remove device compatible property check and instead use quirks to program DMA addressing. Signed-off-by: Srikanth Boyapally <srikanth.boyapally@amd.com> Link: https://patch.msgid.link/20241120120951.56327-3-srikanth.boyapally@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-02spi: apple: Set use_gpio_descriptors to trueSasha Finkelstein
There is at least one peripheral that is attached to this controller and can not use native CS. Make it possible to use a GPIO instead. Signed-off-by: Sasha Finkelstein <fnkl.kernel@gmail.com> Reviewed-by: Janne Grunau <j@jannau.net> Link: https://patch.msgid.link/20241127-gpio-descs-v1-1-c586b518a7d5@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-02spi: mpc52xx: Add cancel_work_sync before module removePei Xiao
If we remove the module which will call mpc52xx_spi_remove it will free 'ms' through spi_unregister_controller. while the work ms->work will be used. The sequence of operations that may lead to a UAF bug. Fix it by ensuring that the work is canceled before proceeding with the cleanup in mpc52xx_spi_remove. Fixes: ca632f556697 ("spi: reorganize drivers") Signed-off-by: Pei Xiao <xiaopei01@kylinos.cn> Link: https://patch.msgid.link/1f16f8ae0e50ca9adb1dc849bf2ac65a40c9ceb9.1732783000.git.xiaopei01@kylinos.cn Signed-off-by: Mark Brown <broonie@kernel.org>
2024-11-28Merge tag 'spi-fix-v6.13-merge-window' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A few fairly minor driver specific fixes, plus one core fix for the handling of deferred probe on ACPI systems - ignoring probe deferral and incorrectly treating it like a fatal error while parsing the generic ACPI bindings for SPI devices" * tag 'spi-fix-v6.13-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: Fix acpi deferred irq probe spi: atmel-quadspi: Fix register name in verbose logging function spi-imx: prevent overflow when estimating transfer time spi: rockchip-sfc: Embedded DMA only support 4B aligned address
2024-11-26spi: Fix acpi deferred irq probeStanislaw Gruszka
When probing spi device take care of deferred probe of ACPI irq gpio similar like for OF/DT case. >From practical standpoint this fixes issue with vsc-tp driver on Dell XP 9340 laptop, which try to request interrupt with spi->irq equal to -EPROBE_DEFER and fail to probe with the following error: vsc-tp spi-INTC10D0:00: probe with driver vsc-tp failed with error -22 Suggested-by: Hans de Goede <hdegoede@redhat.com> Fixes: 33ada67da352 ("ACPI / spi: attach GPIO IRQ from ACPI description to SPI device") Cc: stable@vger.kernel.org Signed-off-by: Stanislaw Gruszka <stanislaw.gruszka@linux.intel.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Alexis Lothoré <alexis.lothore@bootlin.com> # Dell XPS9320, ov01a10 Link: https://patch.msgid.link/20241122094224.226773-1-stanislaw.gruszka@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-11-26spi: atmel-quadspi: Fix register name in verbose logging functionCsókás, Bence
`atmel_qspi_reg_name()` is used for pretty-printing register offsets for verbose logging of register accesses. However, due to a typo (likely a copy-paste error), QSPI_RD's offset prints as "MR", the name of the previous register. Fix this typo. Fixes: c528ecfbef04 ("spi: atmel-quadspi: Add verbose debug facilities to monitor register accesses") Signed-off-by: Csókás, Bence <csokas.bence@prolan.hu> Reviewed-by: Alexander Dahl <ada@thorsis.com> Link: https://patch.msgid.link/20241122141302.2599636-1-csokas.bence@prolan.hu Signed-off-by: Mark Brown <broonie@kernel.org>
2024-11-22Merge tag 'mtd/for-6.13' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD updates from Miquel Raynal: "MTD device changes: - switch platform_driver back to remove() - misc fixes SPI-NAND changes: - a load of fixes to Winbond manufacturer driver - structure constification Raw NAND changes: - improve the power management of the GPMI driver - Davinci driver clean-ups - fix leak in the Atmel driver - fix some typos in the core SPI NOR changes: - Introduce byte swap support for 8D-8D-8D mode and a user for it: macronix. SPI NOR flashes may swap the bytes on a 16-bit boundary when configured in Octal DTR mode. For such cases the byte order is propagated through SPI MEM to the SPI controllers so that the controllers swap the bytes back at runtime. This avoids breaking the boot sequence because of the endianness problems that appear when the bootloaders use 1-1-1 and the kernel uses 8D-8D-8D with byte swap support. Along with the SPI MEM byte swap support we queue a patch for the SPI MXIC controller that swaps the bytes back at runtime" * tag 'mtd/for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (25 commits) mtd: spi-nor: core: replace dummy buswidth from addr to data mtd: spi-nor: winbond: add "w/ and w/o SFDP" comment mtd: spi-nor: spansion: Use nor->addr_nbytes in octal DTR mode in RD_ANY_REG_OP mtd: Switch back to struct platform_driver::remove() mtd: cfi_cmdset_0002: remove redundant assignment to variable ret mtd: spinand: Constify struct nand_ecc_engine_ops MAINTAINERS: add mailing list for GPMI NAND driver mtd: spinand: winbond: Sort the devices mtd: spinand: winbond: Ignore the last ID characters mtd: spinand: winbond: Fix 512GW, 01GW, 01JW and 02JW ECC information mtd: spinand: winbond: Fix 512GW and 02JW OOB layout mtd: nand: raw: gpmi: improve power management handling mtd: nand: raw: gpmi: switch to SYSTEM_SLEEP_PM_OPS mtd: rawnand: davinci: use generic device property helpers mtd: rawnand: davinci: break the line correctly mtd: rawnand: davinci: order headers alphabetically mtd: rawnand: atmel: Fix possible memory leak mtd: rawnand: Correct multiple typos in comments mtd: hyperbus: rpc-if: Add missing MODULE_DEVICE_TABLE mtd: spi-nor: add support for Macronix Octal flash ...
2024-11-21Merge tag 'nand/for-6.13' into mtd/nextMiquel Raynal
SPI-NAND changes: A load of fixes to Winbond manufacturer driver have been done, plus a structure constification. Raw NAND changes: The GPMI driver has been improved on the power management side. The Davinci driver has been cleaned up. A leak in the Atmel driver plus some typos in the core have been fixed.
2024-11-21spi-imx: prevent overflow when estimating transfer timeAntonio Quartulli
The words delay is computed by multiplying two unsigned ints and by adding up the result to a u64 variable. The multiplication, however, is performed with 32bit math thus losing data when the actual result is larger than UINT32_MAX. Fix the operation by casting the first operand to u64, thus forcing the multiplication to be performed with 64bit math. This fixes 1 OVERFLOW_BEFORE_WIDEN issue reported by Coverity Report: CID 1601859: Integer handling issues (OVERFLOW_BEFORE_WIDEN) Cc: Mark Brown <broonie@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Antonio Quartulli <antonio@mandelbit.com> Link: https://patch.msgid.link/20241115220202.31086-1-antonio@mandelbit.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-11-20Merge tag 'spi-v6.13' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi updates from Mark Brown: "The only real core work we've got this time around is the completion of the transition to the new host/target naming for the core APIs, Kconfig still needs doing but that's a lot less invasive. Otherwise the big changes are the new drivers that have been added: - Completion of the conversion to spi_alloc_host()/_target() and removal of the old naming. - Cleanups for Rockchip drivers, these brought in a new logging helper in the driver core for warnings during probe. - Support for configuration of the word delay via spidev_test. - Support for AMD HID2 controllers, Apple SPI controller and Realtek SPI-NAND controllers" * tag 'spi-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (58 commits) spi: imx: support word delay spi: imx: pass struct spi_transfer to prepare_transfer() spi: cs42l43: Add GPIO speaker id support to the bridge configuration spi: Delete useless checks spi: apple: Remove unnecessary .owner for apple_spi_driver spi: spidev_test: add support for word delay spi: apple: Add driver for Apple SPI controller spi: dt-bindings: apple,spi: Add binding for Apple SPI controllers spi: Use of_property_present() for non-boolean properties spi: zynqmp-gqspi: Undo runtime PM changes at driver exit time​ spi: spi-mem: rtl-snand: Correctly handle DMA transfers spi: tegra210-quad: Avoid shift-out-of-bounds spi: axi-spi-engine: Emit trace events for spi transfers dt-bindings: spi: sprd,sc9860-spi: convert to YAML spi: Replace deprecated PCI functions spi: dt-bindings: samsung: Add a compatible for samsung,exynos8895-spi spi: spi-mem: Add Realtek SPI-NAND controller dt-bindings: spi: Add realtek,rtl9301-snand spi: make class structs const spi: dt-bindings: brcm,bcm2835-aux-spi: Convert to dtschema ...
2024-11-19spi: rockchip-sfc: Embedded DMA only support 4B aligned addressJon Lin
Controller limitations. Signed-off-by: Jon Lin <jon.lin@rock-chips.com> Link: https://patch.msgid.link/20241118145646.2609039-1-jon.lin@rock-chips.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-11-14spi: imx: support word delay in ecspiMark Brown
Merge series from Jonas Rebmann <jre@pengutronix.de>: The i.MX SPI controller supports inserting a configurable delay between subsequent words, which is needed for some slower devices that couldn't keep up otherwise. This patch series introduces support for the word delay parameters for i.MX51 onwards. The SPI clock (CSRC=0) was chosen as the clock source over the also available 32.768 KHz Low-Frequency Reference Clock (CSRC=1). The sample period control bits (SAMPLE_PERIOD) are set to the selected word delay converted to SPI clock cycles. A deviation from the requested number of wait cycles and the actual word delay was observed via both software timings and oscilloscope measurements and accounted for. The Chip Select Delay Control bits in the Sample Period Control Register remain zero. Behaviour on i.MX35 and earlier, where the CSPI interface is used, remains unchanged.
2024-11-13spi: imx: support word delayJonas Rebmann
Implement support for the word delay feature of i.MX51 (and onwards) via the ECSPI interface. Convert the requested delay to SPI cycles and account for an extra inter-word delay inserted by the controller in addition to the requested number of cycles, which was observed when testing this patch. Disable dynamic burst when word delay is set. As the configurable delay period in the controller is inserted after bursts, the burst length must equal the word length. Account for word delay in the transfer time estimation for polling_limit_us. Signed-off-by: Jonas Rebmann <jre@pengutronix.de> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/20241113-imx-spi-word-delay-v2-2-2b65b737bf29@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
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