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2025-02-02dt-bindings: clock: qcom: Add CAMCC clocks for QCS8300Imran Shaik
The QCS8300 camera clock controller is a derivative of SA8775P, but has an additional clock and minor differences. Hence, reuse the SA8775P camera bindings and add additional clock required for QCS8300. Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Link: https://lore.kernel.org/r/20250109-qcs8300-mm-patches-new-v4-3-63e8ac268b02@quicinc.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-02-02dt-bindings: clock: qcom: Add GPU clocks for QCS8300Imran Shaik
The QCS8300 GPU clock controller is a derivative of SA8775P, but has few additional clocks and minor differences. Hence, reuse gpucc bindings of SA8775P and add additional clocks required for QCS8300. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Link: https://lore.kernel.org/r/20250109-qcs8300-mm-patches-new-v4-1-63e8ac268b02@quicinc.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
2025-01-21Merge branches 'clk-airoha', 'clk-rockchip', 'clk-stm', 'clk-thead' and ↵Stephen Boyd
'clk-bcm' into clk-next * clk-airoha: clk: en7523: Add clock for eMMC for EN7581 dt-bindings: clock: add ID for eMMC for EN7581 dt-bindings: clock: drop NUM_CLOCKS define for EN7581 clk: en7523: Rework clock handling for different clock numbers clk: en7523: Initialize num before accessing hws in en7523_register_clocks() clk: en7523: Fix wrong BUS clock for EN7581 clk: amlogic: axg-audio: revert reset implementation Revert "clk: Fix invalid execution of clk_set_rate" * clk-rockchip: clk: rockchip: rk3588: make refclko25m_ethX critical clk: rockchip: rk3588: drop RK3588_LINKED_CLK clk: rockchip: implement linked gate clock support clk: rockchip: expose rockchip_clk_set_lookup clk: rockchip: rk3588: register GATE_LINK later clk: rockchip: support clocks registered late * clk-stm: clk: stm32f4: support spread spectrum clock generation clk: stm32f4: use FIELD helpers to access the PLLCFGR fields dt-bindings: clock: st,stm32-rcc: support spread spectrum clocking dt-bindings: clock: convert stm32 rcc bindings to json-schema * clk-thead: clk: thead: Fix cpu2vp_clk for TH1520 AP_SUBSYS clocks clk: thead: Add CLK_IGNORE_UNUSED to fix TH1520 boot clk: thead: Fix clk gate registration to pass flags * clk-bcm: clk: bcm: rpi: Add disp clock clk: bcm: rpi: Create helper to retrieve private data clk: bcm: rpi: Enable minimize for all firmware clocks clk: bcm: rpi: Allow cpufreq driver to also adjust gpu clocks clk: bcm: rpi: Add ISP to exported clocks
2025-01-21Merge branches 'clk-microchip', 'clk-xilinx', 'clk-allwinner', 'clk-imx' and ↵Stephen Boyd
'clk-qcom' into clk-next * clk-microchip: clk: at91: sama7d65: add sama7d65 pmc driver dt-bindings: clock: Add SAMA7D65 PMC compatible string dt-bindings: clocks: atmel,at91sam9x5-sckc: add sama7d65 clk: at91: sckc: Use SCKC_{TD, MD}_SLCK IDs for clk32k clocks dt-bindings: clk: at91: Add clock IDs for the slow clock controller * clk-xilinx: clk: clocking-wizard: calculate dividers fractional parts dt-bindings: clock: xilinx: Add reset GPIO for VCU dt-bindings: clock: xilinx: Convert VCU bindings to dtschema * clk-allwinner: clk: sunxi-ng: h616: Reparent CPU clock during frequency changes clk: sunxi-ng: a64: stop force-selecting PLL-MIPI as TCON0 parent clk: sunxi-ng: a64: drop redundant CLK_PLL_VIDEO0_2X and CLK_PLL_MIPI dt-bindings: clock: sunxi: Export PLL_VIDEO_2X and PLL_MIPI * clk-imx: clk: imx: Apply some clks only for i.MX93 arm64: dts: imx93: Use IMX93_CLK_SPDIF_IPG as SPDIF IPG clock clk: imx93: Add IMX93_CLK_SPDIF_IPG clock dt-bindings: clock: imx93: Add SPDIF IPG clk clk: imx: pll14xx: Add 208 MHz and 416 MHz entries for PLL1416x clk: imx8mp: Fix clkout1/2 support * clk-qcom: (63 commits) clk: qcom: Select CLK_X1E80100_GCC in config CLK_X1P42100_GPUCC dt-bindings: clock: move qcom,x1e80100-camcc to its own file clk: qcom: smd-rpm: Add clocks for MSM8940 dt-bindings: clock: qcom,rpmcc: Add MSM8940 compatible clk: qcom: smd-rpm: Add clocks for MSM8937 dt-bindings: clock: qcom,rpmcc: Add MSM8937 compatible clk: qcom: ipq5424: Use icc-clk for enabling NoC related clocks dt-bindings: interconnect: Add Qualcomm IPQ5424 support clk: qcom: Add SM6115 LPASSCC dt-bindings: clock: Add Qualcomm SM6115 LPASS clock controller clk: qcom: gcc-sdm845: Do not use shared clk_ops for QUPs clk: qcom: gcc-sdm845: Add general purpose clock ops clk: qcom: clk-rcg2: split __clk_rcg2_configure function clk: qcom: clk-rcg2: document calc_rate function clk: qcom: gcc-x1e80100: Do not turn off usb_2 controller GDSC clk: qcom: ipq5424: add gcc_xo_clk dt-bindings: clock: qcom: gcc-ipq5424: add gcc_xo_clk macro dt-bindings: clock: qcom: gcc-ipq5424: remove apss_dbg clock macro clk: qcom: ipq5424: remove apss_dbg clock dt-bindings: clock: qcom,sdm845-camcc: add sdm670 compatible ...
2025-01-21Merge branches 'clk-cleanup', 'clk-renesas', 'clk-mediatek', 'clk-samsung' ↵Stephen Boyd
and 'clk-socfpga' into clk-next - Support for 5L35023 variant of Versa 3 clock generator * clk-cleanup: clk: analogbits: Fix incorrect calculation of vco rate delta clk: Use str_enable_disable-like helpers clk: clk-loongson2: Switch to use devm_clk_hw_register_fixed_rate_parent_data() clk: starfive: Make _clk_get become a common helper function clk: ep93xx: make const read-only arrays static clk: lmk04832: make read-only const arrays static clk: ti: use kcalloc() instead of kzalloc() dt-bindings: clock: st,stm32mp1-rcc: complete the reference path dt-bindings: clock: st,stm32mp1-rcc: fix reference paths dt-bindings: clock: ti: Convert composite.txt to json-schema dt-bindings: clock: ti: Convert gate.txt to json-schema clk: Drop obsolete devm_clk_bulk_get_all_enable() helper PCI: exynos: Switch to devm_clk_bulk_get_all_enabled() soc: mediatek: pwrap: Switch to devm_clk_bulk_get_all_enabled() clk: davinci: remove platform data struct clk: fix an OF node reference leak in of_clk_get_parent_name() clk: mmp: pxa1908-apbc: Fix NULL vs IS_ERR() check clk: mmp: pxa1908-apbcp: Fix a NULL vs IS_ERR() check clk: mmp: pxa1908-mpmu: Fix a NULL vs IS_ERR() check * clk-renesas: (24 commits) dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard clk: renesas: r9a09g057: Add clock and reset entries for GIC clk: renesas: r9a09g057: Add reset entry for SYS clk: renesas: r8a779g0: Add VSPX clocks clk: renesas: r8a779g0: Add FCPVX clocks clk: renesas: r9a09g047: Add I2C clocks/resets clk: renesas: r9a09g047: Add CA55 core clocks clk: renesas: rzv2h: Add support for RZ/G3E SoC clk: renesas: rzv2h: Add MSTOP support dt-bindings: clock: renesas: Document RZ/G3E SoC CPG dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants clk: versaclock3: Add support for the 5L35023 variant dt-bindings: clock: versaclock3: Document 5L35023 Versa3 clock generator clk: versaclock3: Prepare for the addition of 5L35023 device clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ADC IP clk: renesas: r8a779h0: Add display clocks clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets clk: renesas: rzv2h: Add selective Runtime PM support for clocks clk: renesas: r9a06g032: Use BIT macro consistently ... * clk-mediatek: clk: ralink: mtmips: remove duplicated 'xtal' clock for Ralink SoC RT3883 clk: mediatek: mt2701-img: add missing dummy clk clk: mediatek: mt2701-mm: add missing dummy clk clk: mediatek: mt2701-bdp: add missing dummy clk clk: mediatek: mt2701-aud: fix conversion to mtk_clk_simple_probe clk: mediatek: mt2701-vdec: fix conversion to mtk_clk_simple_probe * clk-samsung: clk: samsung: Introduce Exynos990 clock controller driver clk: samsung: clk-pll: Add support for pll_{0717x, 0718x, 0732x} dt-bindings: clock: samsung: Add Exynos990 SoC CMU bindings * clk-socfpga: clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate()
2025-01-15dt-bindings: clock: convert stm32 rcc bindings to json-schemaDario Binacchi
The patch converts st,stm32-rcc.txt to the JSON schema, but it does more than that. The old bindings, in fact, only covered the stm32f{4,7} platforms and not the stm32h7. Therefore, to avoid patch submission tests failing, it was necessary to add the corresponding compatible (i. e. st,stm32h743-rcc) and specify that, in this case, 3 are the clocks instead of the 2 required for the stm32f{4,7} platforms. Additionally, the old bindings made no mention of the st,syscfg property, which is used by both the stm32f{4,7} and the stm32h7 platforms. The patch also fixes the files referencing to the old st,stm32-rcc.txt. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250114182021.670435-2-dario.binacchi@amarulasolutions.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-13dt-bindings: clock: add ID for eMMC for EN7581Christian Marangi
Add ID for eMMC for EN7581. This is to control clock selection of eMMC between 200MHz and 150MHz. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250113231030.6735-4-ansuelsmth@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-13dt-bindings: clock: drop NUM_CLOCKS define for EN7581Christian Marangi
Drop NUM_CLOCKS define for EN7581 include. This is not a binding and should not be placed here. Value is derived internally in the user driver. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250113231030.6735-3-ansuelsmth@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-07dt-bindings: clock: Add Qualcomm SM6115 LPASS clock controllerKonrad Dybcio
SM6115 (and its derivatives or similar SoCs) has an LPASS clock controller block which provides audio-related resets. Add bindings for it. Cc: Konrad Dybcio <konradybcio@kernel.org> Cc: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> [alexey.klimov slightly changed the commit message] Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Link: https://lore.kernel.org/r/20241212002551.2902954-2-alexey.klimov@linaro.org [bjorn: Adjusted Konrad's address] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guardGeert Uytterhoeven
Add the missing "RENESAS" part to the include guard. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/34953d1e9f472e4f29533ed06cf092dd3c0d1178.1736238939.git.geert+renesas@glider.be
2025-01-06dt-bindings: clock: qcom: gcc-ipq5424: add gcc_xo_clk macroManikanta Mylavarapu
The GCC_XO_CLK is required for the functionality of the WiFi copy engine block. Therefore, add the GCC_XO_CLK macro. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241210064110.130466-2-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06dt-bindings: clock: qcom: gcc-ipq5424: remove apss_dbg clock macroManikanta Mylavarapu
The gcc_apss_dbg clk is access protected by trust zone, and accessing it results in a kernel crash. Therefore remove the gcc_apss_dbg_clk macro. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Link: https://lore.kernel.org/r/20241217113909.3522305-3-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06dt-bindings: clock: qcom,mmcc-msm8960: add LCDC-related clocksDmitry Baryshkov
APQ8064 / MSM8960 have separate LVDS / LCDC clock, driving the MDP4 LCD controller. Add corresponding indices to clock controller bindings. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241224-apq8064-fix-mmcc-v1-2-c95d2e2bf143@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06Merge branch '20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com' into ↵Bjorn Andersson
clk-for-6.14 Merge the IPQ CMN PLL clock binding through a topic branch to make it available to DeviceTree source branches as well.
2025-01-06dt-bindings: clock: qcom: Add CMN PLL clock controller for IPQ SoCLuo Jie
The CMN PLL controller provides clocks to networking hardware blocks and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi, and produces output clocks at fixed rates. These output rates are predetermined, and are unrelated to the input clock rate. The primary purpose of CMN PLL is to supply clocks to the networking hardware such as PPE (packet process engine), PCS and the externally connected switch or PHY device. The CMN PLL block also outputs fixed rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep clock supplied to GCC. Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06Merge branch '20250106-sm8750-dispcc-v2-1-6f42beda6317@linaro.org' into ↵Bjorn Andersson
clk-for-6.14 Merge SM8750 display clock controller bindings through topic branch, to make available to DeviceTree source branch as well.
2025-01-06dt-bindings: clock: qcom,sm8550-dispcc: Add SM8750 DISPCCKrzysztof Kozlowski
Add bindings for the Qualcomm SM8750 Display Clock Controller (DISPCC). Bindings are similar to existing SM8550 and SM8650 (same clock inputs), but the clock hierarchy is quite different and these are not compatible devices. The binding header was copied from downstream sources, so I retained original copyrights. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250106-sm8750-dispcc-v2-1-6f42beda6317@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06Merge branch '20241204-sm8750_master_clks-v3-0-1a8f31a53a86@quicinc.com' ↵Bjorn Andersson
into clk-for-6.14 Merge the SM8750 GCC and TCSR clock bindings through topic branch, to allow merging into DeviceTree source branch as well.
2025-01-06dt-bindings: clock: qcom: Document the SM8750 TCSR Clock ControllerTaniya Das
Add bindings documentation for the SM8750 Clock Controller. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-7-1a8f31a53a86@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06dt-bindings: clock: qcom: Add SM8750 GCCTaniya Das
Add device tree bindings for the global clock controller on Qualcomm SM8750 platform. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-5-1a8f31a53a86@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-04dt-bindings: clock: sunxi: Export PLL_VIDEO_2X and PLL_MIPIVasily Khoruzhick
Export PLL_VIDEO_2X and PLL_MIPI, these will be used to explicitly select TCON0 clock parent in dts Fixes: ca1170b69968 ("clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux") Reviewed-by: Dragan Simic <dsimic@manjaro.org> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Frank Oltmanns <frank@oltmanns.dev> # on PinePhone Tested-by: Stuart Gathman <stuart@gathman.org> # on OG Pinebook Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://patch.msgid.link/20250104074035.1611136-2-anarsoul@gmail.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2024-12-26dt-bindings: clock: imx93: Add SPDIF IPG clkShengjiu Wang
Add SPDIF IPG clk. The SPDIF IPG clock and root clock share same clock gate. Fixes: 1c4a4f7362fd ("arm64: dts: imx93: Add audio device nodes") Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241119015805.3840606-2-shengjiu.wang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-12-25Merge branch '20241221-topic-x1p4_clk-v1-2-dbaeccb74884@oss.qualcomm.com' ↵Bjorn Andersson
into clk-for-6.14 Merge the X1P42100 GPUCC binding through a topic branch to make available for the DeviceTree branch as well.
2024-12-25dt-bindings: clock: qcom,x1e80100-gpucc: Extend for X1P42100Konrad Dybcio
To make it easier for X1P4 and X1E to share a common device tree base, extend the existing latter's GPUCC bindings and reuse them on the former platform. While not in the same file, it only makes sense to introduce the new compatible in this commit as well. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241221-topic-x1p4_clk-v1-2-dbaeccb74884@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-17dt-bindings: clock: Add SAMA7D65 PMC compatible stringDharma Balasubiramani
Add the `microchip,sama7d65-pmc` compatible string to the existing binding, since the SAMA7D65 PMC shares the same properties and clock requirements as the SAMA7G5. Export MCK3 and MCK5 to be accessed and referenced in DT to assign to the clocks property for sama7d65 SoC. Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/5252a28531deaee67af1edd8e72d45ca57783464.1733505542.git.Ryan.Wanner@microchip.com [claudiu.beznea: use tabs instead of spaces in include/dt-bindings/clock/at91.h] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2024-12-14dt-bindings: clock: samsung: Add Exynos990 SoC CMU bindingsIgor Belwon
Add dt-schema documentation for the Exynos990 SoC CMU. This clock management unit has a topmost block (CMU_TOP) that generates top clocks for other blocks. Currently the only other block implemented is CMU_HSI0, which provides clocks for the USB part of the SoC. Also, device-tree binding definitions added for these blocks: - CMU_TOP - CMU_HSI0 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Link: https://lore.kernel.org/r/20241209-exynos990-cmu-v4-1-57f07080f9e4@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-12-13dt-bindings: clock: renesas: Document RZ/G3E SoC CPGBiju Das
Document the device tree bindings for the Renesas RZ/G3E SoC Clock Pulse Generator (CPG). Also define constants for the core clocks of the RZ/G3E SoC. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241203105005.103927-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-08dt-bindings: clk: at91: Add clock IDs for the slow clock controllerClaudiu Beznea
Add clock IDs for the slow clock controller. Previously, raw numbers were used (0 or 1) for clocks generated by the slow clock controller. This leads to confusion and wrong IDs were used on few device trees. To avoid this add macros. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240826173116.3628337-2-claudiu.beznea@tuxon.dev Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2024-12-01dt-bindings: clock: qcom: Add QCS615 GCC clocksTaniya Das
Add device tree bindings for global clock controller on QCS615 SoCs. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20241022-qcs615-clock-driver-v4-3-3d716ad0d987@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-22Merge tag 'clk-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The core framework gained a clk provider helper, a clk consumer helper, and some unit tests for the assigned clk rates feature in DeviceTree. On the vendor driver side, we gained a whole pile of SoC driver support detailed below. The majority in the diffstat is Qualcomm, but there's also quite a few Samsung and Mediatek clk driver additions in here as well. The top vendors is quite common, but the sheer amount of new drivers is uncommon, so I'm anticipating a larger number of fixes for clk drivers this cycle. Core: - devm_clk_bulk_get_all_enabled() to return number of clks acquired - devm_clk_hw_register_gate_parent_hw() helper to modernize drivers - KUnit tests for clk-assigned-rates{,-u64} New Drivers: - Marvell PXA1908 SoC clks - Mobileye EyeQ5, EyeQ6L and EyeQ6H clk driver - TWL6030 clk driver - Nuvoton Arbel BMC NPCM8XX SoC clks - MediaTek MT6735 SoC clks - MediaTek MT7620, MT7628 and MT7688 MMC clks - Add a driver for gated fixed rate clocks - Global clock controllers for Qualcomm QCS8300 and IPQ5424 SoCs - Camera, display and video clock controllers for Qualcomm SA8775P SoCs - Global, display, GPU, TCSR, and RPMh clock controllers for Qualcomm SAR2130P - Global, camera, display, GPU, and video clock controllers for Qualcomm SM8475 SoCs - RTC power domain and Battery Backup Function (VBATTB) clock support for the Renesas RZ/G3S SoC - Qualcomm IPQ9574 alpha PLLs - Support for i.MX91 CCM in the i.MX93 driver - Microchip LAN969X SoC clks - Cortex-A55 core clocks and Interrupt Control Unit (ICU) clock and reset on Renesas RZ/V2H(P) - Samsung ExynosAutov920 clk drivers for PERIC1, MISC, HSI0 and HSI1 - Samsung Exynos8895 clk drivers for FSYS0/1, PERIC0/1, PERIS and TOP Updates: - Convert more clk bindings to YAML - Various clk driver cleanups: NULL checks, add const, etc. - Remove END/NUM #defines that count number of clks in various binding headers - Continue moving reset drivers to drivers/reset via auxiliary bus" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (162 commits) clk: clk-loongson2: Fix potential buffer overflow in flexible-array member access clk: Fix invalid execution of clk_set_rate clk: clk-loongson2: Fix memory corruption bug in struct loongson2_clk_provider clk: lan966x: make it selectable for ARCH_LAN969X clk: eyeq: add EyeQ6H west fixed factor clocks clk: eyeq: add EyeQ6H central fixed factor clocks clk: eyeq: add EyeQ5 fixed factor clocks clk: eyeq: add fixed factor clocks infrastructure clk: eyeq: require clock index with phandle in all cases clk: fixed-factor: add clk_hw_register_fixed_factor_index() function dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles clk: clk-axi-clkgen: make sure to enable the AXI bus clock dt-bindings: clock: axi-clkgen: include AXI clk clk: mmp: Add Marvell PXA1908 MPMU driver clk: mmp: Add Marvell PXA1908 APMU driver clk: mmp: Add Marvell PXA1908 APBCP driver clk: mmp: Add Marvell PXA1908 APBC driver dt-bindings: clock: Add Marvell PXA1908 clock bindings clk: mmp: Switch to use struct u32_fract instead of custom one ...
2024-11-22Merge tag 'mfd-next-6.13' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd Pull MFD updates from Lee Jones: - Several drivers, including atmel-flexcom/rk8xx-core, palmas, and tps65010, have undergone minor code improvements to enhance consistency and fix race conditions. - The syscon driver now utilizes the regmap max_register_is_0 capability for consistent register map configuration across syscons of all sizes. - New device support has been added for QCS8300, qcs615, SA8255p, and samsung,s2dos05, expanding the range of compatible hardware. - The cros_ec driver now supports loading cros_ec_ucsi on supported ECs and avoids loading the charger with UCSI, streamlining functionality. - The bd96801 driver now utilizes the more modern maple tree register cache, improving performance. - The da9052-spi driver has undergone a fix to change the read-mask to write-mask, preventing potential issues. - Unused declarations in max77693 have been removed, and support for samsung,s2dos05 has been added, enhancing code clarity and device compatibility. - Error handling in cs42l43 has been fixed to avoid unbalanced regulator put and ensure proper synchronization during driver removal. - The wcd934x driver now uses MODULE_DEVICE_TABLE() instead of MODULE_ALIAS(), improving code consistency. - Documentation for qcom,tcsr, syscon, and atmel-smc has been updated and reorganized for better clarity and maintainability. - The intel_soc_pmic_bxtwc driver has undergone significant improvements, including the use of IRQ domains for various devices, fixing IRQ domain names duplication, and code refactoring for better consistency and maintainability. - The ipaq-micro driver has received a fix for a missing break statement in the default case, enhancing code robustness. - Support for the AXP323 PMIC has been added to the axp20x driver, along with ensuring a clear relationship between IDs and model names, and allowing multiple regulators, broadening hardware compatibility. - The cs42l43 driver now disables IRQs during suspend for improved power management. - The adp5585 driver has reduced its dependencies by dropping the obsolete dependency on COMPILE_TEST. - Initial support for the MT6328 PMIC has been added to the mt6397 driver, expanding the range of supported hardware. - The rtc-bd70528 driver has been simplified by dropping the IC name from IRQ, improving code readability. - Documentation for qcom,spmi-pmic, ti,twl, and zii,rave-sp has been updated to enhance clarity and incorporate new features. - The rt5033 driver has received a fix for a missing regmap_del_irq_chip() in the error handling path. - New device support has been added for MSM8917, and the intel_soc_pmic_crc driver now supports non-ACPI instantiated i2c_client. - The 88pm886 driver has added support for the RTC cell, and the tqmx86 driver has improved its GPIO IRQ setup and added I2C IRQ support, increasing functionality. - The sprd,sc2731 DT schema has been updated and converted to YAML format for better readability and maintainability. * tag 'mfd-next-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (62 commits) dt-bindings: mfd: bd71828: Use charger resistor in mOhm instead of MOhm dt-bindings: mfd: sprd,sc2731: Convert to YAML mfd: tqmx86: Add I2C IRQ support mfd: tqmx86: Make IRQ setup errors non-fatal mfd: tqmx86: Refactor GPIO IRQ setup mfd: tqmx86: Improve gpio_irq module parameter description mfd: tqmx86: Add board definitions for TQMx120UC, TQMx130UC and TQMxE41S mfd: 88pm886: Add the RTC cell dt-bindings: mfd: Add Realtek RTL9300 switch peripherals mfd: intel_soc_pmic_crc: Add support for non ACPI instantiated i2c_client mfd: intel_soc_pmic_*: Consistently use filename as driver name dt-bindings: mfd: qcom,tcsr: Add compatible for MSM8917 mfd: rt5033: Fix missing regmap_del_irq_chip() mfd: cgbc-core: Fix error handling paths in cgbc_init_device() dt-bindings: mfd: aspeed: Support for AST2700 mfd: Switch back to struct platform_driver::remove() dt-bindings: mfd: qcom,spmi-pmic: Document PMICs added in SM8750 mfd: rtc: bd7xxxx Drop IC name from IRQ mfd: mt6397: Add initial support for MT6328 mfd: adp5585: Drop obsolete dependency on COMPILE_TEST ...
2024-11-18Merge branches 'clk-marvell', 'clk-adi', 'clk-qcom' and 'clk-devm' into clk-nextStephen Boyd
- Add devm_clk_bulk_get_all_enabled() to return number of clks acquired - Marvell PXA1908 SoC clks * clk-marvell: clk: mmp: Add Marvell PXA1908 MPMU driver clk: mmp: Add Marvell PXA1908 APMU driver clk: mmp: Add Marvell PXA1908 APBCP driver clk: mmp: Add Marvell PXA1908 APBC driver dt-bindings: clock: Add Marvell PXA1908 clock bindings clk: mmp: Switch to use struct u32_fract instead of custom one * clk-adi: clk: clk-axi-clkgen: make sure to enable the AXI bus clock dt-bindings: clock: axi-clkgen: include AXI clk * clk-qcom: (43 commits) clk: qcom: remove unused data from gcc-ipq5424.c clk: qcom: Add support for Global Clock Controller on QCS8300 dt-bindings: clock: qcom: Add GCC clocks for QCS8300 clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574 dt-bindings: clock: Add Qualcomm IPQ5424 GCC binding clk: qcom: add SAR2130P GPU Clock Controller support clk: qcom: dispcc-sm8550: enable support for SAR2130P clk: qcom: tcsrcc-sm8550: add SAR2130P support clk: qcom: add support for GCC on SAR2130P clk: qcom: rpmh: add support for SAR2130P clk: qcom: rcg2: add clk_rcg2_shared_floor_ops dt-bindings: clk: qcom,sm8450-gpucc: add SAR2130P compatibles dt-bindings: clock: qcom,sm8550-dispcc: Add SAR2130P compatible dt-bindings: clock: qcom,sm8550-tcsr: Add SAR2130P compatible dt-bindings: clock: qcom: document SAR2130P Global Clock Controller dt-bindings: clock: qcom,rpmhcc: Add SAR2130P compatible clk: qcom: Make GCC_6125 depend on QCOM_GDSC dt-bindings: clock: qcom: gcc-ipq9574: remove q6 bring up clock macros dt-bindings: clock: qcom: gcc-ipq5332: remove q6 bring up clock macros ... * clk-devm: clk: Provide devm_clk_bulk_get_all_enabled() helper
2024-11-18Merge branches 'clk-samsung', 'clk-microchip', 'clk-imx', 'clk-amlogic' and ↵Stephen Boyd
'clk-allwinner' into clk-next * clk-samsung: clk: samsung: Introduce Exynos8895 clock driver clk: samsung: clk-pll: Add support for pll_{1051x,1052x} dt-bindings: clock: samsung: Add Exynos8895 SoC clk: samsung: gs101: make all ufs related clocks critical clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions clk: samsung: Fix out-of-bound access of of_match_node() dt-bindings: clock: samsung: remove define with number of clocks for FSD clk: samsung: fsd: do not define number of clocks in bindings clk: samsung: Fix errors reported by checkpatch clk: samsung: Fix block comment style warnings reported by checkpatch * clk-microchip: clk: lan966x: add support for lan969x SoC clock driver clk: lan966x: prepare driver for lan969x support clk: lan966x: make clk_names const char * const dt-bindings: clock: add support for lan969x * clk-imx: clk: imx: imx8-acm: Fix return value check in clk_imx_acm_attach_pm_domains() clk: imx: lpcg-scu: Skip HDMI LPCG clock save/restore clk: imx: clk-scu: fix clk enable state save and restore clk: imx: fracn-gppll: fix pll power up clk: imx: fracn-gppll: correct PLL initialization flow clk: imx: lpcg-scu: SW workaround for errata (e10858) clk: imx: add i.MX91 clk dt-bindings: clock: Add i.MX91 clock support dt-bindings: clock: imx93: Drop IMX93_CLK_END macro definition clk: imx93: Move IMX93_CLK_END macro to clk driver clk: imx95-blk-ctl: Add one clock gate for HSIO block dt-bindings: clock: nxp,imx95-blk-ctl: Add compatible string for i.MX95 HSIO BLK CTRL * clk-amlogic: clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUX clk: amlogic: axg-audio: use the auxiliary reset driver reset: amlogic: Fix small whitespace issue reset: amlogic: add auxiliary reset driver support reset: amlogic: split the device core and platform probe reset: amlogic: move drivers to a dedicated directory reset: amlogic: add reset status support reset: amlogic: use reset number instead of register count reset: amlogic: add driver parameters reset: amlogic: make parameters unsigned reset: amlogic: use generic data matching function reset: amlogic: convert driver to regmap dt-bindings: clock: convert amlogic,meson8b-clkc.txt to dtschema clk: meson: meson8b: remove spinlock clk: meson: mpll: Delete a useless spinlock from the MPLL clk: meson: s4: pll: fix frac maximum value for hifi_pll clk: meson: c3: pll: fix frac maximum value for hifi_pll clk: meson: Support PLL with fixed fractional denominators clk: meson: s4: pll: hifi_pll support fractional multiplier * clk-allwinner: clk: sunxi-ng: Use of_property_present() for non-boolean properties clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset clk: sunxi-ng: Constify struct ccu_reset_map clk: sunxi-ng: h616: Add sigma-delta modulation settings for audio PLL
2024-11-18Merge branches 'clk-mobileye', 'clk-twl', 'clk-nuvoton', 'clk-renesas' and ↵Stephen Boyd
'clk-bindings' into clk-next - Mobileye EyeQ5, EyeQ6L and EyeQ6H clk driver - TWL6030 clk driver - Nuvoton Arbel BMC NPCM8XX SoC clks - Convert more clk bindings to YAML * clk-mobileye: clk: eyeq: add EyeQ6H west fixed factor clocks clk: eyeq: add EyeQ6H central fixed factor clocks clk: eyeq: add EyeQ5 fixed factor clocks clk: eyeq: add fixed factor clocks infrastructure clk: eyeq: require clock index with phandle in all cases clk: fixed-factor: add clk_hw_register_fixed_factor_index() function dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles clk: eyeq: add driver clk: divider: Introduce CLK_DIVIDER_EVEN_INTEGERS flag dt-bindings: clock: add Mobileye EyeQ6L/EyeQ6H clock indexes Revert "dt-bindings: clock: mobileye,eyeq5-clk: add bindings" * clk-twl: clk: twl: add TWL6030 support clk: twl: remove is_prepared * clk-nuvoton: clk: npcm8xx: add clock controller reset: npcm: register npcm8xx clock auxiliary bus device dt-bindings: reset: npcm: add clock properties * clk-renesas: clk: renesas: vbattb: Add VBATTB clock driver clk: Add devm_clk_hw_register_gate_parent_hw() clk: renesas: rzg2l: Fix FOUTPOSTDIV clk dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB clk: renesas: r9a08g045: Add power domain for RTC clk: renesas: r9a08g045: Mark the watchdog and always-on PM domains as IRQ safe clk: renesas: rzg2l-cpg: Use GENPD_FLAG_* flags instead of local ones clk: renesas: rzg2l-cpg: Move PM domain power on in rzg2l_cpg_pd_setup() dt-bindings: clock: r9a08g045-cpg: Add power domain ID for RTC clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks clk: renesas: r9a09g057: Add clock and reset entries for ICU clk: renesas: r9a09g057: Add CA55 core clocks clk: renesas: Remove duplicate and trailing empty lines * clk-bindings: dt-bindings: clock: actions,owl-cmu: convert to YAML dt-bindings: clock: ti: Convert mux.txt to json-schema dt-bindings: clock: ti: Convert divider.txt to json-schema dt-bindings: clock: ti: Convert interface.txt to json-schema dt-bindings: clock: convert rockchip,rk3328-cru.txt to YAML
2024-11-14dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocksThéo Lebrun
Add #defines for Mobileye clock controller: - EyeQ5 core 0 thru 3 clocks. Internally: EQ5C_PLL_CPU: already exposed └── EQ5C_CPU_OCC: unexposed, no reason to do so ├── EQ5C_CPU_CORE0: new! ├── EQ5C_CPU_CORE1: new! ├── EQ5C_CPU_CORE2: new! └── EQ5C_CPU_CORE3: new! - EyeQ5 peripheral clocks. Internally: EQ5C_PLL_PER: already exposed ├── EQ5C_PER_OCC: new! │ ├── EQ5C_PER_SPI: new! │ ├── EQ5C_PER_I2C: new! │ ├── EQ5C_PER_GPIO: new! │ └── EQ5C_PER_UART: new! ├── EQ5C_PER_EMMC: new! └── EQ5C_PER_OCC_PCI: new! - EyeQ6H central OLB. Internally: EQ6HC_CENTRAL_PLL_CPU: new! └── EQ6HC_CENTRAL_CPU_OCC: new! - EyeQ6H west OLB. Internally: EQ6HC_WEST_PLL_PER: new! └── EQ6HC_WEST_PER_OCC: new! └── EQ6HC_WEST_PER_UART: new! Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://lore.kernel.org/r/20241106-mbly-clk-v2-2-84cfefb3f485@bootlin.com Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-11-14dt-bindings: clock: Add Marvell PXA1908 clock bindingsDuje Mihanović
Add dt bindings and documentation for the Marvell PXA1908 clock controller. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr> Link: https://lore.kernel.org/r/20241104-pxa1908-lkml-v13-4-e050609b8d6c@skole.hr Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-11-14dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset ↵Yassine Oudjana
controllers Add device tree bindings for syscon clock and reset controllers (IMGSYS, MFGCFG, VDECSYS and VENCSYS). Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20241106111402.200940-2-y.oudjana@protonmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-11-12Merge tag 'qcom-arm64-for-6.13' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt Qualcomm Arm64 DeviceTree changes for v6.13 Introduce descriptions of the 8cx Gen3-based Microsoft Surface Pro 9 5G, X Elite based Dell XPS 13 9345, the QCS9100 platform and the "Ride" development boards thereon, and the SM7325 platform and the Nothing Phone 1. MSM8998 gains support for HDMI. The Lenovo Miix 630 gains support for volume keys, audio and sensor DSPs, touchscreen, and its specific WiFi calibration variant. On QCM6490, Fairphone FP5 gains a thermistor adjacent to UFS/RAM, while the IDP gains UFS and WiFi support. For QCS6490 changes to Rb3Gen2 enables WiFi, Venus, PCIe, SD-card, and volume keys. Adreno speedbins are adjusted and PMU nodes' compatibles for the two clusters are corrected. The DB845C/RB3 and QRB5165 RB5 vision mezzanines are converted to DeviceTree overlays, and both gains CMA heap for libcamera to use. SA8775P gains GPI DMA support, support for controlling download mode (bootloader-assisted ramdump support), additional UARTs, and qcrypto support. The "Ride" development board gains WiFi and Bluetooth support. On SC8280XP (8cx Gen3) another UART is described, used in the Microsoft Surface 9 5G. The WiFi/BT combo chip's power management unit is described on the CRD and Lenovo ThinkPad X13s. On SDM630/660 the GPU SMMU and clock controller is added, as is the A2Noc and LPASS SMMU, and the DSP-based WiFi device. GPU, modem DSP and WiFi is then enabled on the Inforce 6560 development board. On SM8450 Hardware Development Kit, the WCN6855 is modelled to enable WiFi and Bluetooth. A "global" interrupt is defined on SM8450 PCIe RC controller, to enable hotplug. On X Elite, USB Type-C controllers are marked as usb-role-switch capable, the GICv3 ITS is enabled for PCIe. TCSR region is described and wired up to allow setting and cleaning the download mode (bootloader-assisted ramdump) flag, and residency numbers for C4/C5 are updated. USB role switch is enabled on Lenovo ThinkPad T14s and the ASUS Vivobook S15. The T14s also gains support for a second source trackpad. The Microsoft Surface Laptop gains LID switch and the USB Type-A connector attached to the multiport controller is enabled. The CRD has its HID device power supplies described. Application SMMU is flagged as DMA coherent across QDU1000, SC7180, SC8180X, SC8280XP, SDM670, SDM845, SM8150, SM8350, SM8450, and X1E80100. In addition to this, the effort to improve style and binding compliance continued. * tag 'qcom-arm64-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (120 commits) arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Add cma heap for libcamera softisp support arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Add cma heap for libcamera softisp support arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Drop redundant clock-lanes from camera@1a arm64: dts: qcom: sc8280xp-x13s: Drop redundant clock-lanes from camera@10 arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Convert mezzanine riser to dtso arm64: dts: qcom: qrb5165-rb5-vision-mezzanine: Convert mezzanine riser to dtbo arm64: dts: qcom: sm8450-hdk: model the PMU of the on-board wcn6855 arm64: dts: qcom: sc8280xp-x13s: model the PMU of the on-board wcn6855 arm64: dts: qcom: sc8280xp-crd: enable bluetooth arm64: dts: qcom: sc8280xp-crd: model the PMU of the on-board wcn6855 arm64: dts: qcom: qcs9100: Add support for the QCS9100 Ride and Ride Rev3 boards dt-bindings: arm: qcom: Document qcs9100-ride and qcs9100-ride Rev3 arm64: dts: qcom: x1e80100: Update C4/C5 residency/exit numbers arm64: dts: qcom: x1e80100-crd: describe HID supplies arm64: dts: qcom: msm8998-lenovo-miix-630: add WiFi calibration variant arm64: dts: qcom: msm8998-clamshell: enable resin/VolDown arm64: dts: qcom: msm8998-lenovo-miix-630: enable VolumeUp button arm64: dts: qcom: msm8998-lenovo-miix-630: enable aDSP and SLPI arm64: dts: qcom: msm8998-lenovo-miix-630: enable touchscreen arm64: dts: qcom: qcs6490-rb3gen2: Add PCIe nodes ... Link: https://lore.kernel.org/r/20241105164901.7787-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-11-12Merge tag 'renesas-dts-for-v6.13-tag2' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt Renesas DTS updates for v6.13 (take two) - Add a CPU Operating Performance Points table for the RZ/V2H SoC, - Add Battery Backup Function (VBATTB) and RTC support for the RZ/G3S SoC and the RZ/G3S SMARC SoM, - Add DMAC support for MMC on the RZ/A1H SoC and the Genmai development board, - Miscellaneous fixes and improvements. * tag 'renesas-dts-for-v6.13-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: arm64: dts: renesas: rzg3s-smarc-som: Enable RTC arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB arm64: dts: renesas: r9a08g045: Add RTC node arm64: dts: renesas: r9a08g045: Add VBATTB node arm64: dts: renesas: white-hawk-cpu-common: Add pin control for DSI-eDP IRQ ARM: dts: renesas: r7s72100: Add DMA support to MMCIF ARM: dts: renesas: r7s72100: Add DMAC node arm64: dts: renesas: hihope: Drop #sound-dai-cells dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB dt-bindings: clock: r9a08g045-cpg: Add power domain ID for RTC arm64: dts: renesas: r9a09g057: Add OPP table Link: https://lore.kernel.org/r/cover.1730726155.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-11-05Merge branch '20240822-qcs8300-gcc-v2-1-b310dfa70ad8@quicinc.com' into ↵Bjorn Andersson
clk-for-6.13 Merge QCS8300 global clock controller binding through topic branch to make it available to both clock and DeviceTree branches.
2024-11-05dt-bindings: clock: qcom: Add GCC clocks for QCS8300Imran Shaik
Add support for qcom global clock controller bindings for QCS8300 platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Link: https://lore.kernel.org/r/20240822-qcs8300-gcc-v2-1-b310dfa70ad8@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05Merge branch '20241028060506.246606-3-quic_srichara@quicinc.com' into ↵Bjorn Andersson
clk-for-6.13 Merge IPQ5424 global clock controller binding through topic branch to make the constants available for both clock and DeviceTree branches.
2024-11-05dt-bindings: clock: Add Qualcomm IPQ5424 GCC bindingSricharan Ramabadhran
Add binding for the Qualcomm IPQ5424 Global Clock Controller Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241028060506.246606-3-quic_srichara@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05Merge branch '20241027-sar2130p-clocks-v5-0-ecad2a1432ba@linaro.org' into ↵Bjorn Andersson
clk-for-6.13 Merge SAR2130P clock bindings through topic branch, to allow them being used in both clock and DeviceTree branches.
2024-11-05dt-bindings: clk: qcom,sm8450-gpucc: add SAR2130P compatiblesKonrad Dybcio
Expand qcom,sm8450-gpucc bindings to include SAR2130P. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-5-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05dt-bindings: clock: qcom: document SAR2130P Global Clock ControllerDmitry Baryshkov
Add bindings for the Global Clock Controller (GCC) present on the Qualcomm SAR2130P platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-2-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-03dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTBClaudiu Beznea
The VBATTB IP of the Renesas RZ/G3S SoC controls the clock for RTC, the tamper detector and a small general usage memory of 128B. The VBATTB controller controls the clock for the RTC on the Renesas RZ/G3S. The HW block diagram for the clock logic is as follows: +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ ,/ One could connect as input to this HW block either a crystal or an external clock device. This is board specific. After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: input-xtal xbyp xc mux vbattclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. This allows select the input of the mux based on the type of the connected input clock: - if the 32768 crystal is connected as input for the VBATTB, the input of the mux should be xc - if an external clock device is connected as input for the VBATTB the input of the mux should be xbyp Add bindings for the VBATTB controller. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20241101095720.2247815-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-11-01dt-bindings: mfd: aspeed: Support for AST2700Ryan Chen
Add reset, clk dt bindings headers, and update compatible support for AST2700 clk, silicon-id in yaml. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20241023090153.1395220-2-ryan_chen@aspeedtech.com Signed-off-by: Lee Jones <lee@kernel.org>
2024-10-26Merge branch 'for-v6.13/clk-dt-bindings' into next/clkKrzysztof Kozlowski
2024-10-26dt-bindings: clock: samsung: Add Exynos8895 SoCIvaylo Ivanov
Provide dt-schema documentation for Samsung Exynos8895 SoC clock controller CMU blocks: - CMU_FSYS0/1 - CMU_PERIC0/1 - CMU_PERIS - CMU_TOP Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20241023090136.537395-2-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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