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2023-01-30Merge tag 'amlogic-drivers-for-v6.3' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/drivers Amlogic Drivers changes for v6.3: - Merge of immutable bindings branch with Reset & power domain binding - Addition of NNA power domain for A311D SoC - meson_sm.txt conversionto dt-schema - mark amlogic,meson-gx-pwrc bindings as deprecated - fix of meson_sm driver by using NULL instead of 0 * tag 'amlogic-drivers-for-v6.3' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux: firmware: meson_sm: stop using 0 as NULL pointer dt-bindings: power: amlogic,meson-gx-pwrc: mark bindings as deprecated dt-bindings: firmware: convert meson_sm.txt to dt-schema soc: amlogic: meson-pwrc: Add NNA power domain for A311D dt-bindings: power: Add G12A NNA power domain dt-bindings: reset: meson-g12a: Add missing NNA reset Link: https://lore.kernel.org/r/ec9552d8-96df-a677-ab94-9723f5c30f1c@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-01-30Merge tag 'sunxi-drivers-for-6.3-1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/drivers - introduce Allwinner PPU driver - limit iteration in sram debugfs * tag 'sunxi-drivers-for-6.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: soc: sunxi: Add Allwinner D1 PPU driver dt-bindings: power: Add Allwinner D1 PPU soc: sunxi: sram: Only iterate over SRAM children Link: https://lore.kernel.org/r/Y9RXXATRNqEv0GJT@jernej-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-01-30Merge tag 'riscv-soc-for-v6.3-mw0' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers RISC-V SoC drivers for v6.3-mw0 It's all StarFive stuff this time: Their new JH7110 SoC uses a SiFive core complex, and therefore a SiFive cache controller too. That needed a compatible added to both the binding and driver. The JH7110 also has power domains, which are supported by a new driver and a corresponding dt-binding. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-soc-for-v6.3-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: soc: starfive: Add StarFive JH71XX pmu driver dt-bindings: power: Add starfive,jh7110-pmu soc: sifive: ccache: Add StarFive JH7110 support dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC Link: https://lore.kernel.org/r/Y9LNIm9pkr+Owv/e@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-01-29dt-bindings: imx8ulp: clock: no spaces before tabsMarcel Ziswiler
This fixes the following warnings: include/dt-bindings/clock/imx8ulp-clock.h:204: warning: please, no space before tabs include/dt-bindings/clock/imx8ulp-clock.h:215: warning: please, no space before tabs Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230119085421.102804-3-marcel@ziswiler.com
2023-01-29clk: imx6sll: add proper spdx license identifierMarcel Ziswiler
This fixes the following error: include/dt-bindings/clock/imx6sll-clock.h:1: warning: Improper SPDX comment style for 'include/dt-bindings/clock/imx6sll-clock.h', please use '/*' instead include/dt-bindings/clock/imx6sll-clock.h:1: warning: Missing or malformed SPDX-License-Identifier tag in line 1 Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230119085421.102804-2-marcel@ziswiler.com
2023-01-27dt-bindings: power: Add Allwinner D1 PPUSamuel Holland
The Allwinner D1 family of SoCs contain a PPU power domain controller separate from the PRCM. It can power down the video engine and DSP, and it contains special logic for hardware-assisted CPU idle. Other recent Allwinner SoCs (e.g. TV303) have a PPU with a different set of domains. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20230126063419.15971-2-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-01-25dt-bindings: reset: mt8195: add vdosys1 reset control bitNancy.Lin
Add vdosys1 reset control bit for MT8195 platform. Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20230113104434.28023-3-nancy.lin@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2023-01-20dt-bindings: power: Add starfive,jh7110-pmuWalker Chen
Add bindings for the Power Management Unit on the StarFive JH7110 SoC. Signed-off-by: Walker Chen <walker.chen@starfivetech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-01-19dt-bindings: interconnect: qcom: document the interconnects for sa8775pBartosz Golaszewski
Add a DT binding document for the RPMh interconnects on Qualcomm sa8775p platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230118140825.242544-2-brgl@bgdev.pl Signed-off-by: Georgi Djakov <djakov@kernel.org>
2023-01-19dt-bindings: interconnect: add sdm670 interconnectsRichard Acayan
There are controllable interconnects on Snapdragon 670. Add the compatible strings to the documentation and interconnect ID definitions. The device tree header was generated by linux-interconnect-driver-generator and the copyright year was changed. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230111005155.50452-2-mailingradian@gmail.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2023-01-19dt-bindings: power: Add MT8188 power domainsGarmin.Chang
Add power domains dt-bindings for MT8188. Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221223080553.9397-2-Garmin.Chang@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2023-01-18Revert "dt-bindings: power: rpmpd: Add SM4250 support"Konrad Dybcio
SM4250 and SM6115 use a shared device tree and the RPMPDs are identical. There's no need for a separate entry, so remove it. This reverts commit 45ac44ed10e58cf9b510e6552317ed7d2602346f. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230113152232.2624545-2-konrad.dybcio@linaro.org
2023-01-18Merge branch '20230112204446.30236-2-quic_molvera@quicinc.com' into HEADBjorn Andersson
2023-01-18dt-bindings: clock: Add QDU1000 and QRU1000 GCC clocksMelody Olvera
Add device tree bindings for global clock controller on QDU1000 and QRU1000 SoCs. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230112204446.30236-2-quic_molvera@quicinc.com
2023-01-18dt-bindings: clock: qcom,gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRCDmitry Baryshkov
Add GCC_MMSS_GPLL0_CLK_SRC, the branch clock gating gpll0 clock for the multimedia subsystem. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230111060402.1168726-3-dmitry.baryshkov@linaro.org
2023-01-18Merge branch ↵Bjorn Andersson
'20230103-topic-sm8550-upstream-dispcc-v3-1-8a03d348c572@linaro.org' into HEAD Merge the DT binding in order to get the dispcc include file.
2023-01-18dt-bindings: clock: document SM8550 DISPCC clock controllerNeil Armstrong
Document device tree bindings for display clock controller for Qualcomm SM8550 SoC. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-dispcc-v3-1-8a03d348c572@linaro.org
2023-01-18dt-bindings: arm: qcom,ids: Add a bunch of older SoCsStephan Gerhold
Sync the SoC IDs in qcom,ids.h with relevant entries from Qualcomm's LK bootloader [1] that is used for almost all older Qualcomm SoCs. Several of these are already supported, e.g.: - MSM8960 -> APQ8060, MSM8260, ... - MSM8976 -> APQ8076 - MSM8956 -> APQ8056 Others are currently being worked on, e.g.: - MSM8909(W) -> APQ8009(W), MSM8905, MSM8209, ... - MSM8939 -> MSM8239, ... And even all remaining ones added are close enough to what is already supported so that future support is realistic (if someone steps up to do the work). Add all of them at once to avoid having to add them one by one in the future. This will also benefit other projects making use of the same dt-bindings, e.g. bootloaders where adding support for all these SoCs is a bit easier than on Linux. [1]: https://git.codelinaro.org/clo/la/kernel/lk/-/blob/9d563e4a1d38c5a662bf94215ffc828db57c9e19/platform/msm_shared/smem.h#L286 Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104115348.25046-4-stephan@gerhold.net
2023-01-18dt-bindings: arm: qcom,ids: Add QRD board IDStephan Gerhold
QRD (Qualcomm Reference Design) = 0xb = 11 is used on many devices that were originally derived from some reference design provided by Qualcomm. Examples of existing devices in Linux would be: - msm8916-longcheer-l8150/l8910, msm8916-wingtech-wt88047 - msm8953-xiaomi-daisy/tissot/vince - msm8998-fxtec-pro1 - sm4250-oneplus-billie2 Add it to qcom,ids.h so the qcom,board-id properties can be rewritten more clearly using the macros in a future patch set, i.e. qcom,board-id = <QCOM_BOARD_ID(QRD, 1, 0) 0> instead of qcom,board-id = <0x1000b 0x00> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104115348.25046-3-stephan@gerhold.net
2023-01-18dt-bindings: clock: Add Qualcomm SA8775P GCCBartosz Golaszewski
Add DT bindings for the GCC clock on SA8775P platforms. Add relevant DT include definitions as well. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230117180429.305266-2-brgl@bgdev.pl
2023-01-18dt-bindings: interconnect: qcom: drop IPA_CORE related definesDmitry Baryshkov
These interconnects are modeled as clks, not interconnects, therefore remove corresponding defines from the binding as they're unused. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230109002935.244320-10-dmitry.baryshkov@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
2023-01-17dt-binding: gpio: publish binding IDs under dual licenseEtienne Carriere
Changes gpio.h DT binding header file to be published under GPLv2 or BSD-2-Clause license terms. This change allows this GPIO generic bindings header file to be used in software components as bootloaders and OSes that are not published under GPLv2 terms. All contributors to gpio.h file in copy. Cc: Stephen Warren <swarren@nvidia.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Laxman Dewangan <ldewangan@nvidia.com> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Cc: Nuno Sá <nuno.sa@analog.com> Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Acked-by: Nuno Sá <nuno.sa@analog.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220905145555.674800-1-etienne.carriere@linaro.org Signed-off-by: Rob Herring <robh@kernel.org>
2023-01-16ARM: s3c: remove all s3c24xx supportArnd Bergmann
The platform was deprecated in commit 6a5e69c7ddea ("ARM: s3c: mark as deprecated and schedule removal") and can be removed. This includes all files that are exclusively for s3c24xx and not shared with s3c64xx, as well as the glue logic in Kconfig and the maintainer file entries. Cc: Arnaud Patard <arnaud.patard@rtp-net.org> Cc: Ben Dooks <ben-linux@fluff.org> Cc: Christer Weinigel <christer@weinigel.se> Cc: Guillaume GOURAT <guillaume.gourat@nexvision.tv> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Simtec Linux Team <linux@simtec.co.uk> Cc: openmoko-kernel@lists.openmoko.org Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-01-15dt-bindings: pinctrl: k3: Introduce pinmux definitions for J784s4Apurva Nandan
Add pinctrl macros for J784s4 SoC. These macro definitions are similar to that of J721s2, but adding new definitions to avoid any naming confusions in the soc dts files. checkpatch insists the following error exists: ERROR: Macros with complex values should be enclosed in parentheses However, we do not need parentheses enclosing the values for this macro as we do intend it to generate two separate values as has been done for other similar platforms. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Link: https://lore.kernel.org/r/20230112142725.77785-3-a-nandan@ti.com
2023-01-10Merge branch '20230109130523.298971-3-konrad.dybcio@linaro.org' into ↵Bjorn Andersson
drivers-for-6.3
2023-01-10dt-bindings: firmware: qcom: scm: Separate VMIDs from header to bindingsKonrad Dybcio
The SCM VMIDs represent predefined mappings that come from the irreplaceable and non-omittable firmware that comes with every Qualcomm SoC (unless you steal engineering samples from the factory) and help clarify otherwise totally magic numbers which we are required to pass to the secure world for some parts of the SoC to work at all (with modem being the prime example). On top of that, with changes to the rmtfs binding, secure VMIDs will become useful to have in device trees for readability. Separate them out and add to include/dt-bindings. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230109130523.298971-3-konrad.dybcio@linaro.org
2023-01-10dt-bindings: clock: qcom: gcc-sm8450: drop test clockDmitry Baryshkov
The test clock apparently it's not used by anyone upstream. Remove it. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221228185237.3111988-8-dmitry.baryshkov@linaro.org
2023-01-10dt-bindings: clock: qcom: gcc-sm8350: drop test clockDmitry Baryshkov
The test clock apparently it's not used by anyone upstream. Remove it. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221228185237.3111988-7-dmitry.baryshkov@linaro.org
2023-01-10Merge branch '20230104093450.3150578-2-abel.vesa@linaro.org' into arm64-for-6.3Bjorn Andersson
Merge the TCSR clock binding, to gain the Devicetree include file.
2023-01-10dt-bindings: clock: Add SM8550 TCSR CC clocksAbel Vesa
Add bindings documentation for clock TCSR driver on SM8550. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104093450.3150578-2-abel.vesa@linaro.org
2023-01-10Merge branch 'icc-sm8550-immutable' of ↵Bjorn Andersson
https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into arm64-for-6.3 Merge the immutable SM8550 interconnect branch, to gain the include file from the binding.
2023-01-10dt-bindings: clock: document SM8550 DISPCC clock controllerNeil Armstrong
Document device tree bindings for display clock controller for Qualcomm SM8550 SoC. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-dispcc-v3-1-8a03d348c572@linaro.org
2023-01-10dt-bindings: power: qcom,rpmpd: document sa8775pBartosz Golaszewski
Add a compatible for sa8775p platforms and relevant defines to the include file. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230109174511.1740856-14-brgl@bgdev.pl
2023-01-08dt-bindings: clock: Add D1 CAN bus gates and resetsSamuel Holland
The D1 CCU contains gates and resets for two CAN buses. While the CAN bus controllers are only documented for the T113 SoC, the CCU is the same across all SoC variants. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Samuel Holland <samuel@sholland.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221231231429.18357-6-samuel@sholland.org Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
2023-01-06dt-bindings: clock: Add SM8550 TCSR CC clocksAbel Vesa
Add bindings documentation for clock TCSR driver on SM8550. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230104093450.3150578-2-abel.vesa@linaro.org
2023-01-05Merge branch 'icc-qdu1000' into icc-nextGeorgi Djakov
Add dt bindings and driver support for the Qualcomm QDU1000 and QRU1000 SoCs. The Qualcomm Technologies, Inc. Distributed Unit 1000 and Radio Unit 1000 are new SoCs meant for enabling Open RAN solutions. See more at https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/qualcomm_5g_ran_platforms_product_brief.pdf Link: https://lore.kernel.org/r/20221216230914.21771-1-quic_molvera@quicinc.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2023-01-05dt-bindings: interconnect: Add QDU1000/QRU1000 devicesMelody Olvera
Add separate schema for QDU1000 and QRU1000 interconnect devices to document the different NoCs on these platforms. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20221216230914.21771-2-quic_molvera@quicinc.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
2023-01-02dt-bindings: power: Add G12A NNA power domainTomeu Vizoso
Add define for the NNA power domain for the NPU in the G12A. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20221202115223.39051-3-tomeu.vizoso@collabora.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2023-01-02dt-bindings: reset: meson-g12a: Add missing NNA resetTomeu Vizoso
Doesn't appear in the TRM I have, but it is used by the downstream galcore driver. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20221202115223.39051-2-tomeu.vizoso@collabora.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
2022-12-29dt-bindings: interconnect: Add Qualcomm SM8550Abel Vesa
The Qualcomm SM8550 SoC has several bus fabrics that could be controlled and tuned dynamically according to the bandwidth demand. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20221202232054.2666830-2-abel.vesa@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
2022-12-28dt-bindings: clock: add QCOM SM6350 camera clock bindingsKonrad Dybcio
Add device tree bindings for camera clock controller for Qualcomm Technology Inc's SM6350 SoC. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221213152617.296426-1-konrad.dybcio@linaro.org
2022-12-28dt-bindings: clocks: qcom: rpmcc: add LN_BB_CLK_PIN clocksDmitry Baryshkov
Add pin-controlled Low-Noise BB clock definition. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Alex Elder <elder@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221209164855.128798-2-dmitry.baryshkov@linaro.org
2022-12-28arm64: dts: qcom: sm8450: add RPMH_REGULATOR_LEVEL_LOW_SVS_D1Dmitry Baryshkov
Add another power saving state used on SM8450. Unfortunately adding it in proper place causes renumbering of all the opp states in sm8450.dtsi Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221207012803.114959-2-dmitry.baryshkov@linaro.org
2022-12-27dt-bindings: clock: qcom: gcc-qcs404: add two GDSC entriesDmitry Baryshkov
On QCS404 platform the Global Clock Controller supports two GDSCs: MDSS (display) and OXILI (GPU). Add corresponding indices. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221226042154.2666748-2-dmitry.baryshkov@linaro.org
2022-12-26dt-bindings: power: r8a779g0: Add missing A3DUL power domainTam Nguyen
Add the power domain index for the A3DUL domain, as described in the R-Car V4H Series Hardware User's Manual Rev. 0.51 and later. Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> [geert: Manual reference] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/d61cf54b58629a76e007b9505dac7c2beb3b30db.1669740926.git.geert+renesas@glider.be
2022-12-21Merge tag 'rproc-v6.2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux Pull remoteproc updates from Bjorn Andersson: "rproc-virtio device names are now auto generated, to avoid conflicts between remoteproc instances. The imx_rproc driver is extended with support for communicating with and attaching to a running M4 on i.MX8QXP, as well as support for attaching to the M4 after self-recovering from a crash. Support is added for i.MX8QM and mailbox channels are reconnected during the recovery process, in order to avoid data corruption. The Xilinx Zynqmp firmware interface is extended and support for the Xilinx R5 RPU is introduced. Various resources leaks, primarily in error paths, throughout the Qualcomm drivers are corrected. Lastly a fix to ensure that pm_relax is invoked even if the remoteproc instance is stopped between a crash is being reported and the recovery handler is scheduled" * tag 'rproc-v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux: (25 commits) remoteproc: core: Do pm_relax when in RPROC_OFFLINE state remoteproc: qcom: q6v5: Fix missing clk_disable_unprepare() in q6v5_wcss_qcs404_power_on() remoteproc: qcom_q6v5_pas: Fix missing of_node_put() in adsp_alloc_memory_region() remoteproc: qcom_q6v5_pas: detach power domains on remove remoteproc: qcom_q6v5_pas: disable wakeup on probe fail or remove remoteproc: qcom: q6v5: Fix potential null-ptr-deref in q6v5_wcss_init_mmio() remoteproc: sysmon: fix memory leak in qcom_add_sysmon_subdev() remoteproc: sysmon: Make QMI message rules const drivers: remoteproc: Add Xilinx r5 remoteproc driver firmware: xilinx: Add RPU configuration APIs firmware: xilinx: Add shutdown/wakeup APIs firmware: xilinx: Add ZynqMP firmware ioctl enums for RPU configuration. arm64: dts: xilinx: zynqmp: Add RPU subsystem device node dt-bindings: remoteproc: Add Xilinx RPU subsystem bindings remoteproc: core: Use device_match_of_node() remoteproc: imx_rproc: Correct i.MX93 DRAM mapping remoteproc: imx_rproc: Enable attach recovery for i.MX8QM/QXP remoteproc: imx_rproc: Request mbox channel later remoteproc: imx_rproc: Support i.MX8QM remoteproc: imx_rproc: Support kicking Mcore from Linux for i.MX8QXP ...
2022-12-21Merge tag 'mailbox-v6.2' of ↵Linus Torvalds
git://git.linaro.org/landing-teams/working/fujitsu/integration Pull mailbox updates from Jassi Brar: - qcom: enable sc8280xp, sm8550 and sm4250 support - ti: default to ARCH_K3 for msg manager - mediatek: - add mt8188 and mt8186 support - request irq only after got ready - zynq-ipi: fix error handling after device_register - mpfs: check sys-con status - rockchip: simplify by using device_get_match_data * tag 'mailbox-v6.2' of git://git.linaro.org/landing-teams/working/fujitsu/integration: dt-bindings: mailbox: qcom-ipcc: Add compatible for SM8550 mailbox: mtk-cmdq: Do not request irq until we are ready mailbox: zynq-ipi: fix error handling while device_register() fails mailbox: mtk-cmdq-mailbox: Use platform data directly instead of copying mailbox: arm_mhuv2: Fix return value check in mhuv2_probe() dt-bindings: mailbox: mediatek,gce-mailbox: add mt8188 compatible name dt-bindings: mailbox: add GCE header file for mt8188 mailbox: mpfs: read the system controller's status mailbox: mtk-cmdq: add MT8186 support mailbox: mtk-cmdq: add gce ddr enable support flow mailbox: mtk-cmdq: add gce software ddr enable private data mailbox: mtk-cmdq: Use GCE_CTRL_BY_SW definition instead of number mailbox: rockchip: Use device_get_match_data() to simplify the code dt-bindings: mailbox: qcom-ipcc: Add sc8280xp compatible mailbox: config: ti-msgmgr: Default set to ARCH_K3 for TI msg manager mailbox: qcom-apcs-ipc: Add SM4250 APCS IPC support dt-bindings: mailbox: qcom: Add SM4250 APCS compatible
2022-12-19Merge tag 'phy-for-6.2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "This tme we have again a big pile of qcom-qmp-* changes, one new driver and bunch of new hardware support. New hardware support: - Allwinner H616 USB PHY and A100 DPHY support - TI J721s2, J784s4 and J721e support - Freescale i.MX8MP PCIe PHY support - New driver for Renesas Ethernet SERDES supporting R-Car S4-8 - Qualcomm SM8450 PCIe1 PHY support in EP mode - Qualcomm SC8280XP PCIe PHY support (including x4 mode) - Fixed Qualcomm SC8280XP USB4-USB3-DP PHY DT bindings Updates: - A big pile of updates on qcom-qmp-* drivers following the driver split and reorganization merged earlier - Phy order of API calls documentation update" * tag 'phy-for-6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (174 commits) phy: ti: phy-j721e-wiz: add j721s2-wiz-10g module support dt-bindings: phy-j721e-wiz: add j721s2 compatible string phy: use devm_platform_get_and_ioremap_resource() phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY variant phy: allwinner: phy-sun6i-mipi-dphy: Add a variant power-on hook phy: allwinner: phy-sun6i-mipi-dphy: Set the enable bit last phy: allwinner: phy-sun6i-mipi-dphy: Make RX support optional dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY variant dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts property phy: qcom-qmp-pcie: drop redundant clock allocation phy: qcom-qmp-usb: drop redundant clock allocation phy: qcom-qmp: drop unused type header phy: qcom-qmp-usb: drop sc8280xp reference-clock source dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: drop reference-clock source phy: qcom-qmp-combo: add support for updated sc8280xp binding phy: qcom-qmp-combo: rename DP_PHY register pointer phy: qcom-qmp-combo: rename common-register pointers phy: qcom-qmp-combo: clean up DP clock callbacks phy: qcom-qmp-combo: separate clock and provider registration phy: qcom-qmp-combo: add clock registration helper ...
2022-12-19Merge tag 'iommu-updates-v6.2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull iommu updates from Joerg Roedel: "Core code: - map/unmap_pages() cleanup - SVA and IOPF refactoring - Clean up and document return codes from device/domain attachment AMD driver: - Rework and extend parsing code for ivrs_ioapic, ivrs_hpet and ivrs_acpihid command line options - Some smaller cleanups Intel driver: - Blocking domain support - Cleanups S390 driver: - Fixes and improvements for attach and aperture handling PAMU driver: - Resource leak fix and cleanup Rockchip driver: - Page table permission bit fix Mediatek driver: - Improve safety from invalid dts input - Smaller fixes and improvements Exynos driver: - Fix driver initialization sequence Sun50i driver: - Remove IOMMU_DOMAIN_IDENTITY as it has not been working forever - Various other fixes" * tag 'iommu-updates-v6.2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (74 commits) iommu/mediatek: Fix forever loop in error handling iommu/mediatek: Fix crash on isr after kexec() iommu/sun50i: Remove IOMMU_DOMAIN_IDENTITY iommu/amd: Fix typo in macro parameter name iommu/mediatek: Remove unused "mapping" member from mtk_iommu_data iommu/mediatek: Improve safety for mediatek,smi property in larb nodes iommu/mediatek: Validate number of phandles associated with "mediatek,larbs" iommu/mediatek: Add error path for loop of mm_dts_parse iommu/mediatek: Use component_match_add iommu/mediatek: Add platform_device_put for recovering the device refcnt iommu/fsl_pamu: Fix resource leak in fsl_pamu_probe() iommu/vt-d: Use real field for indication of first level iommu/vt-d: Remove unnecessary domain_context_mapped() iommu/vt-d: Rename domain_add_dev_info() iommu/vt-d: Rename iommu_disable_dev_iotlb() iommu/vt-d: Add blocking domain support iommu/vt-d: Add device_block_translation() helper iommu/vt-d: Allocate pasid table in device probe path iommu/amd: Check return value of mmu_notifier_register() iommu/amd: Fix pci device refcount leak in ppr_notifier() ...
2022-12-18dt-bindings: mailbox: add GCE header file for mt8188Elvis Wang
Add Global Command Engine(GCE) header file to define the GCE thread priority, GCE subsys id, event and constant for mt8188. Signed-off-by: Elvis Wang <Elvis.Wang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno<angelogioacchino.delregno@collabora.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
generated by cgit (git 2.34.1) at 2025-07-19 08:41:06 +0000