// SPDX-License-Identifier:     GPL-2.0
/*
 * Copyright (C) 2025, Altera Corporation
 */
#include "socfpga_agilex5.dtsi"

/ {
	model = "SoCFPGA Agilex5 SoCDK NAND daughter board";
	compatible = "intel,socfpga-agilex5-socdk-nand", "intel,socfpga-agilex5";

	aliases {
		serial0 = &uart0;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	leds {
		compatible = "gpio-leds";
		led0 {
			label = "hps_led0";
			gpios = <&porta 6 GPIO_ACTIVE_HIGH>;
		};

		led1 {
			label = "hps_led1";
			gpios = <&porta 7 GPIO_ACTIVE_HIGH>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		/* We expect the bootloader to fill in the reg */
		reg = <0x0 0x80000000 0x0 0x0>;
	};
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&i2c0 {
	status = "okay";
};

&i3c0 {
	status = "okay";
};

&i3c1 {
	status = "okay";
};

&nand {
	status = "okay";

	nand@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0>;
		nand-bus-width = <8>;

		partition@0 {
			label = "u-boot";
			reg = <0 0x200000>;
		};
		partition@200000 {
			label = "root";
			reg = <0x200000 0xffe00000>;
		};
	};
};

&osc1 {
	clock-frequency = <25000000>;
};

&uart0 {
	status = "okay";
};

&watchdog0 {
	status = "okay";
};