// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
 * Copyright (c) 2024 Yao Zi <ziyao@disroot.org>
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rockchip,rk3528-cru.h>
#include <dt-bindings/reset/rockchip,rk3528-cru.h>

/ {
	compatible = "rockchip,rk3528";

	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		gpio3 = &gpio3;
		gpio4 = &gpio4;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&scmi_clk SCMI_CLK_CPU>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&scmi_clk SCMI_CLK_CPU>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a53";
			reg = <0x2>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&scmi_clk SCMI_CLK_CPU>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a53";
			reg = <0x3>;
			device_type = "cpu";
			enable-method = "psci";
			clocks = <&scmi_clk SCMI_CLK_CPU>;
		};
	};

	firmware {
		scmi: scmi {
			compatible = "arm,scmi-smc";
			arm,smc-id = <0x82000010>;
			shmem = <&scmi_shmem>;
			#address-cells = <1>;
			#size-cells = <0>;

			scmi_clk: protocol@14 {
				reg = <0x14>;
				#clock-cells = <1>;
			};
		};
	};

	pinctrl: pinctrl {
		compatible = "rockchip,rk3528-pinctrl";
		rockchip,grf = <&ioc_grf>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gpio0: gpio@ff610000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff610000 0x0 0x200>;
			clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio1: gpio@ffaf0000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xffaf0000 0x0 0x200>;
			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 32 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@ffb00000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xffb00000 0x0 0x200>;
			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 64 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@ffb10000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xffb10000 0x0 0x200>;
			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 96 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@ffb20000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xffb20000 0x0 0x200>;
			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 128 32>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	psci {
		compatible = "arm,psci-1.0", "arm,psci-0.2";
		method = "smc";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		scmi_shmem: shmem@10f000 {
			compatible = "arm,scmi-shmem";
			reg = <0x0 0x0010f000 0x0 0x100>;
			no-map;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	xin24m: clock-xin24m {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "xin24m";
		#clock-cells = <0>;
	};

	gmac0_clk: clock-gmac50m {
		compatible = "fixed-clock";
		clock-frequency = <50000000>;
		clock-output-names = "gmac0";
		#clock-cells = <0>;
	};

	soc {
		compatible = "simple-bus";
		ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>;
		#address-cells = <2>;
		#size-cells = <2>;

		gic: interrupt-controller@fed01000 {
			compatible = "arm,gic-400";
			reg = <0x0 0xfed01000 0 0x1000>,
			      <0x0 0xfed02000 0 0x2000>,
			      <0x0 0xfed04000 0 0x2000>,
			      <0x0 0xfed06000 0 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
						 IRQ_TYPE_LEVEL_LOW)>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <3>;
		};

		qos_crypto_a: qos@ff200000 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff200000 0x0 0x20>;
		};

		qos_crypto_p: qos@ff200080 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff200080 0x0 0x20>;
		};

		qos_dcf: qos@ff200100 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff200100 0x0 0x20>;
		};

		qos_dft2apb: qos@ff200200 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff200200 0x0 0x20>;
		};

		qos_dma2ddr: qos@ff200280 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff200280 0x0 0x20>;
		};

		qos_dmac: qos@ff200300 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff200300 0x0 0x20>;
		};

		qos_keyreader: qos@ff200380 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff200380 0x0 0x20>;
		};

		qos_cpu: qos@ff210000 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff210000 0x0 0x20>;
		};

		qos_debug: qos@ff210080 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff210080 0x0 0x20>;
		};

		qos_gpu_m0: qos@ff220000 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff220000 0x0 0x20>;
		};

		qos_gpu_m1: qos@ff220080 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff220080 0x0 0x20>;
		};

		qos_pmu_mcu: qos@ff240000 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff240000 0x0 0x20>;
		};

		qos_rkvdec: qos@ff250000 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff250000 0x0 0x20>;
		};

		qos_rkvenc: qos@ff260000 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff260000 0x0 0x20>;
		};

		qos_gmac0: qos@ff270000 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff270000 0x0 0x20>;
		};

		qos_hdcp: qos@ff270080 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff270080 0x0 0x20>;
		};

		qos_jpegdec: qos@ff270100 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff270100 0x0 0x20>;
		};

		qos_rga2_m0ro: qos@ff270200 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff270200 0x0 0x20>;
		};

		qos_rga2_m0wo: qos@ff270280 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff270280 0x0 0x20>;
		};

		qos_sdmmc0: qos@ff270300 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff270300 0x0 0x20>;
		};

		qos_usb2host: qos@ff270380 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff270380 0x0 0x20>;
		};

		qos_vdpp: qos@ff270480 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff270480 0x0 0x20>;
		};

		qos_vop: qos@ff270500 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff270500 0x0 0x20>;
		};

		qos_emmc: qos@ff280000 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff280000 0x0 0x20>;
		};

		qos_fspi: qos@ff280080 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff280080 0x0 0x20>;
		};

		qos_gmac1: qos@ff280100 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff280100 0x0 0x20>;
		};

		qos_pcie: qos@ff280180 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff280180 0x0 0x20>;
		};

		qos_sdio0: qos@ff280200 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff280200 0x0 0x20>;
		};

		qos_sdio1: qos@ff280280 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff280280 0x0 0x20>;
		};

		qos_tsp: qos@ff280300 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff280300 0x0 0x20>;
		};

		qos_usb3otg: qos@ff280380 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff280380 0x0 0x20>;
		};

		qos_vpu: qos@ff280400 {
			compatible = "rockchip,rk3528-qos", "syscon";
			reg = <0x0 0xff280400 0x0 0x20>;
		};

		vpu_grf: syscon@ff340000 {
			compatible = "rockchip,rk3528-vpu-grf", "syscon";
			reg = <0x0 0xff340000 0x0 0x8000>;
		};

		vo_grf: syscon@ff360000 {
			compatible = "rockchip,rk3528-vo-grf", "syscon";
			reg = <0x0 0xff360000 0x0 0x10000>;
		};

		cru: clock-controller@ff4a0000 {
			compatible = "rockchip,rk3528-cru";
			reg = <0x0 0xff4a0000 0x0 0x30000>;
			assigned-clocks =
				<&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>,
				<&cru PLL_PPLL>, <&cru PLL_CPLL>,
				<&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>,
				<&cru CLK_MATRIX_500M_SRC>,
				<&cru CLK_MATRIX_50M_SRC>,
				<&cru CLK_MATRIX_100M_SRC>,
				<&cru CLK_MATRIX_150M_SRC>,
				<&cru CLK_MATRIX_200M_SRC>,
				<&cru CLK_MATRIX_300M_SRC>,
				<&cru CLK_MATRIX_339M_SRC>,
				<&cru CLK_MATRIX_400M_SRC>,
				<&cru CLK_MATRIX_600M_SRC>,
				<&cru CLK_PPLL_50M_MATRIX>,
				<&cru CLK_PPLL_100M_MATRIX>,
				<&cru CLK_PPLL_125M_MATRIX>,
				<&cru ACLK_BUS_VOPGL_ROOT>;
			assigned-clock-rates =
				<32768>, <1188000000>,
				<1000000000>, <996000000>,
				<408000000>, <250000000>,
				<500000000>,
				<50000000>,
				<100000000>,
				<150000000>,
				<200000000>,
				<300000000>,
				<340000000>,
				<400000000>,
				<600000000>,
				<50000000>,
				<100000000>,
				<125000000>,
				<500000000>;
			clocks = <&xin24m>, <&gmac0_clk>;
			clock-names = "xin24m", "gmac0";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		ioc_grf: syscon@ff540000 {
			compatible = "rockchip,rk3528-ioc-grf", "syscon";
			reg = <0x0 0xff540000 0x0 0x40000>;
		};

		uart0: serial@ff9f0000 {
			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
			reg = <0x0 0xff9f0000 0x0 0x100>;
			clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
			clock-names = "baudclk", "apb_pclk";
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&dmac 8>, <&dmac 9>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart1: serial@ff9f8000 {
			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
			reg = <0x0 0xff9f8000 0x0 0x100>;
			clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
			clock-names = "baudclk", "apb_pclk";
			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&dmac 10>, <&dmac 11>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart2: serial@ffa00000 {
			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
			reg = <0x0 0xffa00000 0x0 0x100>;
			clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
			clock-names = "baudclk", "apb_pclk";
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&dmac 12>, <&dmac 13>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart3: serial@ffa08000 {
			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
			reg = <0x0 0xffa08000 0x0 0x100>;
			clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
			clock-names = "baudclk", "apb_pclk";
			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&dmac 14>, <&dmac 15>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart4: serial@ffa10000 {
			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
			reg = <0x0 0xffa10000 0x0 0x100>;
			clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
			clock-names = "baudclk", "apb_pclk";
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&dmac 16>, <&dmac 17>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart5: serial@ffa18000 {
			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
			reg = <0x0 0xffa18000 0x0 0x100>;
			clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
			clock-names = "baudclk", "apb_pclk";
			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&dmac 18>, <&dmac 19>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart6: serial@ffa20000 {
			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
			reg = <0x0 0xffa20000 0x0 0x100>;
			clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
			clock-names = "baudclk", "apb_pclk";
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&dmac 20>, <&dmac 21>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		uart7: serial@ffa28000 {
			compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
			reg = <0x0 0xffa28000 0x0 0x100>;
			clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
			clock-names = "baudclk", "apb_pclk";
			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
			dmas = <&dmac 22>, <&dmac 23>;
			reg-io-width = <4>;
			reg-shift = <2>;
			status = "disabled";
		};

		i2c0: i2c@ffa50000 {
			compatible = "rockchip,rk3528-i2c",
				     "rockchip,rk3399-i2c";
			reg = <0x0 0xffa50000 0x0 0x1000>;
			clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
			clock-names = "i2c", "pclk";
			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c1: i2c@ffa58000 {
			compatible = "rockchip,rk3528-i2c",
				     "rockchip,rk3399-i2c";
			reg = <0x0 0xffa58000 0x0 0x1000>;
			clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
			clock-names = "i2c", "pclk";
			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c2: i2c@ffa60000 {
			compatible = "rockchip,rk3528-i2c",
				     "rockchip,rk3399-i2c";
			reg = <0x0 0xffa60000 0x0 0x1000>;
			clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
			clock-names = "i2c", "pclk";
			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c2m1_xfer>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c3: i2c@ffa68000 {
			compatible = "rockchip,rk3528-i2c",
				     "rockchip,rk3399-i2c";
			reg = <0x0 0xffa68000 0x0 0x1000>;
			clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
			clock-names = "i2c", "pclk";
			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c4: i2c@ffa70000 {
			compatible = "rockchip,rk3528-i2c",
				     "rockchip,rk3399-i2c";
			reg = <0x0 0xffa70000 0x0 0x1000>;
			clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
			clock-names = "i2c", "pclk";
			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c4_xfer>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c5: i2c@ffa78000 {
			compatible = "rockchip,rk3528-i2c",
				     "rockchip,rk3399-i2c";
			reg = <0x0 0xffa78000 0x0 0x1000>;
			clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
			clock-names = "i2c", "pclk";
			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c6: i2c@ffa80000 {
			compatible = "rockchip,rk3528-i2c",
				     "rockchip,rk3399-i2c";
			reg = <0x0 0xffa80000 0x0 0x1000>;
			clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
			clock-names = "i2c", "pclk";
			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		i2c7: i2c@ffa88000 {
			compatible = "rockchip,rk3528-i2c",
				     "rockchip,rk3399-i2c";
			reg = <0x0 0xffa88000 0x0 0x1000>;
			clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
			clock-names = "i2c", "pclk";
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c7_xfer>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		pwm0: pwm@ffa90000 {
			compatible = "rockchip,rk3528-pwm",
				     "rockchip,rk3328-pwm";
			reg = <0x0 0xffa90000 0x0 0x10>;
			clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
			clock-names = "pwm", "pclk";
			#pwm-cells = <3>;
			status = "disabled";
		};

		pwm1: pwm@ffa90010 {
			compatible = "rockchip,rk3528-pwm",
				     "rockchip,rk3328-pwm";
			reg = <0x0 0xffa90010 0x0 0x10>;
			clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
			clock-names = "pwm", "pclk";
			#pwm-cells = <3>;
			status = "disabled";
		};

		pwm2: pwm@ffa90020 {
			compatible = "rockchip,rk3528-pwm",
				     "rockchip,rk3328-pwm";
			reg = <0x0 0xffa90020 0x0 0x10>;
			clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
			clock-names = "pwm", "pclk";
			#pwm-cells = <3>;
			status = "disabled";
		};

		pwm3: pwm@ffa90030 {
			compatible = "rockchip,rk3528-pwm",
				     "rockchip,rk3328-pwm";
			reg = <0x0 0xffa90030 0x0 0x10>;
			clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
			clock-names = "pwm", "pclk";
			#pwm-cells = <3>;
			status = "disabled";
		};

		pwm4: pwm@ffa98000 {
			compatible = "rockchip,rk3528-pwm",
				     "rockchip,rk3328-pwm";
			reg = <0x0 0xffa98000 0x0 0x10>;
			clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
			clock-names = "pwm", "pclk";
			#pwm-cells = <3>;
			status = "disabled";
		};

		pwm5: pwm@ffa98010 {
			compatible = "rockchip,rk3528-pwm",
				     "rockchip,rk3328-pwm";
			reg = <0x0 0xffa98010 0x0 0x10>;
			clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
			clock-names = "pwm", "pclk";
			#pwm-cells = <3>;
			status = "disabled";
		};

		pwm6: pwm@ffa98020 {
			compatible = "rockchip,rk3528-pwm",
				     "rockchip,rk3328-pwm";
			reg = <0x0 0xffa98020 0x0 0x10>;
			clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
			clock-names = "pwm", "pclk";
			#pwm-cells = <3>;
			status = "disabled";
		};

		pwm7: pwm@ffa98030 {
			compatible = "rockchip,rk3528-pwm",
				     "rockchip,rk3328-pwm";
			reg = <0x0 0xffa98030 0x0 0x10>;
			clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
			clock-names = "pwm", "pclk";
			#pwm-cells = <3>;
			status = "disabled";
		};

		saradc: adc@ffae0000 {
			compatible = "rockchip,rk3528-saradc";
			reg = <0x0 0xffae0000 0x0 0x10000>;
			clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
			clock-names = "saradc", "apb_pclk";
			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
			resets = <&cru SRST_P_SARADC>;
			reset-names = "saradc-apb";
			#io-channel-cells = <1>;
			status = "disabled";
		};

		gmac0: ethernet@ffbd0000 {
			compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
			reg = <0x0 0xffbd0000 0x0 0x10000>;
			clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>,
				 <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>,
				 <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>;
			clock-names = "stmmaceth", "clk_mac_ref",
				      "mac_clk_rx", "mac_clk_tx",
				      "pclk_mac", "aclk_mac";
			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq", "eth_wake_irq";
			phy-handle = <&rmii0_phy>;
			phy-mode = "rmii";
			resets = <&cru SRST_A_MAC_VO>;
			reset-names = "stmmaceth";
			rockchip,grf = <&vo_grf>;
			snps,axi-config = <&gmac0_stmmac_axi_setup>;
			snps,mixed-burst;
			snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
			snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
			snps,tso;
			status = "disabled";

			mdio0: mdio {
				compatible = "snps,dwmac-mdio";
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				rmii0_phy: ethernet-phy@2 {
					compatible = "ethernet-phy-ieee802.3-c22";
					reg = <0x2>;
					clocks = <&cru CLK_MACPHY>;
					phy-is-integrated;
					pinctrl-names = "default";
					pinctrl-0 = <&fephym0_led_link>,
						    <&fephym0_led_spd>;
					resets = <&cru SRST_MACPHY>;
				};
			};

			gmac0_stmmac_axi_setup: stmmac-axi-config {
				snps,blen = <0 0 0 0 16 8 4>;
				snps,rd_osr_lmt = <8>;
				snps,wr_osr_lmt = <4>;
			};

			gmac0_mtl_rx_setup: rx-queues-config {
				snps,rx-queues-to-use = <1>;
				queue0 {};
			};

			gmac0_mtl_tx_setup: tx-queues-config {
				snps,tx-queues-to-use = <1>;
				queue0 {};
			};
		};

		gmac1: ethernet@ffbe0000 {
			compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
			reg = <0x0 0xffbe0000 0x0 0x10000>;
			clocks = <&cru CLK_GMAC1_SRC_VPU>,
				 <&cru CLK_GMAC1_RMII_VPU>,
				 <&cru PCLK_MAC_VPU>,
				 <&cru ACLK_MAC_VPU>;
			clock-names = "stmmaceth",
				      "clk_mac_ref",
				      "pclk_mac",
				      "aclk_mac";
			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "macirq", "eth_wake_irq";
			resets = <&cru SRST_A_MAC>;
			reset-names = "stmmaceth";
			rockchip,grf = <&vpu_grf>;
			snps,axi-config = <&gmac1_stmmac_axi_setup>;
			snps,mixed-burst;
			snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
			snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
			snps,tso;
			status = "disabled";

			mdio1: mdio {
				compatible = "snps,dwmac-mdio";
				#address-cells = <0x1>;
				#size-cells = <0x0>;
			};

			gmac1_stmmac_axi_setup: stmmac-axi-config {
				snps,blen = <0 0 0 0 16 8 4>;
				snps,rd_osr_lmt = <8>;
				snps,wr_osr_lmt = <4>;
			};

			gmac1_mtl_rx_setup: rx-queues-config {
				snps,rx-queues-to-use = <1>;
				queue0 {};
			};

			gmac1_mtl_tx_setup: tx-queues-config {
				snps,tx-queues-to-use = <1>;
				queue0 {};
			};
		};

		sdhci: mmc@ffbf0000 {
			compatible = "rockchip,rk3528-dwcmshc",
				     "rockchip,rk3588-dwcmshc";
			reg = <0x0 0xffbf0000 0x0 0x10000>;
			assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>,
					  <&cru CCLK_SRC_EMMC>;
			assigned-clock-rates = <200000000>, <24000000>,
					       <200000000>;
			clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
				 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
				 <&cru TCLK_EMMC>;
			clock-names = "core", "bus", "axi", "block", "timer";
			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			max-frequency = <200000000>;
			pinctrl-names = "default";
			pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>,
				    <&emmc_strb>;
			resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
				 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
				 <&cru SRST_T_EMMC>;
			reset-names = "core", "bus", "axi", "block", "timer";
			status = "disabled";
		};

		sdio0: mmc@ffc10000 {
			compatible = "rockchip,rk3528-dw-mshc",
				     "rockchip,rk3288-dw-mshc";
			reg = <0x0 0xffc10000 0x0 0x4000>;
			clocks = <&cru HCLK_SDIO0>,
				 <&cru CCLK_SRC_SDIO0>,
				 <&cru SCLK_SDIO0_DRV>,
				 <&cru SCLK_SDIO0_SAMPLE>;
			clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
			fifo-depth = <0x100>;
			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
			max-frequency = <200000000>;
			pinctrl-names = "default";
			pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>;
			resets = <&cru SRST_H_SDIO0>;
			reset-names = "reset";
			status = "disabled";
		};

		sdio1: mmc@ffc20000 {
			compatible = "rockchip,rk3528-dw-mshc",
				     "rockchip,rk3288-dw-mshc";
			reg = <0x0 0xffc20000 0x0 0x4000>;
			clocks = <&cru HCLK_SDIO1>,
				 <&cru CCLK_SRC_SDIO1>,
				 <&cru SCLK_SDIO1_DRV>,
				 <&cru SCLK_SDIO1_SAMPLE>;
			clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
			fifo-depth = <0x100>;
			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			max-frequency = <200000000>;
			pinctrl-names = "default";
			pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>;
			resets = <&cru SRST_H_SDIO1>;
			reset-names = "reset";
			status = "disabled";
		};

		sdmmc: mmc@ffc30000 {
			compatible = "rockchip,rk3528-dw-mshc",
				     "rockchip,rk3288-dw-mshc";
			reg = <0x0 0xffc30000 0x0 0x4000>;
			clocks = <&cru HCLK_SDMMC0>,
				 <&cru CCLK_SRC_SDMMC0>,
				 <&cru SCLK_SDMMC_DRV>,
				 <&cru SCLK_SDMMC_SAMPLE>;
			clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
			fifo-depth = <0x100>;
			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			max-frequency = <150000000>;
			pinctrl-names = "default";
			pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>,
				    <&sdmmc_det>;
			resets = <&cru SRST_H_SDMMC0>;
			reset-names = "reset";
			rockchip,default-sample-phase = <90>;
			status = "disabled";
		};

		dmac: dma-controller@ffd60000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x0 0xffd60000 0x0 0x4000>;
			clocks = <&cru ACLK_DMAC>;
			clock-names = "apb_pclk";
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			arm,pl330-periph-burst;
		};
	};
};

#include "rk3528-pinctrl.dtsi"