// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
 * Copyright (c) 2024 MNT Research GmbH
 */

/dts-v1/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include <dt-bindings/usb/pd.h>

#include "rk3588-firefly-icore-3588q.dtsi"

/ {
	model = "MNT Reform 2 with RCORE RK3588 Module";
	compatible = "mntre,reform2-rcore", "firefly,icore-3588q", "rockchip,rk3588";
	chassis-type = "laptop";

	aliases {
		ethernet0 = &gmac0;
		mmc1 = &sdmmc;
	};

	chosen {
		stdout-path = "serial2:1500000n8";
	};

	backlight: backlight {
		compatible = "pwm-backlight";
		brightness-levels = <0 8 16 32 64 128 160 200 255>;
		default-brightness-level = <128>;
		enable-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
		pwms = <&pwm8 0 10000 0>;
	};

	gmac0_clkin: external-gmac0-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <125000000>;
		clock-output-names = "gmac0_clkin";
	};

	pcie30_avdd1v8: regulator-pcie30-avdd1v8 {
		compatible = "regulator-fixed";
		regulator-boot-on;
		regulator-always-on;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-name = "pcie30_avdd1v8";
		vin-supply = <&avcc_1v8_s0>;
	};

	pcie30_avdd0v75: regulator-pcie30-avdd0v75 {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <750000>;
		regulator-max-microvolt = <750000>;
		regulator-name = "pcie30_avdd0v75";
		vin-supply = <&avdd_0v75_s0>;
	};

	vcc12v_dcin: regulator-vcc12v-dcin {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-name = "vcc12v_dcin";
	};

	vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 {
		compatible = "regulator-fixed";
		regulator-name = "vcc_1v1_nldo_s3";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <1100000>;
		regulator-max-microvolt = <1100000>;
		vin-supply = <&vcc5v0_sys>;
	};

	vcc3v3_pcie30: regulator-vcc3v3-pcie30 {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-name = "vcc3v3_pcie30";
		vin-supply = <&vcc12v_dcin>;
	};

	vcc5v0_host: regulator-vcc5v0-host {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-name = "vcc5v0_host";
	};

	vcc5v0_sys: regulator-vcc5v0-sys {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-name = "vcc5v0_sys";
		vin-supply = <&vcc12v_dcin>;
	};

	vcc5v0_usb: regulator-vcc5v0-usb {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		regulator-name = "vcc5v0_usb";
		vin-supply = <&vcc12v_dcin>;
	};
};

&combphy0_ps {
	status = "okay";
};

&gmac0 {
	clock_in_out = "output";
	phy-handle = <&rgmii_phy>;
	phy-mode = "rgmii-id";
	pinctrl-names = "default";
	pinctrl-0 = <&gmac0_miim
		     &gmac0_tx_bus2
		     &gmac0_rx_bus2
		     &gmac0_rgmii_clk
		     &gmac0_rgmii_bus
		     &gmac0_clkinout
		     &eth_phy_reset>;
	status = "okay";
};

&gpu {
	mali-supply = <&vdd_gpu_s0>;
	sram-supply = <&vdd_gpu_mem_s0>;
	status = "okay";
};

&hdmi0 {
	status = "okay";
};

&hdmi0_in {
	hdmi0_in_vp2: endpoint {
		remote-endpoint = <&vp2_out_hdmi0>;
	};
};

&hdptxphy0 {
	status = "okay";
};

&i2c6 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c6m0_xfer>;
	status = "okay";

	rtc@68 {
		compatible = "nxp,pcf8523";
		reg = <0x68>;
	};
};

&mdio0 {
	rgmii_phy: ethernet-phy@0 {
		compatible = "ethernet-phy-ieee802.3-c22";
		reg = <0x0>;
	};
};

&pcie2x1l2 {
	pinctrl-0 = <&pcie2_0_rst>;
	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&pcie30phy {
	status = "okay";
};

&pcie3x4 {
	num-lanes = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pcie3_reset>;
	reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
	vpcie3v3-supply = <&vcc3v3_pcie30>;
	status = "okay";
};

&pinctrl {
	dp {
		dp1_hpd: dp1-hpd {
			rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	pcie2 {
		pcie2_0_rst: pcie2-0-rst {
			rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	pcie3 {
		pcie3_reset: pcie3-reset {
			rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	eth_phy {
		eth_phy_reset: eth-phy-reset {
			rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};
};

&pwm8 {
	pinctrl-0 = <&pwm8m2_pins>;
	status = "okay";
};

&saradc {
	vref-supply = <&avcc_1v8_s0>;
	status = "okay";
};

&sdmmc {
	bus-width = <4>;
	cap-sd-highspeed;
	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
	disable-wp;
	max-frequency = <40000000>;
	no-1-8-v;
	no-mmc;
	no-sdio;
	vmmc-supply = <&vcc3v3_pcie30>;
	vqmmc-supply = <&vcc3v3_pcie30>;
	status = "okay";
};

&tsadc {
	status = "okay";
};

&u2phy0 {
	status = "okay";
};

&u2phy0_otg {
	status = "okay";
};

&u2phy1 {
	status = "okay";
};

&u2phy1_otg {
	status = "okay";
};

&u2phy2 {
	status = "okay";
};

&u2phy2_host {
	phy-supply = <&vcc5v0_host>;
	status = "okay";
};

&u2phy3 {
	status = "okay";
};

&u2phy3_host {
	phy-supply = <&vcc5v0_host>;
	status = "okay";
};

&usbdp_phy0 {
	status = "okay";
};

&usbdp_phy1 {
	status = "okay";
};

&usb_host0_ehci {
	status = "okay";
};

&usb_host0_ohci {
	status = "okay";
};

&usb_host0_xhci {
	dr_mode = "host";
	status = "okay";
};

&usb_host1_ehci {
	status = "okay";
};

&usb_host1_ohci {
	status = "okay";
};

&usb_host1_xhci {
	dr_mode = "host";
	status = "okay";
};

&vop {
	status = "okay";
};

&vop_mmu {
	status = "okay";
};

&vp2 {
	vp2_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
		remote-endpoint = <&hdmi0_in_vp2>;
	};
};