diff options
| author | Icenowy Zheng <uwu@icenowy.me> | 2025-10-20 13:35:23 +0800 |
|---|---|---|
| committer | Christian König <christian.koenig@amd.com> | 2025-10-28 09:19:46 +0100 |
| commit | 4f9ffd2c80a2fa09dcc8dfa0482cb7e0fb6fcf6c (patch) | |
| tree | 88218ab9ced7217263c31201516f1c4a366b7224 | |
| parent | a80c98b6f0d900f820ea9c76c367348804c1e895 (diff) | |
drm/ttm: add pgprot handling for RISC-V
The RISC-V Svpbmt privileged extension provides support for overriding
page memory coherency attributes, and, along with vendor extensions like
Xtheadmae, supports pgprot_{writecombine,noncached} on RISC-V.
Adapt the codepath that maps ttm_write_combined to pgprot_writecombine
and ttm_noncached to pgprot_noncached to RISC-V, to allow proper page
access attributes.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
Tested-by: Han Gao <rabenda.cn@gmail.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Link: https://lore.kernel.org/r/20251020053523.731353-1-uwu@icenowy.me
| -rw-r--r-- | drivers/gpu/drm/ttm/ttm_module.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c index b3fffe7b5062..aa137ead5cc5 100644 --- a/drivers/gpu/drm/ttm/ttm_module.c +++ b/drivers/gpu/drm/ttm/ttm_module.c @@ -74,7 +74,8 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp) #endif /* CONFIG_UML */ #endif /* __i386__ || __x86_64__ */ #if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \ - defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) + defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) || \ + defined(__riscv) if (caching == ttm_write_combined) tmp = pgprot_writecombine(tmp); else |