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authorAndrew Cooper <andrew.cooper3@citrix.com>2025-10-20 15:41:24 +0100
committerBorislav Petkov (AMD) <bp@alien8.de>2025-10-21 12:16:51 +0200
commit876f0d43af78639790bee0e57b39d498ae35adcf (patch)
tree710d037adc53c0fc344405434b0861310a9dd05e
parent19de7113bfac33ba92c004a9b510612bb745cfa0 (diff)
x86/microcode: Fix Entrysign revision check for Zen1/Naples
... to match AMD's statement here: https://www.amd.com/en/resources/product-security/bulletin/amd-sb-7033.html Fixes: 50cef76d5cb0 ("x86/microcode/AMD: Load only SHA256-checksummed patches") Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Cc: <stable@kernel.org> Link: https://patch.msgid.link/20251020144124.2930784-1-andrew.cooper3@citrix.com
-rw-r--r--arch/x86/kernel/cpu/microcode/amd.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c
index cdce885e2fd5..28ed8c089024 100644
--- a/arch/x86/kernel/cpu/microcode/amd.c
+++ b/arch/x86/kernel/cpu/microcode/amd.c
@@ -194,7 +194,7 @@ static bool need_sha_check(u32 cur_rev)
}
switch (cur_rev >> 8) {
- case 0x80012: return cur_rev <= 0x800126f; break;
+ case 0x80012: return cur_rev <= 0x8001277; break;
case 0x80082: return cur_rev <= 0x800820f; break;
case 0x83010: return cur_rev <= 0x830107c; break;
case 0x86001: return cur_rev <= 0x860010e; break;