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| author | Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> | 2025-05-23 11:50:35 +0530 |
|---|---|---|
| committer | Animesh Manna <animesh.manna@intel.com> | 2025-05-26 13:18:15 +0530 |
| commit | 796b6df0f8f57c40e95bd49294cf5f869eab3e9b (patch) | |
| tree | 826f473acba4b2358be224990f11e24829e1a6c2 /scripts/gdb/linux/utils.py | |
| parent | 2c41d62f6fb16d591df17b29edaa81ea56569bb3 (diff) | |
drm/i915/dsb: add intel_dsb_gosub_finish()
A DSB buffer which will be used for GOSUB execution does not need
the DEWAKE mechanism but still need to be 64 bit aligned. Add helper
to finish preparation of a dsb buffer to be executed with GOSUB
instruction.
v2: Add a cacheline of noops at the end of GOSUB buffer (Ville)
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://lore.kernel.org/r/20250523062041.166468-6-chaitanya.kumar.borah@intel.com
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions