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| author | Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> | 2025-05-23 11:50:37 +0530 |
|---|---|---|
| committer | Animesh Manna <animesh.manna@intel.com> | 2025-05-26 13:18:16 +0530 |
| commit | 9dae0b6e9c8c05931c1708fa9e0f4d69166a61c0 (patch) | |
| tree | d32836b915fc73ef1f08eeb3d734b6dc2cf33994 /scripts/gdb/linux/utils.py | |
| parent | 78f237a6a61b102e0b4cd0ea842861e82ec323dd (diff) | |
drm/i915: s/dsb_color_vblank/dsb_color
With double buffer gamma registers in the mix, we need not wait for
vblank to execute gamma writes through dsb. Before we implement
that s/dsb_color_vblank/dsb_color.
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://lore.kernel.org/r/20250523062041.166468-8-chaitanya.kumar.borah@intel.com
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions