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| author | Serge Semin <Sergey.Semin@baikalelectronics.ru> | 2020-05-15 13:47:42 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2020-05-15 18:29:17 +0100 |
| commit | 0327f0b881dc5645c7ba670331e822cdaa8c5e09 (patch) | |
| tree | cfd79617fa6391a399db20d1259e27dd2787e138 /tools/perf/scripts/python/export-to-sqlite.py | |
| parent | 77810d484f4f28107391787dfa1c6c53d994c4fc (diff) | |
spi: dw: Clear DMAC register when done or stopped
If DMAC register is left uncleared any further DMAless transfers
may cause the DMAC hardware handshaking interface getting activated.
So the next DMA-based Rx/Tx transaction will be started right
after the dma_async_issue_pending() method is invoked even if no
DMATDLR/DMARDLR conditions are met. This at the same time may cause
the Tx/Rx FIFO buffers underrun/overrun. In order to fix this we
must clear DMAC register after a current DMA-based transaction is
finished.
Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20200515104758.6934-4-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-sqlite.py')
0 files changed, 0 insertions, 0 deletions