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-rw-r--r--arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi37
-rw-r--r--arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi41
-rw-r--r--arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi36
-rw-r--r--arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi74
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-a1.dtsi15
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-axg.dtsi21
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-g12a.dtsi27
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-g12b.dtsi62
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gx.dtsi27
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts4
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-gxm.dtsi24
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi5
-rw-r--r--arch/arm64/boot/dts/amlogic/meson-sm1.dtsi27
13 files changed, 385 insertions, 15 deletions
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
index 563bc2e662fa..fce45933fa28 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a4.dtsi
@@ -17,6 +17,13 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2>;
};
cpu1: cpu@1 {
@@ -24,6 +31,13 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2>;
};
cpu2: cpu@2 {
@@ -31,6 +45,13 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2>;
};
cpu3: cpu@3 {
@@ -38,6 +59,22 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x80000>; /* L2. 512 KB */
+ cache-line-size = <64>;
+ cache-sets = <512>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi
index cb9ea3ca6ee0..07aaaf71ea9a 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi
@@ -23,6 +23,13 @@
compatible = "arm,cortex-a35";
reg = <0x0 0x0>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2>;
};
cpu1: cpu@1 {
@@ -30,6 +37,22 @@
compatible = "arm,cortex-a35";
reg = <0x0 0x1>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x7d000>; /* L2. 512 KB */
+ cache-line-size = <64>;
+ cache-sets = <512>;
};
};
@@ -53,6 +76,13 @@
#clock-cells = <0>;
};
+ xtal_32k: xtal-clk-32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "xtal_32k";
+ #clock-cells = <0>;
+ };
+
sm: secure-monitor {
compatible = "amlogic,meson-gxbb-sm";
@@ -792,7 +822,7 @@
pwm_mn: pwm@54000 {
compatible = "amlogic,c3-pwm",
"amlogic,meson-s4-pwm";
- reg = <0x0 54000 0x0 0x24>;
+ reg = <0x0 0x54000 0x0 0x24>;
clocks = <&clkc_periphs CLKID_PWM_M>,
<&clkc_periphs CLKID_PWM_N>;
#pwm-cells = <3>;
@@ -967,6 +997,15 @@
clock-names = "core", "device";
status = "disabled";
};
+
+ rtc@9a000 {
+ compatible = "amlogic,c3-rtc",
+ "amlogic,a5-rtc";
+ reg = <0x0 0x9a000 0x0 0x38>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal_32k>, <&clkc_periphs CLKID_SYS_RTC>;
+ clock-names = "osc", "sys";
+ };
};
ethmac: ethernet@fdc00000 {
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
index 260918b37b9a..d262c0b66e4b 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-s7.dtsi
@@ -18,6 +18,13 @@
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2>;
};
cpu1: cpu@100 {
@@ -25,6 +32,13 @@
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2>;
};
cpu2: cpu@200 {
@@ -32,6 +46,13 @@
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2>;
};
cpu3: cpu@300 {
@@ -39,8 +60,23 @@
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2>;
};
+ l2: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x40000>; /* L2. 256 KB */
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
};
timer {
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
index ec743cad57db..6510068bcff9 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
@@ -53,6 +53,13 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2_cache_l>;
};
cpu101: cpu@101 {
@@ -60,6 +67,13 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2_cache_l>;
};
cpu102: cpu@102 {
@@ -67,6 +81,13 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x102>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2_cache_l>;
};
cpu103: cpu@103 {
@@ -74,6 +95,13 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x103>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2_cache_l>;
};
cpu0: cpu@0 {
@@ -81,6 +109,13 @@
compatible = "arm,cortex-a73";
reg = <0x0 0x0>;
enable-method = "psci";
+ d-cache-line-size = <64>;
+ d-cache-size = <0x10000>;
+ d-cache-sets = <64>;
+ i-cache-line-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <64>;
+ next-level-cache = <&l2_cache_b>;
};
cpu1: cpu@1 {
@@ -88,6 +123,13 @@
compatible = "arm,cortex-a73";
reg = <0x0 0x1>;
enable-method = "psci";
+ d-cache-line-size = <64>;
+ d-cache-size = <0x10000>;
+ d-cache-sets = <64>;
+ i-cache-line-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <64>;
+ next-level-cache = <&l2_cache_b>;
};
cpu2: cpu@2 {
@@ -95,6 +137,13 @@
compatible = "arm,cortex-a73";
reg = <0x0 0x2>;
enable-method = "psci";
+ d-cache-line-size = <64>;
+ d-cache-size = <0x10000>;
+ d-cache-sets = <64>;
+ i-cache-line-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <64>;
+ next-level-cache = <&l2_cache_b>;
};
cpu3: cpu@3 {
@@ -102,6 +151,31 @@
compatible = "arm,cortex-a73";
reg = <0x0 0x3>;
enable-method = "psci";
+ d-cache-line-size = <64>;
+ d-cache-size = <0x10000>;
+ d-cache-sets = <64>;
+ i-cache-line-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <64>;
+ next-level-cache = <&l2_cache_b>;
+ };
+
+ l2_cache_l: l2-cache-cluster0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x40000>; /* L2. 256 KB */
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
+
+ l2_cache_b: l2-cache-cluster1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x100000>; /* L2. 1 Mb */
+ cache-line-size = <64>;
+ cache-sets = <512>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index f7f25a10f409..27b68ed85c4c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -27,6 +27,12 @@
compatible = "arm,cortex-a35";
reg = <0x0 0x0>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@@ -36,6 +42,12 @@
compatible = "arm,cortex-a35";
reg = <0x0 0x1>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@@ -44,6 +56,9 @@
compatible = "cache";
cache-level = <2>;
cache-unified;
+ cache-size = <0x80000>; /* L2. 512 KB */
+ cache-line-size = <64>;
+ cache-sets = <512>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 2df143aa77ce..04fb130ac7c6 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -83,6 +83,12 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
dynamic-power-coefficient = <140>;
@@ -94,6 +100,12 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
dynamic-power-coefficient = <140>;
@@ -105,6 +117,12 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
dynamic-power-coefficient = <140>;
@@ -115,6 +133,9 @@
compatible = "cache";
cache-level = <2>;
cache-unified;
+ cache-size = <0x80000>; /* L2. 512 KB */
+ cache-line-size = <64>;
+ cache-sets = <512>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index deee61dbe074..1321ad95923d 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -17,6 +17,12 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@@ -26,6 +32,12 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@@ -35,6 +47,12 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@@ -44,6 +62,12 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@@ -52,6 +76,9 @@
compatible = "cache";
cache-level = <2>;
cache-unified;
+ cache-size = <0x80000>; /* L2. 512 KB */
+ cache-line-size = <64>;
+ cache-sets = <512>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
index 86e6ceb31d5e..f04efa828256 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi
@@ -49,7 +49,13 @@
reg = <0x0 0x0>;
enable-method = "psci";
capacity-dmips-mhz = <592>;
- next-level-cache = <&l2>;
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2_cache_l>;
#cooling-cells = <2>;
};
@@ -59,7 +65,13 @@
reg = <0x0 0x1>;
enable-method = "psci";
capacity-dmips-mhz = <592>;
- next-level-cache = <&l2>;
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2_cache_l>;
#cooling-cells = <2>;
};
@@ -69,7 +81,13 @@
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
- next-level-cache = <&l2>;
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2_cache_l>;
#cooling-cells = <2>;
};
@@ -79,7 +97,13 @@
reg = <0x0 0x101>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
- next-level-cache = <&l2>;
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
+ next-level-cache = <&l2_cache_l>;
#cooling-cells = <2>;
};
@@ -89,7 +113,13 @@
reg = <0x0 0x102>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
- next-level-cache = <&l2>;
+ d-cache-line-size = <64>;
+ d-cache-size = <0x10000>;
+ d-cache-sets = <64>;
+ i-cache-line-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <64>;
+ next-level-cache = <&l2_cache_b>;
#cooling-cells = <2>;
};
@@ -99,14 +129,32 @@
reg = <0x0 0x103>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
- next-level-cache = <&l2>;
+ d-cache-line-size = <64>;
+ d-cache-size = <0x10000>;
+ d-cache-sets = <64>;
+ i-cache-line-size = <64>;
+ i-cache-size = <0x10000>;
+ i-cache-sets = <64>;
+ next-level-cache = <&l2_cache_b>;
#cooling-cells = <2>;
};
- l2: l2-cache0 {
+ l2_cache_l: l2-cache-cluster0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
+ cache-size = <0x40000>; /* L2. 256 KB */
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
+
+ l2_cache_b: l2-cache-cluster1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x100000>; /* L2. 1MB */
+ cache-line-size = <64>;
+ cache-sets = <512>;
};
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index 7d99ca44e660..c1d8e81d95cb 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -95,6 +95,12 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
#cooling-cells = <2>;
@@ -105,6 +111,12 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
#cooling-cells = <2>;
@@ -115,6 +127,12 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
#cooling-cells = <2>;
@@ -125,6 +143,12 @@
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 0>;
#cooling-cells = <2>;
@@ -134,6 +158,9 @@
compatible = "cache";
cache-level = <2>;
cache-unified;
+ cache-size = <0x80000>; /* L2. 512 KB */
+ cache-line-size = <64>;
+ cache-sets = <512>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
index 959bd8d77a82..12e26f99d4f0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
@@ -348,10 +348,6 @@
bus-width = <4>;
cap-sd-highspeed;
- sd-uhs-sdr12;
- sd-uhs-sdr25;
- sd-uhs-sdr50;
- sd-uhs-ddr50;
max-frequency = <100000000>;
disable-wp;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
index 411cc312fc62..514c9bea6423 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
@@ -64,6 +64,12 @@
reg = <0x0 0x100>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
@@ -75,6 +81,12 @@
reg = <0x0 0x101>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
@@ -86,6 +98,12 @@
reg = <0x0 0x102>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
@@ -97,6 +115,12 @@
reg = <0x0 0x103>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
clocks = <&scpi_dvfs 1>;
#cooling-cells = <2>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
index 538b35036954..5e07f0f9538e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1-bananapi.dtsi
@@ -380,11 +380,10 @@
bus-width = <4>;
cap-sd-highspeed;
- max-frequency = <50000000>;
+ /* Boot failures are observed at 50MHz */
+ max-frequency = <35000000>;
disable-wp;
- /* TOFIX: SD card is barely usable in SDR modes */
-
cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
vmmc-supply = <&tflash_vdd>;
vqmmc-supply = <&vddio_c>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
index 966ebb19cc55..e5db8ce94062 100644
--- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi
@@ -55,6 +55,12 @@
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@@ -64,6 +70,12 @@
compatible = "arm,cortex-a55";
reg = <0x0 0x1>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@@ -73,6 +85,12 @@
compatible = "arm,cortex-a55";
reg = <0x0 0x2>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@@ -82,6 +100,12 @@
compatible = "arm,cortex-a55";
reg = <0x0 0x3>;
enable-method = "psci";
+ d-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <32>;
+ i-cache-line-size = <32>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <32>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
@@ -90,6 +114,9 @@
compatible = "cache";
cache-level = <2>;
cache-unified;
+ cache-size = <0x40000>; /* L2. 256 KB */
+ cache-line-size = <64>;
+ cache-sets = <256>;
};
};
generated by cgit (git 2.34.1) at 2025-10-18 01:23:02 +0000