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path: root/drivers/interconnect/qcom/sm7150.c
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Diffstat (limited to 'drivers/interconnect/qcom/sm7150.c')
-rw-r--r--drivers/interconnect/qcom/sm7150.c653
1 files changed, 319 insertions, 334 deletions
diff --git a/drivers/interconnect/qcom/sm7150.c b/drivers/interconnect/qcom/sm7150.c
index c8c77407cd50..0390d0468b48 100644
--- a/drivers/interconnect/qcom/sm7150.c
+++ b/drivers/interconnect/qcom/sm7150.c
@@ -14,1169 +14,1154 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
-#include "sm7150.h"
+
+static struct qcom_icc_node qhm_a1noc_cfg;
+static struct qcom_icc_node qhm_qup_center;
+static struct qcom_icc_node qhm_tsif;
+static struct qcom_icc_node xm_emmc;
+static struct qcom_icc_node xm_sdc2;
+static struct qcom_icc_node xm_sdc4;
+static struct qcom_icc_node xm_ufs_mem;
+static struct qcom_icc_node qhm_a2noc_cfg;
+static struct qcom_icc_node qhm_qdss_bam;
+static struct qcom_icc_node qhm_qup_north;
+static struct qcom_icc_node qnm_cnoc;
+static struct qcom_icc_node qxm_crypto;
+static struct qcom_icc_node qxm_ipa;
+static struct qcom_icc_node xm_pcie3_0;
+static struct qcom_icc_node xm_qdss_etr;
+static struct qcom_icc_node xm_usb3_0;
+static struct qcom_icc_node qxm_camnoc_hf0_uncomp;
+static struct qcom_icc_node qxm_camnoc_rt_uncomp;
+static struct qcom_icc_node qxm_camnoc_sf_uncomp;
+static struct qcom_icc_node qxm_camnoc_nrt_uncomp;
+static struct qcom_icc_node qnm_npu;
+static struct qcom_icc_node qhm_spdm;
+static struct qcom_icc_node qnm_snoc;
+static struct qcom_icc_node xm_qdss_dap;
+static struct qcom_icc_node qhm_cnoc_dc_noc;
+static struct qcom_icc_node acm_apps;
+static struct qcom_icc_node acm_sys_tcu;
+static struct qcom_icc_node qhm_gemnoc_cfg;
+static struct qcom_icc_node qnm_cmpnoc;
+static struct qcom_icc_node qnm_mnoc_hf;
+static struct qcom_icc_node qnm_mnoc_sf;
+static struct qcom_icc_node qnm_pcie;
+static struct qcom_icc_node qnm_snoc_gc;
+static struct qcom_icc_node qnm_snoc_sf;
+static struct qcom_icc_node qxm_gpu;
+static struct qcom_icc_node llcc_mc;
+static struct qcom_icc_node qhm_mnoc_cfg;
+static struct qcom_icc_node qxm_camnoc_hf;
+static struct qcom_icc_node qxm_camnoc_nrt;
+static struct qcom_icc_node qxm_camnoc_rt;
+static struct qcom_icc_node qxm_camnoc_sf;
+static struct qcom_icc_node qxm_mdp0;
+static struct qcom_icc_node qxm_mdp1;
+static struct qcom_icc_node qxm_rot;
+static struct qcom_icc_node qxm_venus0;
+static struct qcom_icc_node qxm_venus1;
+static struct qcom_icc_node qxm_venus_arm9;
+static struct qcom_icc_node qhm_snoc_cfg;
+static struct qcom_icc_node qnm_aggre1_noc;
+static struct qcom_icc_node qnm_aggre2_noc;
+static struct qcom_icc_node qnm_gemnoc;
+static struct qcom_icc_node qxm_pimem;
+static struct qcom_icc_node xm_gic;
+static struct qcom_icc_node qns_a1noc_snoc;
+static struct qcom_icc_node srvc_aggre1_noc;
+static struct qcom_icc_node qns_a2noc_snoc;
+static struct qcom_icc_node qns_pcie_gemnoc;
+static struct qcom_icc_node srvc_aggre2_noc;
+static struct qcom_icc_node qns_camnoc_uncomp;
+static struct qcom_icc_node qns_cdsp_gemnoc;
+static struct qcom_icc_node qhs_a1_noc_cfg;
+static struct qcom_icc_node qhs_a2_noc_cfg;
+static struct qcom_icc_node qhs_ahb2phy_north;
+static struct qcom_icc_node qhs_ahb2phy_south;
+static struct qcom_icc_node qhs_ahb2phy_west;
+static struct qcom_icc_node qhs_aop;
+static struct qcom_icc_node qhs_aoss;
+static struct qcom_icc_node qhs_camera_cfg;
+static struct qcom_icc_node qhs_camera_nrt_thrott_cfg;
+static struct qcom_icc_node qhs_camera_rt_throttle_cfg;
+static struct qcom_icc_node qhs_clk_ctl;
+static struct qcom_icc_node qhs_compute_dsp_cfg;
+static struct qcom_icc_node qhs_cpr_cx;
+static struct qcom_icc_node qhs_cpr_mx;
+static struct qcom_icc_node qhs_crypto0_cfg;
+static struct qcom_icc_node qhs_ddrss_cfg;
+static struct qcom_icc_node qhs_display_cfg;
+static struct qcom_icc_node qhs_display_throttle_cfg;
+static struct qcom_icc_node qhs_emmc_cfg;
+static struct qcom_icc_node qhs_glm;
+static struct qcom_icc_node qhs_gpuss_cfg;
+static struct qcom_icc_node qhs_imem_cfg;
+static struct qcom_icc_node qhs_ipa;
+static struct qcom_icc_node qhs_mnoc_cfg;
+static struct qcom_icc_node qhs_pcie_cfg;
+static struct qcom_icc_node qhs_pdm;
+static struct qcom_icc_node qhs_pimem_cfg;
+static struct qcom_icc_node qhs_prng;
+static struct qcom_icc_node qhs_qdss_cfg;
+static struct qcom_icc_node qhs_qupv3_center;
+static struct qcom_icc_node qhs_qupv3_north;
+static struct qcom_icc_node qhs_sdc2;
+static struct qcom_icc_node qhs_sdc4;
+static struct qcom_icc_node qhs_snoc_cfg;
+static struct qcom_icc_node qhs_spdm;
+static struct qcom_icc_node qhs_tcsr;
+static struct qcom_icc_node qhs_tlmm_north;
+static struct qcom_icc_node qhs_tlmm_south;
+static struct qcom_icc_node qhs_tlmm_west;
+static struct qcom_icc_node qhs_tsif;
+static struct qcom_icc_node qhs_ufs_mem_cfg;
+static struct qcom_icc_node qhs_usb3_0;
+static struct qcom_icc_node qhs_venus_cfg;
+static struct qcom_icc_node qhs_venus_cvp_throttle_cfg;
+static struct qcom_icc_node qhs_venus_throttle_cfg;
+static struct qcom_icc_node qhs_vsense_ctrl_cfg;
+static struct qcom_icc_node qns_cnoc_a2noc;
+static struct qcom_icc_node srvc_cnoc;
+static struct qcom_icc_node qhs_gemnoc;
+static struct qcom_icc_node qhs_llcc;
+static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg;
+static struct qcom_icc_node qns_gem_noc_snoc;
+static struct qcom_icc_node qns_llcc;
+static struct qcom_icc_node srvc_gemnoc;
+static struct qcom_icc_node ebi;
+static struct qcom_icc_node qns2_mem_noc;
+static struct qcom_icc_node qns_mem_noc_hf;
+static struct qcom_icc_node srvc_mnoc;
+static struct qcom_icc_node qhs_apss;
+static struct qcom_icc_node qns_cnoc;
+static struct qcom_icc_node qns_gemnoc_gc;
+static struct qcom_icc_node qns_gemnoc_sf;
+static struct qcom_icc_node qxs_imem;
+static struct qcom_icc_node qxs_pimem;
+static struct qcom_icc_node srvc_snoc;
+static struct qcom_icc_node xs_qdss_stm;
+static struct qcom_icc_node xs_sys_tcu_cfg;
static struct qcom_icc_node qhm_a1noc_cfg = {
- .name = "qhm-a1noc-cfg",
- .id = SM7150_MASTER_A1NOC_CFG,
+ .name = "qhm_a1noc_cfg",
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SM7150_SLAVE_SERVICE_A1NOC },
+ .link_nodes = { &srvc_aggre1_noc },
};
static struct qcom_icc_node qhm_qup_center = {
.name = "qhm_qup_center",
- .id = SM7150_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SM7150_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node qhm_tsif = {
.name = "qhm_tsif",
- .id = SM7150_MASTER_TSIF,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SM7150_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_emmc = {
.name = "xm_emmc",
- .id = SM7150_MASTER_EMMC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SM7150_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
- .id = SM7150_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SM7150_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
- .id = SM7150_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SM7150_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
- .id = SM7150_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SM7150_A1NOC_SNOC_SLV },
+ .link_nodes = { &qns_a1noc_snoc },
};
static struct qcom_icc_node qhm_a2noc_cfg = {
.name = "qhm_a2noc_cfg",
- .id = SM7150_MASTER_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SM7150_SLAVE_SERVICE_A2NOC },
+ .link_nodes = { &srvc_aggre2_noc },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
- .id = SM7150_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SM7150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_node qhm_qup_north = {
.name = "qhm_qup_north",
- .id = SM7150_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SM7150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_node qnm_cnoc = {
.name = "qnm_cnoc",
- .id = SM7150_MASTER_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SM7150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
- .id = SM7150_MASTER_CRYPTO_CORE_0,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SM7150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
- .id = SM7150_MASTER_IPA,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SM7150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
- .id = SM7150_MASTER_PCIE,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SM7150_SLAVE_ANOC_PCIE_GEM_NOC },
+ .link_nodes = { &qns_pcie_gemnoc },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
- .id = SM7150_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SM7150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
- .id = SM7150_MASTER_USB3,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SM7150_A2NOC_SNOC_SLV },
+ .link_nodes = { &qns_a2noc_snoc },
};
static struct qcom_icc_node qxm_camnoc_hf0_uncomp = {
.name = "qxm_camnoc_hf0_uncomp",
- .id = SM7150_MASTER_CAMNOC_HF0_UNCOMP,
.channels = 2,
.buswidth = 32,
.num_links = 1,
- .links = { SM7150_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp },
};
static struct qcom_icc_node qxm_camnoc_rt_uncomp = {
.name = "qxm_camnoc_rt_uncomp",
- .id = SM7150_MASTER_CAMNOC_RT_UNCOMP,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SM7150_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp },
};
static struct qcom_icc_node qxm_camnoc_sf_uncomp = {
.name = "qxm_camnoc_sf_uncomp",
- .id = SM7150_MASTER_CAMNOC_SF_UNCOMP,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SM7150_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp },
};
static struct qcom_icc_node qxm_camnoc_nrt_uncomp = {
.name = "qxm_camnoc_nrt_uncomp",
- .id = SM7150_MASTER_CAMNOC_NRT_UNCOMP,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SM7150_SLAVE_CAMNOC_UNCOMP },
+ .link_nodes = { &qns_camnoc_uncomp },
};
static struct qcom_icc_node qnm_npu = {
.name = "qnm_npu",
- .id = SM7150_MASTER_NPU,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SM7150_SLAVE_CDSP_GEM_NOC },
+ .link_nodes = { &qns_cdsp_gemnoc },
};
static struct qcom_icc_node qhm_spdm = {
.name = "qhm_spdm",
- .id = SM7150_MASTER_SPDM,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SM7150_SLAVE_CNOC_A2NOC },
+ .link_nodes = { &qns_cnoc_a2noc },
};
static struct qcom_icc_node qnm_snoc = {
.name = "qnm_snoc",
- .id = SM7150_SNOC_CNOC_MAS,
.channels = 1,
.buswidth = 8,
.num_links = 47,
- .links = { SM7150_SLAVE_TLMM_SOUTH,
- SM7150_SLAVE_CAMERA_CFG,
- SM7150_SLAVE_SDCC_4,
- SM7150_SLAVE_SDCC_2,
- SM7150_SLAVE_CNOC_MNOC_CFG,
- SM7150_SLAVE_UFS_MEM_CFG,
- SM7150_SLAVE_QUP_0,
- SM7150_SLAVE_GLM,
- SM7150_SLAVE_PDM,
- SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG,
- SM7150_SLAVE_A2NOC_CFG,
- SM7150_SLAVE_QDSS_CFG,
- SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG,
- SM7150_SLAVE_DISPLAY_CFG,
- SM7150_SLAVE_PCIE_CFG,
- SM7150_SLAVE_DISPLAY_THROTTLE_CFG,
- SM7150_SLAVE_TCSR,
- SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG,
- SM7150_SLAVE_CNOC_DDRSS,
- SM7150_SLAVE_AHB2PHY_NORTH,
- SM7150_SLAVE_SNOC_CFG,
- SM7150_SLAVE_GRAPHICS_3D_CFG,
- SM7150_SLAVE_VENUS_CFG,
- SM7150_SLAVE_TSIF,
- SM7150_SLAVE_CDSP_CFG,
- SM7150_SLAVE_CLK_CTL,
- SM7150_SLAVE_AOP,
- SM7150_SLAVE_QUP_1,
- SM7150_SLAVE_AHB2PHY_SOUTH,
- SM7150_SLAVE_SERVICE_CNOC,
- SM7150_SLAVE_AHB2PHY_WEST,
- SM7150_SLAVE_USB3,
- SM7150_SLAVE_VENUS_THROTTLE_CFG,
- SM7150_SLAVE_IPA_CFG,
- SM7150_SLAVE_RBCPR_CX_CFG,
- SM7150_SLAVE_TLMM_WEST,
- SM7150_SLAVE_A1NOC_CFG,
- SM7150_SLAVE_AOSS,
- SM7150_SLAVE_PRNG,
- SM7150_SLAVE_VSENSE_CTRL_CFG,
- SM7150_SLAVE_EMMC_CFG,
- SM7150_SLAVE_SPDM_WRAPPER,
- SM7150_SLAVE_CRYPTO_0_CFG,
- SM7150_SLAVE_PIMEM_CFG,
- SM7150_SLAVE_TLMM_NORTH,
- SM7150_SLAVE_RBCPR_MX_CFG,
- SM7150_SLAVE_IMEM_CFG
- },
+ .link_nodes = { &qhs_tlmm_south,
+ &qhs_camera_cfg,
+ &qhs_sdc4,
+ &qhs_sdc2,
+ &qhs_mnoc_cfg,
+ &qhs_ufs_mem_cfg,
+ &qhs_qupv3_center,
+ &qhs_glm,
+ &qhs_pdm,
+ &qhs_camera_nrt_thrott_cfg,
+ &qhs_a2_noc_cfg,
+ &qhs_qdss_cfg,
+ &qhs_camera_rt_throttle_cfg,
+ &qhs_display_cfg,
+ &qhs_pcie_cfg,
+ &qhs_display_throttle_cfg,
+ &qhs_tcsr,
+ &qhs_venus_cvp_throttle_cfg,
+ &qhs_ddrss_cfg,
+ &qhs_ahb2phy_north,
+ &qhs_snoc_cfg,
+ &qhs_gpuss_cfg,
+ &qhs_venus_cfg,
+ &qhs_tsif,
+ &qhs_compute_dsp_cfg,
+ &qhs_clk_ctl,
+ &qhs_aop,
+ &qhs_qupv3_north,
+ &qhs_ahb2phy_south,
+ &srvc_cnoc,
+ &qhs_ahb2phy_west,
+ &qhs_usb3_0,
+ &qhs_venus_throttle_cfg,
+ &qhs_ipa,
+ &qhs_cpr_cx,
+ &qhs_tlmm_west,
+ &qhs_a1_noc_cfg,
+ &qhs_aoss,
+ &qhs_prng,
+ &qhs_vsense_ctrl_cfg,
+ &qhs_emmc_cfg,
+ &qhs_spdm,
+ &qhs_crypto0_cfg,
+ &qhs_pimem_cfg,
+ &qhs_tlmm_north,
+ &qhs_cpr_mx,
+ &qhs_imem_cfg },
};
static struct qcom_icc_node xm_qdss_dap = {
.name = "xm_qdss_dap",
- .id = SM7150_MASTER_QDSS_DAP,
.channels = 1,
.buswidth = 8,
.num_links = 48,
- .links = { SM7150_SLAVE_TLMM_SOUTH,
- SM7150_SLAVE_CAMERA_CFG,
- SM7150_SLAVE_SDCC_4,
- SM7150_SLAVE_SDCC_2,
- SM7150_SLAVE_CNOC_MNOC_CFG,
- SM7150_SLAVE_UFS_MEM_CFG,
- SM7150_SLAVE_QUP_0,
- SM7150_SLAVE_GLM,
- SM7150_SLAVE_PDM,
- SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG,
- SM7150_SLAVE_A2NOC_CFG,
- SM7150_SLAVE_QDSS_CFG,
- SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG,
- SM7150_SLAVE_DISPLAY_CFG,
- SM7150_SLAVE_PCIE_CFG,
- SM7150_SLAVE_DISPLAY_THROTTLE_CFG,
- SM7150_SLAVE_TCSR,
- SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG,
- SM7150_SLAVE_CNOC_DDRSS,
- SM7150_SLAVE_CNOC_A2NOC,
- SM7150_SLAVE_AHB2PHY_NORTH,
- SM7150_SLAVE_SNOC_CFG,
- SM7150_SLAVE_GRAPHICS_3D_CFG,
- SM7150_SLAVE_VENUS_CFG,
- SM7150_SLAVE_TSIF,
- SM7150_SLAVE_CDSP_CFG,
- SM7150_SLAVE_CLK_CTL,
- SM7150_SLAVE_AOP,
- SM7150_SLAVE_QUP_1,
- SM7150_SLAVE_AHB2PHY_SOUTH,
- SM7150_SLAVE_SERVICE_CNOC,
- SM7150_SLAVE_AHB2PHY_WEST,
- SM7150_SLAVE_USB3,
- SM7150_SLAVE_VENUS_THROTTLE_CFG,
- SM7150_SLAVE_IPA_CFG,
- SM7150_SLAVE_RBCPR_CX_CFG,
- SM7150_SLAVE_TLMM_WEST,
- SM7150_SLAVE_A1NOC_CFG,
- SM7150_SLAVE_AOSS,
- SM7150_SLAVE_PRNG,
- SM7150_SLAVE_VSENSE_CTRL_CFG,
- SM7150_SLAVE_EMMC_CFG,
- SM7150_SLAVE_SPDM_WRAPPER,
- SM7150_SLAVE_CRYPTO_0_CFG,
- SM7150_SLAVE_PIMEM_CFG,
- SM7150_SLAVE_TLMM_NORTH,
- SM7150_SLAVE_RBCPR_MX_CFG,
- SM7150_SLAVE_IMEM_CFG
- },
+ .link_nodes = { &qhs_tlmm_south,
+ &qhs_camera_cfg,
+ &qhs_sdc4,
+ &qhs_sdc2,
+ &qhs_mnoc_cfg,
+ &qhs_ufs_mem_cfg,
+ &qhs_qupv3_center,
+ &qhs_glm,
+ &qhs_pdm,
+ &qhs_camera_nrt_thrott_cfg,
+ &qhs_a2_noc_cfg,
+ &qhs_qdss_cfg,
+ &qhs_camera_rt_throttle_cfg,
+ &qhs_display_cfg,
+ &qhs_pcie_cfg,
+ &qhs_display_throttle_cfg,
+ &qhs_tcsr,
+ &qhs_venus_cvp_throttle_cfg,
+ &qhs_ddrss_cfg,
+ &qns_cnoc_a2noc,
+ &qhs_ahb2phy_north,
+ &qhs_snoc_cfg,
+ &qhs_gpuss_cfg,
+ &qhs_venus_cfg,
+ &qhs_tsif,
+ &qhs_compute_dsp_cfg,
+ &qhs_clk_ctl,
+ &qhs_aop,
+ &qhs_qupv3_north,
+ &qhs_ahb2phy_south,
+ &srvc_cnoc,
+ &qhs_ahb2phy_west,
+ &qhs_usb3_0,
+ &qhs_venus_throttle_cfg,
+ &qhs_ipa,
+ &qhs_cpr_cx,
+ &qhs_tlmm_west,
+ &qhs_a1_noc_cfg,
+ &qhs_aoss,
+ &qhs_prng,
+ &qhs_vsense_ctrl_cfg,
+ &qhs_emmc_cfg,
+ &qhs_spdm,
+ &qhs_crypto0_cfg,
+ &qhs_pimem_cfg,
+ &qhs_tlmm_north,
+ &qhs_cpr_mx,
+ &qhs_imem_cfg },
};
static struct qcom_icc_node qhm_cnoc_dc_noc = {
.name = "qhm_cnoc_dc_noc",
- .id = SM7150_MASTER_CNOC_DC_NOC,
.channels = 1,
.buswidth = 4,
.num_links = 2,
- .links = { SM7150_SLAVE_LLCC_CFG,
- SM7150_SLAVE_GEM_NOC_CFG
- },
+ .link_nodes = { &qhs_llcc,
+ &qhs_gemnoc },
};
static struct qcom_icc_node acm_apps = {
.name = "acm_apps",
- .id = SM7150_MASTER_AMPSS_M0,
.channels = 1,
.buswidth = 16,
.num_links = 2,
- .links = { SM7150_SLAVE_LLCC,
- SM7150_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc },
};
static struct qcom_icc_node acm_sys_tcu = {
.name = "acm_sys_tcu",
- .id = SM7150_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
.num_links = 2,
- .links = { SM7150_SLAVE_LLCC,
- SM7150_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc },
};
static struct qcom_icc_node qhm_gemnoc_cfg = {
.name = "qhm_gemnoc_cfg",
- .id = SM7150_MASTER_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 2,
- .links = { SM7150_SLAVE_SERVICE_GEM_NOC,
- SM7150_SLAVE_MSS_PROC_MS_MPU_CFG
- },
+ .link_nodes = { &srvc_gemnoc,
+ &qhs_mdsp_ms_mpu_cfg },
};
static struct qcom_icc_node qnm_cmpnoc = {
.name = "qnm_cmpnoc",
- .id = SM7150_MASTER_COMPUTE_NOC,
.channels = 1,
.buswidth = 32,
.num_links = 2,
- .links = { SM7150_SLAVE_LLCC,
- SM7150_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
- .id = SM7150_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
.num_links = 1,
- .links = { SM7150_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
- .id = SM7150_MASTER_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
.num_links = 2,
- .links = { SM7150_SLAVE_LLCC,
- SM7150_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
- .id = SM7150_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 2,
- .links = { SM7150_SLAVE_LLCC,
- SM7150_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
- .id = SM7150_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SM7150_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
- .id = SM7150_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SM7150_SLAVE_LLCC },
+ .link_nodes = { &qns_llcc },
};
static struct qcom_icc_node qxm_gpu = {
.name = "qxm_gpu",
- .id = SM7150_MASTER_GRAPHICS_3D,
.channels = 2,
.buswidth = 32,
.num_links = 2,
- .links = { SM7150_SLAVE_LLCC,
- SM7150_SLAVE_GEM_NOC_SNOC
- },
+ .link_nodes = { &qns_llcc,
+ &qns_gem_noc_snoc },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
- .id = SM7150_MASTER_LLCC,
.channels = 2,
.buswidth = 4,
.num_links = 1,
- .links = { SM7150_SLAVE_EBI_CH0 },
+ .link_nodes = { &ebi },
};
static struct qcom_icc_node qhm_mnoc_cfg = {
.name = "qhm_mnoc_cfg",
- .id = SM7150_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SM7150_SLAVE_SERVICE_MNOC },
+ .link_nodes = { &srvc_mnoc },
};
static struct qcom_icc_node qxm_camnoc_hf = {
.name = "qxm_camnoc_hf",
- .id = SM7150_MASTER_CAMNOC_HF0,
.channels = 2,
.buswidth = 32,
.num_links = 1,
- .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_node qxm_camnoc_nrt = {
.name = "qxm_camnoc_nrt",
- .id = SM7150_MASTER_CAMNOC_NRT,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc },
};
static struct qcom_icc_node qxm_camnoc_rt = {
.name = "qxm_camnoc_rt",
- .id = SM7150_MASTER_CAMNOC_RT,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_node qxm_camnoc_sf = {
.name = "qxm_camnoc_sf",
- .id = SM7150_MASTER_CAMNOC_SF,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc },
};
static struct qcom_icc_node qxm_mdp0 = {
.name = "qxm_mdp0",
- .id = SM7150_MASTER_MDP_PORT0,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_node qxm_mdp1 = {
.name = "qxm_mdp1",
- .id = SM7150_MASTER_MDP_PORT1,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SM7150_SLAVE_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_node qxm_rot = {
.name = "qxm_rot",
- .id = SM7150_MASTER_ROTATOR,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc },
};
static struct qcom_icc_node qxm_venus0 = {
.name = "qxm_venus0",
- .id = SM7150_MASTER_VIDEO_P0,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc },
};
static struct qcom_icc_node qxm_venus1 = {
.name = "qxm_venus1",
- .id = SM7150_MASTER_VIDEO_P1,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc },
};
static struct qcom_icc_node qxm_venus_arm9 = {
.name = "qxm_venus_arm9",
- .id = SM7150_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SM7150_SLAVE_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qns2_mem_noc },
};
static struct qcom_icc_node qhm_snoc_cfg = {
.name = "qhm_snoc_cfg",
- .id = SM7150_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SM7150_SLAVE_SERVICE_SNOC },
+ .link_nodes = { &srvc_snoc },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
- .id = SM7150_A1NOC_SNOC_MAS,
.channels = 1,
.buswidth = 16,
.num_links = 6,
- .links = { SM7150_SLAVE_SNOC_GEM_NOC_SF,
- SM7150_SLAVE_PIMEM,
- SM7150_SLAVE_OCIMEM,
- SM7150_SLAVE_APPSS,
- SM7150_SNOC_CNOC_SLV,
- SM7150_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qns_gemnoc_sf,
+ &qxs_pimem,
+ &qxs_imem,
+ &qhs_apss,
+ &qns_cnoc,
+ &xs_qdss_stm },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
- .id = SM7150_A2NOC_SNOC_MAS,
.channels = 1,
.buswidth = 16,
.num_links = 7,
- .links = { SM7150_SLAVE_SNOC_GEM_NOC_SF,
- SM7150_SLAVE_PIMEM,
- SM7150_SLAVE_OCIMEM,
- SM7150_SLAVE_APPSS,
- SM7150_SNOC_CNOC_SLV,
- SM7150_SLAVE_TCU,
- SM7150_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qns_gemnoc_sf,
+ &qxs_pimem,
+ &qxs_imem,
+ &qhs_apss,
+ &qns_cnoc,
+ &xs_sys_tcu_cfg,
+ &xs_qdss_stm },
};
static struct qcom_icc_node qnm_gemnoc = {
.name = "qnm_gemnoc",
- .id = SM7150_MASTER_GEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 6,
- .links = { SM7150_SLAVE_PIMEM,
- SM7150_SLAVE_OCIMEM,
- SM7150_SLAVE_APPSS,
- SM7150_SNOC_CNOC_SLV,
- SM7150_SLAVE_TCU,
- SM7150_SLAVE_QDSS_STM
- },
+ .link_nodes = { &qxs_pimem,
+ &qxs_imem,
+ &qhs_apss,
+ &qns_cnoc,
+ &xs_sys_tcu_cfg,
+ &xs_qdss_stm },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
- .id = SM7150_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
.num_links = 2,
- .links = { SM7150_SLAVE_SNOC_GEM_NOC_GC,
- SM7150_SLAVE_OCIMEM
- },
+ .link_nodes = { &qns_gemnoc_gc,
+ &qxs_imem },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
- .id = SM7150_MASTER_GIC,
.channels = 1,
.buswidth = 8,
.num_links = 2,
- .links = { SM7150_SLAVE_SNOC_GEM_NOC_GC,
- SM7150_SLAVE_OCIMEM
- },
+ .link_nodes = { &qns_gemnoc_gc,
+ &qxs_imem },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
- .id = SM7150_A1NOC_SNOC_SLV,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SM7150_A1NOC_SNOC_MAS },
+ .link_nodes = { &qnm_aggre1_noc },
};
static struct qcom_icc_node srvc_aggre1_noc = {
.name = "srvc_aggre1_noc",
- .id = SM7150_SLAVE_SERVICE_A1NOC,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
- .id = SM7150_A2NOC_SNOC_SLV,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SM7150_A2NOC_SNOC_MAS },
+ .link_nodes = { &qnm_aggre2_noc },
};
static struct qcom_icc_node qns_pcie_gemnoc = {
.name = "qns_pcie_gemnoc",
- .id = SM7150_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SM7150_MASTER_GEM_NOC_PCIE_SNOC },
+ .link_nodes = { &qnm_pcie },
};
static struct qcom_icc_node srvc_aggre2_noc = {
.name = "srvc_aggre2_noc",
- .id = SM7150_SLAVE_SERVICE_A2NOC,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_camnoc_uncomp = {
.name = "qns_camnoc_uncomp",
- .id = SM7150_SLAVE_CAMNOC_UNCOMP,
.channels = 1,
.buswidth = 32,
};
static struct qcom_icc_node qns_cdsp_gemnoc = {
.name = "qns_cdsp_gemnoc",
- .id = SM7150_SLAVE_CDSP_GEM_NOC,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SM7150_MASTER_COMPUTE_NOC },
+ .link_nodes = { &qnm_cmpnoc },
};
static struct qcom_icc_node qhs_a1_noc_cfg = {
.name = "qhs_a1_noc_cfg",
- .id = SM7150_SLAVE_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SM7150_MASTER_A1NOC_CFG },
+ .link_nodes = { &qhm_a1noc_cfg },
};
static struct qcom_icc_node qhs_a2_noc_cfg = {
.name = "qhs_a2_noc_cfg",
- .id = SM7150_SLAVE_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SM7150_MASTER_A2NOC_CFG },
+ .link_nodes = { &qhm_a2noc_cfg },
};
static struct qcom_icc_node qhs_ahb2phy_north = {
.name = "qhs_ahb2phy_north",
- .id = SM7150_SLAVE_AHB2PHY_NORTH,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ahb2phy_south = {
.name = "qhs_ahb2phy_south",
- .id = SM7150_SLAVE_AHB2PHY_SOUTH,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ahb2phy_west = {
.name = "qhs_ahb2phy_west",
- .id = SM7150_SLAVE_AHB2PHY_WEST,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_aop = {
.name = "qhs_aop",
- .id = SM7150_SLAVE_AOP,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
- .id = SM7150_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
- .id = SM7150_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_camera_nrt_thrott_cfg = {
.name = "qhs_camera_nrt_thrott_cfg",
- .id = SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
.name = "qhs_camera_rt_throttle_cfg",
- .id = SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
- .id = SM7150_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_compute_dsp_cfg = {
.name = "qhs_compute_dsp_cfg",
- .id = SM7150_SLAVE_CDSP_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
- .id = SM7150_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_cpr_mx = {
.name = "qhs_cpr_mx",
- .id = SM7150_SLAVE_RBCPR_MX_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
- .id = SM7150_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ddrss_cfg = {
.name = "qhs_ddrss_cfg",
- .id = SM7150_SLAVE_CNOC_DDRSS,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SM7150_MASTER_CNOC_DC_NOC },
+ .link_nodes = { &qhm_cnoc_dc_noc },
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
- .id = SM7150_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_display_throttle_cfg = {
.name = "qhs_display_throttle_cfg",
- .id = SM7150_SLAVE_DISPLAY_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_emmc_cfg = {
.name = "qhs_emmc_cfg",
- .id = SM7150_SLAVE_EMMC_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_glm = {
.name = "qhs_glm",
- .id = SM7150_SLAVE_GLM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
- .id = SM7150_SLAVE_GRAPHICS_3D_CFG,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
- .id = SM7150_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
- .id = SM7150_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_mnoc_cfg = {
.name = "qhs_mnoc_cfg",
- .id = SM7150_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SM7150_MASTER_CNOC_MNOC_CFG },
+ .link_nodes = { &qhm_mnoc_cfg },
};
static struct qcom_icc_node qhs_pcie_cfg = {
.name = "qhs_pcie_cfg",
- .id = SM7150_SLAVE_PCIE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
- .id = SM7150_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
- .id = SM7150_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_prng = {
.name = "qhs_prng",
- .id = SM7150_SLAVE_PRNG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
- .id = SM7150_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_qupv3_center = {
.name = "qhs_qupv3_center",
- .id = SM7150_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_qupv3_north = {
.name = "qhs_qupv3_north",
- .id = SM7150_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
- .id = SM7150_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
- .id = SM7150_SLAVE_SDCC_4,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_snoc_cfg = {
.name = "qhs_snoc_cfg",
- .id = SM7150_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SM7150_MASTER_SNOC_CFG },
+ .link_nodes = { &qhm_snoc_cfg },
};
static struct qcom_icc_node qhs_spdm = {
.name = "qhs_spdm",
- .id = SM7150_SLAVE_SPDM_WRAPPER,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
- .id = SM7150_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_tlmm_north = {
.name = "qhs_tlmm_north",
- .id = SM7150_SLAVE_TLMM_NORTH,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_tlmm_south = {
.name = "qhs_tlmm_south",
- .id = SM7150_SLAVE_TLMM_SOUTH,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_tlmm_west = {
.name = "qhs_tlmm_west",
- .id = SM7150_SLAVE_TLMM_WEST,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_tsif = {
.name = "qhs_tsif",
- .id = SM7150_SLAVE_TSIF,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
- .id = SM7150_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
- .id = SM7150_SLAVE_USB3,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
- .id = SM7150_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = {
.name = "qhs_venus_cvp_throttle_cfg",
- .id = SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_venus_throttle_cfg = {
.name = "qhs_venus_throttle_cfg",
- .id = SM7150_SLAVE_VENUS_THROTTLE_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
- .id = SM7150_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_cnoc_a2noc = {
.name = "qns_cnoc_a2noc",
- .id = SM7150_SLAVE_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SM7150_MASTER_CNOC_A2NOC },
+ .link_nodes = { &qnm_cnoc },
};
static struct qcom_icc_node srvc_cnoc = {
.name = "srvc_cnoc",
- .id = SM7150_SLAVE_SERVICE_CNOC,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_gemnoc = {
.name = "qhs_gemnoc",
- .id = SM7150_SLAVE_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
- .links = { SM7150_MASTER_GEM_NOC_CFG },
+ .link_nodes = { &qhm_gemnoc_cfg },
};
static struct qcom_icc_node qhs_llcc = {
.name = "qhs_llcc",
- .id = SM7150_SLAVE_LLCC_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
.name = "qhs_mdsp_ms_mpu_cfg",
- .id = SM7150_SLAVE_MSS_PROC_MS_MPU_CFG,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qns_gem_noc_snoc = {
.name = "qns_gem_noc_snoc",
- .id = SM7150_SLAVE_GEM_NOC_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SM7150_MASTER_GEM_NOC_SNOC },
+ .link_nodes = { &qnm_gemnoc },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
- .id = SM7150_SLAVE_LLCC,
.channels = 2,
.buswidth = 16,
.num_links = 1,
- .links = { SM7150_MASTER_LLCC },
+ .link_nodes = { &llcc_mc },
};
static struct qcom_icc_node srvc_gemnoc = {
.name = "srvc_gemnoc",
- .id = SM7150_SLAVE_SERVICE_GEM_NOC,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node ebi = {
.name = "ebi",
- .id = SM7150_SLAVE_EBI_CH0,
.channels = 2,
.buswidth = 4,
};
static struct qcom_icc_node qns2_mem_noc = {
.name = "qns2_mem_noc",
- .id = SM7150_SLAVE_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
.num_links = 1,
- .links = { SM7150_MASTER_MNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_sf },
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
- .id = SM7150_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
.num_links = 1,
- .links = { SM7150_MASTER_MNOC_HF_MEM_NOC },
+ .link_nodes = { &qnm_mnoc_hf },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
- .id = SM7150_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
- .id = SM7150_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_node qns_cnoc = {
.name = "qns_cnoc",
- .id = SM7150_SNOC_CNOC_SLV,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SM7150_SNOC_CNOC_MAS },
+ .link_nodes = { &qnm_snoc },
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
- .id = SM7150_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
- .links = { SM7150_MASTER_SNOC_GC_MEM_NOC },
+ .link_nodes = { &qnm_snoc_gc },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
- .id = SM7150_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
.num_links = 1,
- .links = { SM7150_MASTER_SNOC_SF_MEM_NOC },
+ .link_nodes = { &qnm_snoc_sf },
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
- .id = SM7150_SLAVE_OCIMEM,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
- .id = SM7150_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
- .id = SM7150_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
- .id = SM7150_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
- .id = SM7150_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
};
generated by cgit (git 2.34.1) at 2025-12-07 22:45:36 +0000