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2025-05-02drm/msm/dpu: rename non-SmartDMA feature masks to be more explicitDmitry Baryshkov
It is easy to skip or ignore the fact that the default SSPP feature masks for SDM845+ don't include the SmartDMA bit (both during development and during the review stage). Rename SSPP feature masks to make it more explicit that using non-SmartDMA masks should not be an exception rather than the rule. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/650425/ Link: https://lore.kernel.org/r/20250425-dpu-rework-vig-masks-v2-5-c71900687d08@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/dpu: enable SmartDMA on SM8550Dmitry Baryshkov
In order to support more versatile configuration of the display pipes on SM8550, enable SmartDMA for this platform. Patchwork: https://patchwork.freedesktop.org/patch/650424/ Link: https://lore.kernel.org/r/20250425-dpu-rework-vig-masks-v2-4-c71900687d08@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/dpu: enable SmartDMA on SC8280XPDmitry Baryshkov
In order to support more versatile configuration of the display pipes on SC8280XP, enable SmartDMA for this platform. Patchwork: https://patchwork.freedesktop.org/patch/650420/ Link: https://lore.kernel.org/r/20250425-dpu-rework-vig-masks-v2-3-c71900687d08@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/dpu: enable SmartDMA on SC8180XDmitry Baryshkov
Reworking of the catalog dropped the SmartDMA feature bit on the SC8180X platform. Renable SmartDMA support on this SoC. Fixes: 460c410f02e4 ("drm/msm/dpu: duplicate sdm845 catalog entries") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/650421/ Link: https://lore.kernel.org/r/20250425-dpu-rework-vig-masks-v2-2-c71900687d08@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/dpu: enable SmartDMA on SM8150Dmitry Baryshkov
Reworking of the catalog dropped the SmartDMA feature bit on the SM8150 platform. Renable SmartDMA support on this SoC. Fixes: 460c410f02e4 ("drm/msm/dpu: duplicate sdm845 catalog entries") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/650418/ Link: https://lore.kernel.org/r/20250425-dpu-rework-vig-masks-v2-1-c71900687d08@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/dpu: allow sharing SSPP between planesDmitry Baryshkov
Since SmartDMA planes provide two rectangles, it is possible to use them to drive two different DRM planes, first plane getting the rect_0, another one using rect_1 of the same SSPP. The sharing algorithm is pretty simple, it requires that each of the planes can be driven by the single rectangle and only consecutive planes are considered. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/650441/ Link: https://lore.kernel.org/r/20250426-dpu-share-sspp-v7-1-6f4c719e373c@oss.qualcomm.com Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
2025-05-02drm/msm/mdp4: switch LVDS to use drm_bridge/_connectorDmitry Baryshkov
LVDS support in MDP4 driver makes use of drm_connector directly. However LCDC encoder and LVDS connector are wrappers around drm_panel. Switch them to use drm_panel_bridge/drm_bridge_connector. This allows using standard interface for the drm_panel and also inserting additional bridges between encoder and panel. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/650290/ Link: https://lore.kernel.org/r/20250425-fd-mdp4-lvds-v4-6-6b212160b44c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/mdp4: move move_valid callback to lcdc_encoderDmitry Baryshkov
We can check the LCDC clock directly from the LCDC encoder driver, so remove it from the LVDS connector. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/650285/ Link: https://lore.kernel.org/r/20250425-fd-mdp4-lvds-v4-5-6b212160b44c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/mdp4: use parent_data for LVDS PLLDmitry Baryshkov
Instead of using .parent_names, use .parent_data, which binds parent clocks by using relative names specified in DT in addition to using global system clock names. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/650284/ Link: https://lore.kernel.org/r/20250425-fd-mdp4-lvds-v4-4-6b212160b44c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/mdp4: register the LVDS PLL as a clock providerDmitry Baryshkov
The LVDS/LCDC controller uses pixel clock coming from the multimedia controller (mmcc) rather than using the PLL directly. Stop using LVDS PLL directly and register it as a clock provider. Use lcdc_clk as a pixel clock for the LCDC. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/650280/ Link: https://lore.kernel.org/r/20250425-fd-mdp4-lvds-v4-3-6b212160b44c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02drm/msm/mdp4: drop mpd4_lvds_pll_init stubDmitry Baryshkov
Drop the !COMMON_CLK stub for mpd4_lvds_pll_init(), the DRM_MSM driver depends on COMMON_CLK. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/650281/ Link: https://lore.kernel.org/r/20250425-fd-mdp4-lvds-v4-2-6b212160b44c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02dt-bindings: display: msm: mdp4: add LCDC clock and PLL sourceDmitry Baryshkov
Add the LCDC / LVDS clock input and the XO used to drive internal LVDS PLL to MDP4 controller bindings. The controller also provides LVDS PHY PLL, so add optional #clock-cells to the device. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/650278/ Link: https://lore.kernel.org/r/20250425-fd-mdp4-lvds-v4-1-6b212160b44c@oss.qualcomm.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-02dt-bindings: msm: qcom,mdss: Document interconnect pathsLuca Weiss
Document two interconnect paths found on the MDSS on MSM8953. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Luca Weiss <luca@lucaweiss.eu> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/649391/ Link: https://lore.kernel.org/r/20250420-msm8953-interconnect-v2-1-828715dcb674@lucaweiss.eu Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-01drm/msm: Convert comma to semicolonChen Ni
Replace comma between expressions with semicolons. Using a ',' in place of a ';' can have unintended side effects. Although that is not the case here, it is seems best to use ';' unless ',' is intended. Found by inspection. No functional change intended. Compile tested only. Signed-off-by: Chen Ni <nichen@iscas.ac.cn> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Patchwork: https://patchwork.freedesktop.org/patch/647875/ Link: https://lore.kernel.org/r/20250410025221.3358387-1-nichen@iscas.ac.cn Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-01drm/msm/dpu: drop now-unused condition for has_legacy_ctlsDmitry Baryshkov
Now as we have dropped the DPU_CTL_SPLIT_DISPLAY from DPU >= 5.0 configuration, drop the rm->has_legacy_ctl condition which short-cutted the check for those platforms. Suggested-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/641586/ Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-8-5d20655f10ca@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-01drm/msm/dpu: remove DPU_CTL_SPLIT_DISPLAY from CTL blocks on DPU >= 5.0Dmitry Baryshkov
Since DPU 5.0 CTL blocks do not require DPU_CTL_SPLIT_DISPLAY, as single CTL is used for both interfaces. As both RM and encoder now handle active CTLs, drop that feature bit. Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/641592/ Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-7-5d20655f10ca@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-01drm/msm/dpu: allocate single CTL for DPU >= 5.0Dmitry Baryshkov
Unlike previous generation, since DPU 5.0 it is possible to use just one CTL to handle all INTF and WB blocks for a single output. And one has to use single CTL to support bonded DSI config. Allocate single CTL for these DPU versions. Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/641587/ Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-6-5d20655f10ca@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-01drm/msm/dpu: don't select single flush for active CTL blocksDmitry Baryshkov
In case of ACTIVE CTLs, a single CTL is being used for flushing all INTF blocks. Don't skip programming the CTL on those targets. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/641585/ Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-5-5d20655f10ca@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-01drm/msm/dpu: use single CTL if it is the only CTL returned by RMDmitry Baryshkov
On DPU >= 5.0 CTL blocks were reworked in order to support using a single CTL for all outputs. In preparation of reworking the RM code to return single CTL make sure that dpu_encoder can cope with that. Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/641582/ Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-4-5d20655f10ca@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-01drm/msm/dpu: pass master interface to CTL configurationDmitry Baryshkov
Active controls require setup of the master interface. Pass the selected interface to CTL configuration. Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/641583/ Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-3-5d20655f10ca@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-01drm/msm/dpu: program master INTF valueDmitry Baryshkov
If several interfaces are being handled through a single CTL, a main ('master') INTF needs to be programmed into a separate register. Write corresponding value into that register. Co-developed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/641581/ Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-2-5d20655f10ca@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-05-01drm/msm/dpu: don't overwrite CTL_MERGE_3D_ACTIVE registerDmitry Baryshkov
In case of complex pipelines (e.g. the forthcoming quad-pipe) the DPU might use more that one MERGE_3D block for a single output. Follow the pattern and extend the CTL_MERGE_3D_ACTIVE active register instead of simply writing new value there. Currently at most one MERGE_3D block is being used, so this has no impact on existing targets. Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/641580/ Link: https://lore.kernel.org/r/20250307-dpu-active-ctl-v3-1-5d20655f10ca@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2025-04-29Merge remote-tracking branch 'drm-misc/drm-misc-next' into msm-nextRob Clark
Merge drm-misc-next to get commit Fixes: fec450ca15af ("drm/display: hdmi: provide central data authority for ACR params"). Signed-off-by: Rob Clark <robdclark@chromium.org>
2025-04-29drm/panel-edp: Add support for CSW MNE007QS3-8 panelZhengqiao Xia
CSW MNE007QS3-8 EDID: edid-decode (hex): 00 ff ff ff ff ff ff 00 0e 77 57 14 00 00 00 00 34 22 01 04 a5 1e 13 78 07 ee 95 a3 54 4c 99 26 0f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 cd 7c 80 a0 70 b0 50 40 30 20 26 04 2e bc 10 00 00 1a cd 7c 80 a0 70 b0 50 45 30 20 26 04 2e bc 10 00 00 1a 00 00 00 fd 00 1e 78 9a 9a 20 01 0a 20 20 20 20 20 20 00 00 00 fc 00 4d 4e 45 30 30 37 51 53 33 2d 38 0a 20 01 3f 70 20 79 02 00 21 00 1d c8 0b 5d 07 80 07 b0 04 80 3d 8a 54 cd a4 99 66 62 0f 02 45 54 7c 5d 7c 5d 00 43 12 78 2b 00 0c 27 00 1e 77 00 00 27 00 1e 3b 00 00 2e 00 06 00 43 7c 5d 7c 5d 81 00 20 74 1a 00 00 03 01 1e 78 00 00 5a ff 5a ff 78 00 00 00 00 8d 00 e3 05 04 00 e6 06 01 01 5a 5a ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 76 90 Signed-off-by: Zhengqiao Xia <xiazhengqiao@huaqin.corp-partner.google.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20250429092030.8025-4-xiazhengqiao@huaqin.corp-partner.google.com
2025-04-29drm/panel-edp: Add support for BOE NE140WUM-N6S panelZhengqiao Xia
BOE NE140WUM-N6S EDID: edid-decode (hex): 00 ff ff ff ff ff ff 00 09 e5 73 0d 00 00 00 00 32 22 01 04 a5 1e 13 78 07 13 45 a6 54 4d a0 27 0c 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 03 3e 80 a0 70 b0 48 40 30 20 36 00 2e bc 10 00 00 1a 00 00 00 fd 00 1e 78 99 99 20 01 0a 20 20 20 20 20 20 00 00 00 fc 00 4e 45 31 34 30 57 55 4d 2d 4e 36 53 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 45 70 20 79 02 00 22 00 14 33 d8 04 85 7f 07 9f 00 2f 00 1f 00 af 04 47 00 02 00 05 00 81 00 13 72 1a 00 00 03 01 1e 78 00 00 5a 4a 5a 4a 78 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ad 90 Signed-off-by: Zhengqiao Xia <xiazhengqiao@huaqin.corp-partner.google.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20250429092030.8025-3-xiazhengqiao@huaqin.corp-partner.google.com
2025-04-29drm/panel-edp: Add support for AUO B140QAN08.H panelZhengqiao Xia
AUO B140QAN08.H EDID: edid-decode (hex): 00 ff ff ff ff ff ff 00 06 af b9 fe 00 00 00 00 00 23 01 04 a5 1e 13 78 03 c1 45 a8 55 48 9d 24 0f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 18 86 40 a0 b0 08 52 70 30 20 65 00 2d bc 10 00 00 18 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20 00 00 00 fd 00 28 3c 71 71 22 01 0a 20 20 20 20 20 20 00 00 00 fc 00 42 31 34 30 51 41 4e 30 38 2e 48 20 0a 01 79 70 20 79 02 00 21 01 1d c2 0b 58 07 40 0b 08 07 88 8b fa 54 7e 24 9d 45 12 0f 02 35 54 40 5e 40 5e 00 44 12 78 22 00 14 ef 3c 05 85 3f 0b 9f 00 2f 80 1f 00 07 07 51 00 05 00 04 00 25 01 09 ef 3c 05 ef 3c 05 28 3c 80 2e 00 06 00 44 40 5e 40 5e 81 00 15 74 1a 00 00 03 00 28 3c 00 00 60 ff 60 ff 3c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 4f 90 Signed-off-by: Zhengqiao Xia <xiazhengqiao@huaqin.corp-partner.google.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20250429092030.8025-2-xiazhengqiao@huaqin.corp-partner.google.com
2025-04-29drm/panthor: Fix build warning when DEBUG_FS is disabledAdrián Larumbe
Commit a3707f53eb3f ("drm/panthor: show device-wide list of DRM GEM objects over DebugFS") causes a build warning and linking error when built without support for DebugFS, because of a non-inline non-static function declaration in a header file. On top of that, the function is only being used inside a single compilation unit, so there is no point in exposing it as a global symbol. This is a follow-up from Arnd Bergmann's first fix. Also move panthor_gem_debugfs_set_usage_flags() into panthor_gem.c and declare it static. Fixes: a3707f53eb3f ("drm/panthor: show device-wide list of DRM GEM objects over DebugFS") Reported-by: Arnd Bergmann <arnd@arndb.de> Closes: https://lore.kernel.org/dri-devel/20250424142419.47b9d457@collabora.com/T/#t Signed-off-by: Adrián Larumbe <adrian.larumbe@collabora.com> Reviewed-by: Steven Price <steven.price@arm.com> Reviewed-by: Liviu Dudau <liviu.dudau@arm.com> Link: https://lore.kernel.org/r/20250424184041.356191-1-adrian.larumbe@collabora.com Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
2025-04-29drm/appletbdrm: Make appletbdrm depend on X86Aditya Garg
The appletbdrm driver is exclusively for Touch Bars on x86 Intel Macs. The M1 Macs have a separate driver. So, lets avoid compiling it for other architectures. Signed-off-by: Aditya Garg <gargaditya08@live.com> Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Link: https://lore.kernel.org/r/PN3PR01MB95970778982F28E4A3751392B8B72@PN3PR01MB9597.INDPRD01.PROD.OUTLOOK.COM Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2025-04-29vsprintf: Use %p4chR instead of %p4cn for reading data in reversed host orderingPetr Mladek
The generic FourCC format always prints the data using the big endian order. It is generic because it allows to read the data using a custom ordering. The current code uses "n" for reading data in the reverse host ordering. It makes the 4 variants [hnbl] consistent with the generic printing of IPv4 addresses. Unfortunately, it creates confusion on big endian systems. For example, it shows the data &(u32)0x67503030 as %p4cn 00Pg (0x30305067) But people expect that the ordering stays the same. The network ordering is a big-endian ordering. The problem is that the semantic is not the same. The modifiers affect the output ordering of IPv4 addresses while they affect the reading order in case of FourCC code. Avoid the confusion by replacing the "n" modifier with "hR", aka reverse host ordering. It is inspired by the existing %p[mM]R printf format. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Closes: https://lore.kernel.org/r/CAMuHMdV9tX=TG7E_CrSF=2PY206tXf+_yYRuacG48EWEtJLo-Q@mail.gmail.com Signed-off-by: Petr Mladek <pmladek@suse.com> Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Aditya Garg <gargaditya08@live.com> Link: https://lore.kernel.org/r/20250428123132.578771-1-pmladek@suse.com Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2025-04-29drm/st7571-i2c: select CONFIG_DRM_CLIENT_SELECTIONArnd Bergmann
The newly added driver calls drm_client_setup(), but that is not always built in: x86_64-linux-ld: vmlinux.o: in function `st7571_probe': st7571-i2c.c:(.text+0x7b7119): undefined reference to `drm_client_setup' Select the appropriate Kconfig symbol. Fixes: 4b35f0f41ee2 ("drm/st7571-i2c: add support for Sitronix ST7571 LCD controller") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Marcus Folkesson <marcus.folkesson@gmail.com> Link: https://lore.kernel.org/r/20250428150752.3970145-1-arnd@kernel.org Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
2025-04-29drm/bridge: imx8*-ldb: convert to devm_drm_bridge_alloc() APILuca Ceresoli
This is the new API for allocating DRM bridges. These two drivers are tangled together by the ldb_add_bridge_helper(), so they are converted at once. They also have a similar design, each embedding an array of channels in their main struct, and each channel embeds a drm_bridge. This prevents dynamic, refcount-based deallocation of the bridges. To make the new, dynamic bridge allocation possible: * change the array of channels into an array of channel pointers * allocate each channel using devm_drm_bridge_alloc() * adapt ldb_add_bridge_helper() to not set the funcs pointer (now done by devm_drm_bridge_alloc()) * adapt the code wherever using the channels Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Acked-by: Liu Ying <victor.liu@nxp.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250424-drm-bridge-convert-to-alloc-api-v2-31-8f91a404d86b@bootlin.com Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com>
2025-04-29drm/vc4: convert to devm_drm_bridge_alloc() APILuca Ceresoli
This is the new API for allocating DRM bridges. This driver already implements refcounting of the struct vc4_dsi, which embeds struct drm_bridge. Now this is a duplicate of the refcounting implemented by the DRM bridge core, so convert the vc4_dsi_get/put() calls into drm_bridge_get/put() calls and get rid of the driver-specific refcounting implementation. Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Acked-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250424-drm-bridge-convert-to-alloc-api-v2-27-8f91a404d86b@bootlin.com Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com>
2025-04-29drm/msm/hdmi: convert to devm_drm_bridge_alloc() APILuca Ceresoli
This is the new API for allocating DRM bridges. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250424-drm-bridge-convert-to-alloc-api-v2-18-8f91a404d86b@bootlin.com Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com>
2025-04-29drm/msm/dsi: convert to devm_drm_bridge_alloc() APILuca Ceresoli
This is the new API for allocating DRM bridges. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250424-drm-bridge-convert-to-alloc-api-v2-17-8f91a404d86b@bootlin.com Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com>
2025-04-29drm/msm/dp: convert to devm_drm_bridge_alloc() APILuca Ceresoli
This is the new API for allocating DRM bridges. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250424-drm-bridge-convert-to-alloc-api-v2-16-8f91a404d86b@bootlin.com Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com>
2025-04-29drm/mcde: convert to devm_drm_bridge_alloc() APILuca Ceresoli
This is the new API for allocating DRM bridges. Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20250424-drm-bridge-convert-to-alloc-api-v2-15-8f91a404d86b@bootlin.com Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com>
2025-04-29drm/exynos: mic: convert to devm_drm_bridge_alloc() APILuca Ceresoli
This is the new API for allocating DRM bridges. Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250424-drm-bridge-convert-to-alloc-api-v2-14-8f91a404d86b@bootlin.com Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com>
2025-04-29drm/bridge: ti-sn65dsi86: convert to devm_drm_bridge_alloc() APILuca Ceresoli
This is the new API for allocating DRM bridges. Reviewed-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20250424-drm-bridge-convert-to-alloc-api-v2-13-8f91a404d86b@bootlin.com Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com>
2025-04-29drm/bridge: tda998x: convert to devm_drm_bridge_alloc() APILuca Ceresoli
This is the new API for allocating DRM bridges. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250424-drm-bridge-convert-to-alloc-api-v2-12-8f91a404d86b@bootlin.com Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com>
2025-04-29drm/bridge: dw-hdmi: convert to devm_drm_bridge_alloc() APILuca Ceresoli
This is the new API for allocating DRM bridges. Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250424-drm-bridge-convert-to-alloc-api-v2-11-8f91a404d86b@bootlin.com Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com>
2025-04-29drm/bridge: lt9611uxc: convert to devm_drm_bridge_alloc() APILuca Ceresoli
This is the new API for allocating DRM bridges. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250424-drm-bridge-convert-to-alloc-api-v2-7-8f91a404d86b@bootlin.com Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com>
2025-04-29drm/bridge: display-connector: convert to devm_drm_bridge_alloc() APILuca Ceresoli
This is the new API for allocating DRM bridges. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250424-drm-bridge-convert-to-alloc-api-v2-6-8f91a404d86b@bootlin.com Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com>
2025-04-29drm/bridge: analogix-anx6345: convert to devm_drm_bridge_alloc() APILuca Ceresoli
This is the new API for allocating DRM bridges. Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Reviewed-by: Andy Yan <andyshrk@163.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250424-drm-bridge-convert-to-alloc-api-v2-3-8f91a404d86b@bootlin.com Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com>
2025-04-29platform: arm64: acer-aspire1-ec: convert to devm_drm_bridge_alloc() APILuca Ceresoli
This is the new API for allocating DRM bridges. Acked-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20250424-drm-bridge-convert-to-alloc-api-v2-2-8f91a404d86b@bootlin.com Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com>
2025-04-28drm/panfrost: reorder pd/clk/rst sequencePhilippe Simons
According to Mali manuals, the powerup sequence should be enable pd, asserting the reset then enabling the clock and the reverse for powerdown. Reviewed-by: Steven Price <steven.price@arm.com> Tested-by: John Williams <porschemad911@gmail.com> Signed-off-by: Philippe Simons <simons.philippe@gmail.com> Signed-off-by: Steven Price <steven.price@arm.com> Link: https://lore.kernel.org/r/20250403055210.54486-4-simons.philippe@gmail.com
2025-04-28drm/panfrost: add h616 compatible stringPhilippe Simons
Tie the Allwinner compatible string to the GPU_PM_RT feature bits that will toggle the clocks and the reset line whenever the power domain is changing state. Reviewed-by: Steven Price <steven.price@arm.com> Signed-off-by: Philippe Simons <simons.philippe@gmail.com> Signed-off-by: Steven Price <steven.price@arm.com> Link: https://lore.kernel.org/r/20250403055210.54486-3-simons.philippe@gmail.com
2025-04-28drm/panfrost: Add PM runtime flagPhilippe Simons
When the GPU is the only device attached to a single power domain, core genpd disable and enable it when gpu enter and leave runtime suspend. Some power-domain requires a sequence before disabled, and the reverse when enabled. Add GPU_PM_RT flag, and implement in panfrost_device_runtime_suspend/resume. Reviewed-by: Steven Price <steven.price@arm.com> Signed-off-by: Philippe Simons <simons.philippe@gmail.com> Signed-off-by: Steven Price <steven.price@arm.com> Link: https://lore.kernel.org/r/20250403055210.54486-2-simons.philippe@gmail.com
2025-04-27drm/v3d: client ranges from axi_ids are different with V3D 7.1Jose Maria Casanova Crespo
The client mask has been reduced from 8 bits on V3D 4.1 to 7 bits on V3D 7.1, so the ranges for each client are not compatible. On V3D 7.1, the CSD client can also report MMU errors. Therefore, add its AXI ID to the IDs list. Fixes: 0ad5bc1ce463 ("drm/v3d: fix up register addresses for V3D 7.x") Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com> Reviewed-by: Maíra Canal <mcanal@igalia.com> Link: https://lore.kernel.org/r/20250425122522.18425-2-jmcasanova@igalia.com Signed-off-by: Maíra Canal <mcanal@igalia.com>
2025-04-27drm/v3d: fix client obtained from axi_ids on V3D 4.1Jose Maria Casanova Crespo
In the case of MMU errors caused by the TFU unit, the client that causes the MMU error is expected to be reported. But in the case of MMU TFU errors, a non existing client was being reported. This happened because the client calculation was taking into account more than the bits 0-7 from the axi_id that were representing the client. [ 27.845132] v3d fec00000.v3d: MMU error from client ? (13) at 0x3bb1000, pte invalid Masking the bits and using the correct axi_id ranges fixes the calculation to report the real guilty client on V3D 4.1 and 4.2. Make the MMU error print axi_id with hexadecimal as used in the ranges. Fixes: 38c2c7917adc ("drm/v3d: Fix and extend MMU error handling.") Signed-off-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com> Reviewed-by: Maíra Canal <mcanal@igalia.com> Link: https://lore.kernel.org/r/20250425122522.18425-1-jmcasanova@igalia.com Signed-off-by: Maíra Canal <mcanal@igalia.com>
2025-04-25accel/ivpu: Implement heartbeat-based TDR mechanismKarol Wachowski
Introduce a heartbeat-based Timeout Detection and Recovery (TDR) mechanism. The enhancement aims to improve the reliability of device hang detection by monitoring heartbeat updates. Each progressing inference will update heartbeat counter allowing driver to monitor its progression. Limit maximum number of reschedules when heartbeat indicates progression to 30. This increases the maximum running time of single inference to about 60 seconds. The heartbeat mechanism provides a more robust method for detecting device hangs, potentially reducing false positive recoveries due to long running inferences. Signed-off-by: Karol Wachowski <karol.wachowski@intel.com> Signed-off-by: Maciej Falkowski <maciej.falkowski@linux.intel.com> Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Link: https://lore.kernel.org/r/20250416102555.384526-1-maciej.falkowski@linux.intel.com
generated by cgit (git 2.34.1) at 2025-07-15 13:13:32 +0000