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2022-02-22arm64: dts: renesas: spider-cpu: Enable watchdog timerGeert Uytterhoeven
Enable the watchdog timer on the Spider board. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/b36b2bb5770e10d906571721a3d73ca205b6f56e.1642525158.git.geert+renesas@glider.be
2022-02-22arm64: dts: renesas: r8a779f0: Add RWDT nodeGeert Uytterhoeven
Add a device node for the RCLK Watchdog Timer (RWDT) on the Renesas R-Car S4-8 (R8A779F0) SoC. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/556a7f41bdadceecbe8b59b79ac7e9f592ca17a2.1642525158.git.geert+renesas@glider.be
2022-02-22ARM: dts: imx6qp-sabresd: Enable PCIe supportRichard Zhu
In the i.MX6QP sabresd board(sch-28857) design, one external oscillator is powered up by vgen3 and used as the PCIe reference clock source by the endpoint device. If RC uses this oscillator as reference clock too, PLL6(ENET PLL) would has to be in bypass mode, and ENET clocks would be messed up. To keep things simple, let RC use the internal PLL as reference clock and set vgen3 always on to enable the external oscillator for endpoint device on i.MX6QP sabresd board. NOTE: This reference clock setup is used to pass the GEN2 TX compliance tests, and isn't recommended as a setup in the end-user design. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: juno: Add separate SCMI variantsRobin Murphy
While Juno's SCP firmware initially spoke the SCPI protocol, binary releases since 2018, and the newer open-source codebase, only speak SCMI and thus aren't particularly compatibile with the DTs we currently have upstream. Add a parallel set of variant DTs for boards with up-to-date firmware, replacing the SCPI parts with their new SCMI equivalents. Link: https://lore.kernel.org/r/f3516815104f951a05fc0f799681f77d7968f6ac.1645125063.git.robin.murphy@arm.com Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2022-02-21MAINTAINERS: Specify IRC channel for Renesas ARM64 portSergey Shtylyov
The Renesas ARM ports do have their own IRC channel #renesas-soc (initially created on Freenode, then moved to Liberta.Chat). Hopefully, adding it to this file will attract more people... :-) Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Link: https://lore.kernel.org/r/6c08e98f-c7bb-9d95-5032-69022e43e39b@omp.ru Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-21MAINTAINERS: Specify IRC channel for Renesas ARM32 portSergey Shtylyov
The Renesas ARM ports do have their own IRC channel #renesas-soc (initially created on Freenode, then moved to Liberta.Chat). Hopefully, adding it to this file will attract more people... :-) Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru> Link: https://lore.kernel.org/r/2f108f63-0cf7-cc4c-462e-ec63736234cf@omp.ru Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-21arm64: dts: renesas: ulcb-kf: fix wrong commentNikita Yushchenko
Fix comment referencing salvator board, likely a copy-paste leftover. ulcb-kf.dtsi has nothing to do with salvator. Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com> Fixes: 80c07701d5918928 ("arm64: dts: renesas: ulcb-kf: add pcm3168 sound codec") Link: https://lore.kernel.org/r/20220216181003.114049-1-nikita.yoush@cogentembedded.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2022-02-21arm64: dts: meson: add support for OSMC Vero 4K+Christian Hewitt
The OSMC Vero 4K+ device is based on the Amlogic S905D (P230) reference design with the following specifications: - 2GB DDR4 RAM - 16GB eMMC - HDMI 2.1 video - S/PDIF optical output - AV output - 10/100/1000 Ethernet - AP6255 Wireless (802.11 a/b/g/n/ac, BT 4.2) - 2x USB 2.0 ports (1x OTG) - IR receiver (internal) - IR extender port (external) - 1x micro SD card slot - 1x Power LED (red) - 1x Reset button (in AV jack) Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Tested-by: Chad Wagner <wagnerch42@gmail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220211105311.30320-4-christianshewitt@gmail.com
2022-02-21dt-bindings: arm: amlogic: add Vero 4K+ bindingsChristian Hewitt
Add the board binding for the OSMC Vero 4K+ STB device Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220211105311.30320-3-christianshewitt@gmail.com
2022-02-21dt-bindings: vendor-prefixes: add osmc prefixChristian Hewitt
Open Source Media Centre (Sam Nazarko Trading Ltd.) are a manufacturer of Linux Set-Top Box devices. Signed-off-by: Christian Hewitt <christianshewitt@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20220211105311.30320-2-christianshewitt@gmail.com
2022-02-21arm64: dts: imx8mp-phycore-som: Set usdhc root clock for eMMCJonas Kuenstler
Set the usdhc root clock to 400MHz to be able to support HS400/HS400ES modes for eMMC on phyCORE-i.MX8MP SoM. Signed-off-by: Jonas Kuenstler <j.kuenstler@phytec.de> Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-phycore-som: LDO5 needs to be enabled instead of LDO4Teresa Remmet
LDO4 is not connected so disable it. And LDO5 is used for VSEL of the NVCC_SD2 SD-Card bus. Having it disabled seems not to have an impact on the functionality. We enable it, as it is used. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-phycore-som: Set VDD_ARM run and standby voltageTeresa Remmet
Add bindings for VDD_ARM (BUCK2) run and standby voltage. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-phycore-som: Update WDOG muxingTeresa Remmet
To be able to trigger a reset also from an external source we need to configure the WDOG pin as open drain. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-phycore-som: Reduce drive strength for fec tx linesTeresa Remmet
Reduce drive strength on fec tx lines for signal quality improvements. Measurements showed that TD0 and TD1 require X4 and the other lines X2 for optimized settings. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-phycore-som: Adapt eMMC drive strengthTeresa Remmet
Set eMMC drive strength for USDHC3_DATA lines (200Mhz) to X4 for signal improvement. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-phycore-som: Set minimum output impedance for eth phyTeresa Remmet
To fit spec requirements set minimum output impedance for dp83867 ethernet phy. Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlay for imx219 rpi v2 cameraTim Harvey
Add support for the RaspberryPi Camera v2 which is an IMX219 8MP module: - https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf - has its own on-board 24MHz osc so no clock required from baseboard - pin 11 enables 1.8V and 2.8V LDO which is connected to GW73xx MIPI_GPIO4 (IMX8MM GPIO1_IO1) so we use this as a gpio Support is added via a device-tree overlay. The IMX219 supports RAW8/RAW10 image formats. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlay for imx219 rpi v2 cameraTim Harvey
Add support for the RaspberryPi Camera v2 which is an IMX219 8MP module: - https://datasheets.raspberrypi.com/camera/camera-v2-schematics.pdf - has its own on-board 24MHz osc so no clock required from baseboard - pin 11 enables 1.8V and 2.8V LDO which is connected to GW73xx MIPI_GPIO4 (IMX8MM GPIO1_IO1) so we use this as a gpio controlled regulator enable. Support is added via a device-tree overlay. The IMX219 supports RAW8/RAW10 image formats. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mm-venice-gw72xx-0x: add dt overlays for serial modesTim Harvey
The imx8mm-venice-gw72xx-0x som+baseboard combination has a multi-protocol RS-232/RS-485/RS-422 transceiver to an off-board connector which can be configured in a number of ways via UART and GPIO configuration. The default configuration per the imx8mm-venice-gw72xx-0x dts is for UART2 TX/RX and UART4 TX/RX to be available as RS-232: J15.1 UART2 TX out J15.2 UART2 RX in J15.3 UART4 TX out J15.4 UART4 RX in J15.5 GND Add dt overlays to allow additional the modes of operation: rs232-rts (UART2 RS-232 with RTS/CTS hardware flow control) J15.1 TX out J15.2 RX in J15.3 RTS out J15.4 CTS in J15.5 GND rs485 (UART2 RS-485 half duplex) J15.1 TXRX- J15.2 N/C J15.3 TXRX+ J15.4 N/C J15.5 GND rs422 (UART2 RS-422 full duplex) J15.1 TX- J15.2 RX+ J15.3 TX+ J15.4 RX- J15.5 GND Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mm-venice-gw73xx-0x: add dt overlays for serial modesTim Harvey
The imx8mm-venice-gw73xx-0x som+baseboard combination has a multi-protocol RS-232/RS-485/RS-422 transceiver to an off-board connector which can be configured in a number of ways via UART and GPIO configuration. The default configuration per the imx8mm-venice-gw73xx-0x dts is for UART2 TX/RX and UART4 TX/RX to be available as RS-232: J15.1 UART2 TX out J15.2 UART2 RX in J15.3 UART4 TX out J15.4 UART4 RX in J15.5 GND Add dt overlays to allow additional the modes of operation: rs232-rts (UART2 RS-232 with RTS/CTS hardware flow control) J15.1 TX out J15.2 RX in J15.3 RTS out J15.4 CTS in J15.5 GND rs485 (UART2 RS-485 half duplex) J15.1 TXRX- J15.2 N/C J15.3 TXRX+ J15.4 N/C J15.5 GND rs422 (UART2 RS-422 full duplex) J15.1 TX- J15.2 RX+ J15.3 TX+ J15.4 RX- J15.5 GND Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21dt-bindings: arm: imx: add imx8mm gw7903 supportTim Harvey
The GW7903 is based on the i.MX 8M Mini SoC featuring: - LPDDR4 DRAM - eMMC FLASH - microSD connector with UHS support - LIS2DE12 3-axis accelerometer - Gateworks System Controller - IMX8M FEC - software selectable RS232/RS485/RS422 serial transceiver - PMIC - 2x off-board bi-directional opto-isolated digital I/O - 1x M.2 A-E Key Socket and 1x MiniPCIe socket with USB2.0 and PCIe (resistor loading to route PCIe/USB2 between M.2 and MiniPCIe socket) Signed-off-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx: Add i.mx8mm Gateworks gw7903 dts supportTim Harvey
The GW7903 is based on the i.MX 8M Mini SoC featuring: - LPDDR4 DRAM - eMMC FLASH - microSD connector with UHS support - LIS2DE12 3-axis accelerometer - Gateworks System Controller - IMX8M FEC - software selectable RS232/RS485/RS422 serial transceiver - PMIC - 2x off-board bi-directional opto-isolated digital I/O - 1x M.2 A-E Key Socket and 1x MiniPCIe socket with USB2.0 and PCIe (resistor loading to route PCIe/USB2 between M.2 and MiniPCIe socket) Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: ls1028a: add efuse nodeMichael Walle
Layerscape SoCs contain a Security Fuse Processor which is basically a efuse controller. Add the node, so userspace can read the efuses. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-evk: add support for I2C5Hugo Villeneuve
Add support for i2c5, which is used to access the external I2C bus on connector J22 of the imx8mp-evk. Limit the speed to 100kHz since this is an external I2C bus. Disabled by default, since it is shared with the CAN1 bus. To enable i2c5, you need to disable the CAN1 function, enable the i2c5 function and also configure the CAN1/I2C5_SEL GPIO to HIGH to select i2c5 instead of CAN1. This can be done by defining a gpio-hog inside the pca6416 node, in your board device tree, like in this example: &flexcan1 { status = "disabled"; }; &i2c5 { status = "okay"; }; &pca6416 { can1-i2c5-sel-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_HIGH>; output-high; line-name = "can1-i2c5-sel"; }; }; Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8mp-evk: add PCA6416 gpio line namesHugo Villeneuve
Add gpio-line-names for the various GPIO's connected to the PCA6416 I/O expander on the imx8mp EVK. This helps when using the new gpiod interface to find the GPIOs by name. Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8qm: added more serial alias to dtsOliver Graute
Add more serial alias to imx8qm.dtsi file Cc: Rob Herring <robh+dt@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21arm64: dts: imx8qm: add compatible string for usdhc3Oliver Graute
add compatible string for usdhc3 Cc: Rob Herring <robh+dt@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Fabio Estevam <festevam@gmail.com> Cc: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2022-02-21MAINTAINERS: ARM/WPCM450: Add 'W:' line with wikiJonathan Neuschäfer
The wiki is a useful source of 3rd-party information about the SoC, mostly hardware documentation. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20220218160834.320200-1-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2022-02-19arm64: dts: rockchip: fix supplies for pwm regulatorsHeiko Stuebner
The supply-name for pwm-regualators is "pwm", so the property needs to be pwm-supply, not vin-supply as in a number of boards. In all cases changed here, the supplying regulator is always an always-on fixed-regulator, so there will be no functional change and only a change in the regulator hirarchy, as can be seen for example in the regulator-summary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20211227234529.1970281-2-heiko@sntech.de
2022-02-19arm64: dts: rockchip: define vdd_log on rk3399-pumaHeiko Stuebner
vdd_log supplied a lot of the logic parts of the soc and is supplied through pwm2. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20211227234529.1970281-1-heiko@sntech.de
2022-02-18ARM: dts: am335x-sancloud-bbe-extended-wifi: New devicetreePaul Barker
Add support for the SanCloud BBE Extended WiFi board which shares common hardware with other BBE varients. Compared to the vanilla BBE, this particular model: * adds a WiFi+Bluetooth module connected via SDIO and UART. * drops the HDMI encoder, barometer and accelerometer. Signed-off-by: Paul Barker <paul.barker@sancloud.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-02-18ARM: dts: logicpd-torpedo: Add isp1763 support to baseboardAdam Ford
The baseboard has an ISP1763 USB controller acting as a host. Since the pinmuxing for the corresponding IRQ is different between OMAP35 and DM37, the pinmux has been placed in the kit-level files, while the common code is placed into the baseboard file. Signed-off-by: Adam Ford <aford173@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-02-18ARM: dts: am334x: pdu001: Use correct node name for RTCThierry Reding
RTC devices should be named "rtc" according to the standard RTC device tree schema. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2022-02-16ARM: mstar: Extend opp_table for infinity2mRomain Perier
infinity2m are running up to 1.2Ghz, this extends opp_table with the corresponding frequencies and enable operating-points table for cpu1 Signed-off-by: Romain Perier <romain.perier@gmail.com>
2022-02-16ARM: mstar: Add OPP table for infinity3Daniel Palmer
The infinity3 has a slightly higher max frequency compared to the infinity so extend the OPP table. Co-authored-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Daniel Palmer <daniel@0x0f.com> Reviewed-by: Romain Perier <romain.perier@gmail.com>
2022-02-16ARM: mstar: Add OPP table for infinityDaniel Palmer
Add an OPP table for the inifinity chips so that cpu frequency scaling can happen. Co-authored-by: Willy Tarreau <w@1wt.eu> Signed-off-by: Daniel Palmer <daniel@0x0f.com> Reviewed-by: Romain Perier <romain.perier@gmail.com>
2022-02-16ARM: mstar: Link cpupll to second coreDaniel Palmer
The second core also sources it's clock from the CPU PLL. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Reviewed-by: Romain Perier <romain.perier@gmail.com>
2022-02-16ARM: mstar: Link cpupll to cpuDaniel Palmer
The CPU clock is sourced from the CPU PLL. Link cpupll to the cpu so that frequency scaling can happen. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Reviewed-by: Romain Perier <romain.perier@gmail.com>
2022-02-16ARM: mstar: Add cpupll to base dtsiDaniel Palmer
All MStar/SigmaStar ARMv7 SoCs have the CPU PLL at the same place so add it to the base dtsi. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Reviewed-by: Romain Perier <romain.perier@gmail.com>
2022-02-16dt-bindings: clk: mstar msc313 cpupll binding descriptionDaniel Palmer
Add a binding description for the MStar/SigmaStar CPU PLL block. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Reviewed-by: Rob Herring <robh@kernel.org>
2022-02-15ARM: dts: sti: move usb picophy nodes out of soc in stih418.dtsiAlain Volmat
Move the usb2_picophy1 and usb2_picophy2 nodes out of the soc section. Since they are controlled via syscfg, there is no reg property needed, which is required when having the node within the soc section. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-02-15ARM: dts: sti: move usb picophy nodes out of soc in stih410.dtsiAlain Volmat
Move the usb2_picophy1 and usb2_picophy2 nodes out of the soc section. Since they are controlled via syscfg, there is no reg property needed, which is required when having the node within the soc section. Modification is done within stih410.dtsi and within related board dts files (stih410-b2120.dts, stih410-b2260.dts). Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-02-15ARM: dts: sti: remove delta node from stih410.dtsiAlain Volmat
The delta0 node within stih410.dtsi is identical to the one already written within stih407-family.dtsi and included within stih410.dtsi. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-02-15ARM: dts: sti: move some nodes out of the soc section in stih407-family.dtsiAlain Volmat
Move all nodes without reg property out of the soc section of stih407-family.dtsi and DT including stih407-family.dtsi. This avoid to set a <0> reg property. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-02-15ARM: dts: sti: ensure unique unit-address in stih418-clockAlain Volmat
Move quadfs and a9-mux clocks nodes into clockgen nodes so that they can get the reg property from the parent node and ensure only one node has the address. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-02-15ARM: dts: sti: ensure unique unit-address in stih410-clockAlain Volmat
Move quadfs and a9-mux clocks nodes into clockgen nodes so that they can get the reg property from the parent node and ensure only one node has the address. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-02-15ARM: dts: sti: ensure unique unit-address in stih407-clockAlain Volmat
Move quadfs and a9-mux clocks nodes into clockgen nodes so that they can get the reg property from the parent node and ensure only one node has the address. Signed-off-by: Alain Volmat <avolmat@me.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-02-15ARM: dts: rockchip: remove status from rk3288 crypto nodeJohan Jonker
A node that is not disabled is standard already "okay", so remove status from rk3288 crypto node. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Link: https://lore.kernel.org/r/20220213212319.8448-1-jbx6244@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-02-15ARM: dts: wpcm450: Add pinmux information to UART0Jonathan Neuschäfer
UART0 always uses the same pins, so lets add the pinctrl information to the common devicetree for WPCM450. UART1 has different connection options, so I'm not adding the pinctrl properties there. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Link: https://lore.kernel.org/r/20220129115228.2257310-10-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
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