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2021-03-12arm64: dts: qcom: pmk8350: Add base dts fileVinod Koul
Add base DTS file for PMK8350 along with GPIO node Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312052737.3558801-3-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-12arm64: dts: qcom: sm8350: Add spmi nodeVinod Koul
Add SPMI node found in SM8350 SoC Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312052737.3558801-2-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: db845c: fix correct powerdown pin for WSA881xSrinivas Kandagatla
WSA881x powerdown pin is connected to GPIO1 not gpio2, so correct this. This was working so far due to a shift bug in gpio driver, however once that is fixed this will stop working, so fix this! Fixes: 89a32a4e769cc ("arm64: dts: qcom: db845c: add analog audio support") Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20210309102025.28405-1-srinivas.kandagatla@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11dt-bindings: arm: qcom: Add SM8350 HDKBjorn Andersson
Document the SM8350 Hardware Development Kit (HDK). Reviewed-by: Vinod Koul <vkoul@kernel.org> Reported-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210310035710.2816699-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sc7180: Drop duplicate dp_hot_plug_det node in trogdorStephen Boyd
This moved from being trogdor specific to being part of the general sc7180.dtsi SoC file in commit 681a607ad21a ("arm64: dts: qcom: sc7180: Add DisplayPort HPD pin dt node"). Then we dropped the pinconf from the general sc7180.dtsi file in commit 8d079bf20410 ("arm64: dts: qcom: sc7180: Drop pinconf on dp_hot_plug_det") and added it back to the trogdor dts file in commit f772081f4883 ("arm64: dts: qcom: sc7180: Add "dp_hot_plug_det" pinconf for trogdor"). As part of this we managed to forget to drop the old copy in the trogdor dts. Let's do it now. Signed-off-by: Stephen Boyd <swboyd@chromium.org> [dianders: updated desc] Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210311131008.1.I85fc8146c0ee47e261faa0c54dd621467b81952d@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sm8350: fix number of pins in 'gpio-ranges'Shawn Guo
The last cell of 'gpio-ranges' should be number of GPIO pins, and in case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather than msm_pinctrl_soc_data.ngpio - 1. This fixes the problem that when the last GPIO pin in the range is configured with the following call sequence, it always fails with -EPROBE_DEFER. pinctrl_gpio_set_config() pinctrl_get_device_gpio_range() pinctrl_match_gpio_range() Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC") Cc: Vinod Koul <vkoul@kernel.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210303033106.549-5-shawn.guo@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sm8250: fix number of pins in 'gpio-ranges'Shawn Guo
The last cell of 'gpio-ranges' should be number of GPIO pins, and in case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather than msm_pinctrl_soc_data.ngpio - 1. This fixes the problem that when the last GPIO pin in the range is configured with the following call sequence, it always fails with -EPROBE_DEFER. pinctrl_gpio_set_config() pinctrl_get_device_gpio_range() pinctrl_match_gpio_range() Fixes: 16951b490b20 ("arm64: dts: qcom: sm8250: Add TLMM pinctrl node") Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210303033106.549-4-shawn.guo@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sm8150: fix number of pins in 'gpio-ranges'Shawn Guo
The last cell of 'gpio-ranges' should be number of GPIO pins, and in case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather than msm_pinctrl_soc_data.ngpio - 1. This fixes the problem that when the last GPIO pin in the range is configured with the following call sequence, it always fails with -EPROBE_DEFER. pinctrl_gpio_set_config() pinctrl_get_device_gpio_range() pinctrl_match_gpio_range() Fixes: e13c6d144fa0 ("arm64: dts: qcom: sm8150: Add base dts file") Cc: Vinod Koul <vkoul@kernel.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210303033106.549-3-shawn.guo@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sdm845: fix number of pins in 'gpio-ranges'Shawn Guo
The last cell of 'gpio-ranges' should be number of GPIO pins, and in case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather than msm_pinctrl_soc_data.ngpio - 1. This fixes the problem that when the last GPIO pin in the range is configured with the following call sequence, it always fails with -EPROBE_DEFER. pinctrl_gpio_set_config() pinctrl_get_device_gpio_range() pinctrl_match_gpio_range() Fixes: bc2c806293c6 ("arm64: dts: qcom: sdm845: Add gpio-ranges to TLMM node") Cc: Evan Green <evgreen@chromium.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210303033106.549-2-shawn.guo@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sc7280: Add rpmh power-domain nodeRajendra Nayak
Add the DT node for the rpmhpd power controller on SC7280 SoCs. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1615461961-17716-15-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sc7280: Add cpuidle statesMaulik Shah
Add cpuidle states for little and big cpus. The latency values are preliminary placeholders and will be updated once testing provides the real numbers. Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1615461961-17716-14-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280satya priya
Add SPMI PMIC arbiter device to communicate with PMICs attached to SPMI bus. Signed-off-by: satya priya <skakit@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1615461961-17716-13-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sc7280: Add APSS watchdog nodeSai Prakash Ranjan
Add APSS (Application Processor Subsystem) watchdog DT node for SC7280 SoC. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1615461961-17716-12-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sc7280: Add reserved memory for fwMaulik Shah
Add fw reserved memory area for CPUCP (CPUSS control processor) and AOP (Always ON processor) Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1615461961-17716-10-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sc7280: Add device node for APPS SMMUSai Prakash Ranjan
Adding device node for APPS SMMU available on SC7280 chipset. This is shared among the multiple client devices such as display, video, usb, mmc and others. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1615461961-17716-9-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: SC7280: Add rpmhcc clock controller nodeRajendra Nayak
Add rpmhcc clock controller node for SC7280. Also add references to rpmhcc clocks in gcc. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1615461961-17716-7-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sc7280: Add RSC and PDC devicesMaulik Shah
Add PDC interrupt controller along with apps RSC device. Also add reserved memory for command_db. Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1615461961-17716-6-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sc7280: Add basic dts/dtsi files for sc7280 socRajendra Nayak
Add initial device tree support for the sc7280 SoC and the IDP boards based on this SoC Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1615461961-17716-4-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11dt-bindings: arm: qcom: Document sc7280 SoC and boardRajendra Nayak
Document the sc7280 SoC and the IDP board bindings Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1615461961-17716-2-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: Introduce SM8350 HDKBjorn Andersson
Add initial DTS for the Snapdragon 888 Mobile Hardware Development Kit, aka SM8350 HDK. This initial version describes debug UART, UFS storage, the three USB connectors and remoteprocs. Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210308182113.1284966-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11dt-bindings: arm: qcom: Document sony boards for apq8094Vinod Koul
Document the various sony boards for apq8094. These are used in various sony dts files but not documented Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210308060826.3074234-6-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: msm8994: don't use empty memory nodeVinod Koul
We expect bootloader to full memory details but passing empty values gives warning, so add a default value arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 0, 0, 0]]} Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210308060826.3074234-5-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11dt-bindings: arm: qcom: Document ipq6018-cp01 boardVinod Koul
Document the ipq6018-cp01 board. It was missing leading to warning: arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml: /: compatible: 'oneOf' conditional failed, one must be fixed: ['qcom,ipq6018-cp01', 'qcom,ipq6018'] is too short ['qcom,ipq6018-cp01', 'qcom,ipq6018'] is too long Additional items are not allowed ('qcom,ipq6018' was unexpected) Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210308060826.3074234-4-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: msm8916: don't use empty memory nodeVinod Koul
We expect bootloader to full memory details but passing empty values gives warning, so add a default value arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 0, 0, 0]]} Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210308060826.3074234-3-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: apq8016-sbc: drop qcom,sbcVinod Koul
apq8016-sbc is one of the compaitibles for this board, but is not documented, so drop it. This fixes these two warns: arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible: ['qcom,apq8016-sbc', 'qcom,apq8016', 'qcom,sbc'] is not valid under any of the given schemas (Possible causes of the failure): arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible: ['qcom,apq8016-sbc', 'qcom,apq8016', 'qcom,sbc'] is too long arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible:0: 'qcom,apq8016-sbc' is not one of ['qcom,apq8064-cm-qs600', 'qcom,apq8064-ifc6410'] arch/arm64/boot/dts/qcom/apq8016-sbc.dt.yaml: /: compatible:0: 'qcom,apq8016-sbc' is not one of ['qcom,apq8074-dragonboard'] Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210308060826.3074234-2-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sc7180: Avoid glitching SPI CS at bootup on trogdorDouglas Anderson
At boot time the following happens: 1. Device core gets ready to probe our SPI driver. 2. Device core applies SPI controller's "default" pinctrl. 3. Device core calls the SPI driver's probe() function which will eventually setup the chip select GPIO as "unasserted". Thinking about the above, we can find: a) For SPI devices that the BIOS inits (Cr50 and EC), the BIOS would have had them configured as "GENI" pins and not as "GPIO" pins. b) It turns out that our BIOS also happens to init these pins as "output" (even though it doesn't need to since they're not muxed as GPIO) but leaves them at the default state of "low". c) As soon as we apply the "default" chip select it'll switch the function to GPIO and stop driving the chip select high (which is how "GENI" was driving it) and start driving it low. d) As of commit 9378f46040be ("UPSTREAM: spi: spi-geni-qcom: Use the new method of gpio CS control"), when the SPI core inits things it inits the GPIO to be "deasserted". Prior to that commit the GPIO was left untouched until first use. e) When the first transaction happens we'll assert the chip select and then deassert it after done. So before the commit to change us to use gpio descriptors we used to have a _really long_ assertion of chip select before our first transaction (because it got pulled down and then the first "assert" was a no-op). That wasn't great but (apparently) didn't cause any real harm. After the commit to change us to use gpio descriptors we end up glitching the chip select line during probe. It would go low and then high with no data transferred. The other side ought to be robust against this, but it certainly could cause some confusion. It's known to at least cause an error message on the EC console and it's believed that, under certain timing conditions, it could be getting the EC into a confused state causing the EC driver to fail to probe. Let's fix things to avoid the glitch. We'll add an extra pinctrl entry that sets the value of the pin to output high (CS deasserted) before doing anything else. We'll do this in its own pinctrl node that comes before the normal pinctrl entries to ensure that the order is correct and that this gets applied before the mux change. This change is in the trogdor board file rather than in the SoC dtsi file because chip select polarity can be different depending on what's hooked up and it doesn't feel worth it to spam the SoC dtsi file with both options. The board file would need to pick the right one anyway. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Fixes: cfbb97fde694 ("arm64: dts: qcom: Switch sc7180-trogdor to control SPI CS via GPIO") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210218145456.1.I1da01a075dd86e005152f993b2d5d82dd9686238@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sc7180: Use pdc interrupts for USB instead of GIC interruptsSandeep Maheswaram
Using pdc interrupts for USB instead of GIC interrupts to support wake up in case xo shutdown. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Link: https://lore.kernel.org/r/1594235417-23066-4-git-send-email-sanm@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: Add sc7180-trogdor-coachz skusDouglas Anderson
This is a trogdor variant. This is mostly a grab from the downstream tree with notable exceptions: - I skip -rev0. This was a super early build and there's no advantage of long term support. - I remove sound node since sound hasn't landed upstream yet. Cc: Gwendal Grignou <gwendal@chromium.org> Cc: Matthias Kaehlcke <mka@chromium.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Tzung-Bi Shih <tzungbi@chromium.org> Cc: Judy Hsiao <judyhsiao@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.13.I3d1f5f8a3bf31e8014229df0d4cfdff20e9cc90f@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: Add sc7180-trogdor-pompom skusDouglas Anderson
This is a trogdor variant. This is mostly a grab from the downstream tree with notable exceptions: - I skip -rev0. This was a super early build and there's no advantage of long term support. - In -rev1 I translate the handling of the USB hub like is done for similar boards. See the difference between the downstream and upstream 'sc7180-trogdor-lazor-r0.dts' for an example. This will need to be resolved when proper support for the USB hub is figured out upstream. - I remove sound node since sound hasn't landed upstream yet. - In incorporate the pending <https://crrev.com/c/2719075> for the keyboard. Cc: Philip Chen <philipchen@google.com> Cc: Matthias Kaehlcke <mka@chromium.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Tzung-Bi Shih <tzungbi@chromium.org> Cc: Judy Hsiao <judyhsiao@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.12.If93a01b30d20dccacbad4be8ddc519dc20a51a1e@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: Add sc7180-lazor-limozeen skusDouglas Anderson
This is a SKU variant of lazor. Add it. This squashes the downstream patches to support this hardware. NOTES: - The non-touch SKU actually has "innolux,n116bca-ea1" but that driver is still pending in simple-panel. The bindings have been Acked though [1]. Things work well enough with the "innolux,n116bge" timings for now, though. - The wonky special dts just for "-rev4" arguably doesn't need to go upstream since they weren't widely distributed, but since a few people have them we might as well. If it ever causes problems we can delete it. [1] https://lore.kernel.org/r/20210115144345.v2.4.I6889e21811df6adaff5c5b8a8c80fda0669ab3a5@changeid Cc: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.11.I556326b24441e22c8c429ce383cc157c7aaef44b@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sc7180: Set up lazor r3+ as sc7180-lite SKUsMatthias Kaehlcke
Lazor rev3 and later use the 'lite' version of the SC7180 SoC. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Cc: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Matthias Kaehlcke <mka@chromium.org> [dianders: Adjust commit message which referred to downstream history] Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.10.Ia3795e192f5bbe17e6714e45fcb0bf5acdbd4c17@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sc7180: add GO_LAZOR variant property for lazorAbhishek Kumar
For trogdor, in the latest board-2.bin file, new BDF with variant name GO_LAZOR has been introduced, so we need this property set, for GO_LAZOR BDF to be picked. Cc: Philip Chen <philipchen@chromium.org> Signed-off-by: Abhishek Kumar <kuabhs@chromium.org> [dianders: adjusted subject line and sort order] Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.9.I4a38fe64dd79c54af80d7e4ef5940f8cf4f86e75@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sc7180: Remove clock for bluetooth on TrogdorVenkata Lakshmi Narayana Gubba
Removed voting for RPMH_RF_CLK2 which is not required as it is getting managed by BT SoC through SW_CTRL line. Cc: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Venkata Lakshmi Narayana Gubba <gubbaven@codeaurora.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.8.I80c268f163e6d49a70af1238be442b5de400c579@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sc7180-trogdor: Remove fp control pins in prep for coachzAlexandru M Stan
Removed the pinctrl and pin{mux,conf} for the control pins because: 1. The only need for them is for userspace control via flash_fp_mcu 2. cros-ec doesn't know what to do with them, and even if it did, it would interfere with flash_fp_mcu at the most inopportune times Since we're not using hogs, we rely on AP firmware to set all the control pins correctly. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Craig Hesling <hesling@chromium.org> Signed-off-by: Alexandru M Stan <amstan@chromium.org> [dianders: adjusted since coachz isn't upstream yet] Reviewed-by; Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.7.Ifd7b86f826b18410eada75758a7bca1eebfa336d@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: Disable camera clk on sc7180-trogdor devices by defaultStephen Boyd
We only want to use this clk driver on CoachZ devices. Disable it for all other Trogdor boards. NOTE: CoachZ devices aren't yet supported upstream so until it is this is just disabled for all trogdor. Cc: Tomasz Figa <tfiga@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> [dianders:adjusted since no coachz upstream yet] Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.6.I22522b0c9db505ee43ed08e8d5d9e8fe632e7447@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: trogdor: Only wakeup from pen ejectStephen Boyd
Configure the pen to be a wakeup source only when the pen is ejected instead of both when the pen is ejected and inserted. This corresponds to wake source requirements. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.5.Ib9672bfbe639c96c85408d6f0217a2609eb0b70f@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: Unify the sc7180-trogdor panel nodesDouglas Anderson
Let's avoid a bit of duplication by pushing this up to the trogdor.dtsi file. Suggested-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.4.I1483fac4c5ae4b2d7660290ff85d69945292618f@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: Prep sc7180-trogdor trackpad IRQ for new boardsDouglas Anderson
The trackpad interrupt got renamed and also moved to a new GPIO on newer boards. Let's do the move in the "trogdor.dtsi" file and then undo it in the two old boards. NOTE: since none of the new boards have device trees yet, this change looks silly on its own but it will make sense after more boards are supported. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.3.Iddf6dc8102aa4fbc3847936226fc7bf2e2cd315c@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: Move sc7180 MI2S config to board files and make pulldownDouglas Anderson
In general pinconf belongs in board files, not SoC files. Move it to the only current user (trogdor). Also adjust the drive strengths and pulls. Cc: V Sujith Kumar Reddy <vsujithk@codeaurora.org> Cc: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Cc: Tzung-Bi Shih <tzungbi@chromium.org> Cc: Judy Hsiao <judyhsiao@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.2.Id27e7e6f90c29bf623fa4880e18a14ba1dffd2d2@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sc7180: Update dts for DP phy inside QMP phyStephen Boyd
Drop the old node and add the new one in its place. Cc: Stephen Boyd <swboyd@chromium.org> Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Rob Clark <robdclark@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> [dianders: Adjusted due to DP not itself not in upstream dts yet] Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210301133318.v2.1.Iad06142ceb8426ce5492737bf3d9162ed0dd2b55@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sm8350: Add cpufreq nodeVinod Koul
Add cpufreq node and reference it for the CPUs. Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210216111703.1838663-1-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sm8350: Use enums for GCCVinod Koul
Now that we have GCC define, use the enums instead of numbers in the DTS Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210212115532.1339942-8-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sm8350-mtp: Enable remoteprocsVinod Koul
This enabled the four remoteprocs found in SM8350, audio, compute, modem and sensor for MTP platform and adds firmware for them. Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210212115532.1339942-7-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sm8350: Add remoteprocsVinod Koul
Add remoteproc nodes for the audio, compute and sensor cores, define glink for each one. Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210212115532.1339942-6-vkoul@kernel.org [bjorn: Replaced rpmhpd defines with constants, for now] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sm8350: Add SMP2P nodesVinod Koul
SMP2P is used for interrupting and being interrupted about remoteproc state changes related to the audio, compute, modem and sensor subsystems. Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210212115532.1339942-5-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sm8350: Add rmtfs nodeVinod Koul
Add the rmtfs as a reserved memory node. Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210212115532.1339942-4-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sm8350: Add rpmhpd nodeVinod Koul
This adds RPMH power domain found in SM8350 SoC Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210212115532.1339942-3-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sm8350: fix typoVinod Koul
Fix the typo s/Limaited/Limited Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210212115532.1339942-2-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sm8350-mtp: add regulator namesVinod Koul
Add the property "regulator-names" to the regulators as given in schematics so that it is easier to understand the regulators being used Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210204170907.63545-7-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
2021-03-11arm64: dts: qcom: sm8350-mtp: enable UFS nodesVinod Koul
Enabled the UFS node found in SM8350-MTP platform, also add the regulators associated with UFS HC and UFS phy to these nodes. Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210204170907.63545-6-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
generated by cgit (git 2.34.1) at 2025-07-15 22:00:04 +0000