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2024-08-30arm64: dts: qcom: Add X1E78100 ThinkPad T14s Gen 6Konrad Dybcio
Add support for the aforementioned laptop. That includes: - input methods, incl. lid switch (keyboard needs the pdc wakeup-parent removal hack..) - NVMe, WiFi - USB-C ports - GPU, display - DSPs Notably, the USB-A ports on the side are depenedent on the USB multiport controller making it upstream. At least one of the eDP panels used (non-touchscreen) identifies as BOE 0x0b66. See below for the hardware description from the OEM. Link: https://www.lenovo.com/us/en/p/laptops/thinkpad/thinkpadt/lenovo-thinkpad-t14s-gen-6-(14-inch-snapdragon)/len101t0099 Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240828-topic-t14s_upstream-v2-2-49faea18de84@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-30dt-bindings: arm: qcom: Add Lenovo ThinkPad T14s Gen 6Konrad Dybcio
Document the X1E78100-based ThinkPad. X1E78100 is a binned version of X1E80100, hence use the latter's compatible string as fallback. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240828-topic-t14s_upstream-v2-1-49faea18de84@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-30Revert "arm64: dts: qcom: msm8939-longcheer-l9100: Add rear flash"André Apitzsch
Patch "arm64: dts: qcom: msm8939-longcheer-l9100: Add rear flash" has been applied twice. This reverts the older version of the patch. Revert the commit f98bdb21cfc9 ("arm64: dts: qcom: msm8939-longcheer-l9100: Add rear flash") Fixes: f98bdb21cfc9 ("arm64: dts: qcom: msm8939-longcheer-l9100: Add rear flash") Signed-off-by: André Apitzsch <git@apitzsch.eu> Link: https://lore.kernel.org/r/20240830-revert_flash-v1-1-ad7057ea7e6e@apitzsch.eu Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-26arm64: dts: qcom: Add support for X1-based Surface Laptop 7 devicesKonrad Dybcio
Add support for Surface Laptop 7 machines, based on X1E80100. The feature status is mostly on par with other X Elite machines, notably lacking: - USB-A and probably USB-over-Surface-connector (pending NXP retimer support) - SD card reader (Realtek RTS5261 connected over PCIe) - Touchscreen and touchpad support (hid-over-SPI [1]) - Audio (a quick look suggests the setup is very close to the one in X1E CRD) The two Surface Laptop 7 SKUs (13.8" and 15") only have very minor differences, amounting close to none on the software side. Even the MBN firmware files and ACPI tables are shared between the two machines. With that in mind, support is added for both, although only the larger one was physically tested. Display differences will be taken care of through fused-in EDID and other matters should be solved within the EC and boot firmware. [1] https://www.microsoft.com/en-us/download/details.aspx?id=103325 Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Link: https://lore.kernel.org/r/20240826-topic-sl7-v2-5-c32ebae78789@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-26arm64: dts: qcom: x1e80100: Add UART2Konrad Dybcio
GENI SE2 within QUP0 is used as UART on some devices, describe it. While at it, rewrite the adjacent UART21 pins node to make it more easily modifiable. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Link: https://lore.kernel.org/r/20240826-topic-sl7-v2-4-c32ebae78789@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-26arm64: dts: qcom: x1e80100-pmics: Add PMC8380C PWMKonrad Dybcio
The PMC8380C (PM8550) has a PWM block, describe it. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Link: https://lore.kernel.org/r/20240826-topic-sl7-v2-3-c32ebae78789@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-26dt-bindings: arm: qcom: Add Surface Laptop 7 devicesKonrad Dybcio
Document the X1E80100-based Microsoft laptops. Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240826-topic-sl7-v2-1-c32ebae78789@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-21arm64: dts: qcom: sm8150-mtp: drop incorrect amd,imageonKrzysztof Kozlowski
The SM8150 MTP board does not have magically different GPU than the SM8150, so it cannot use amd,imageon compatible, also pointed by dtbs_check: sm8150-mtp.dtb: gpu@2c00000: compatible: 'oneOf' conditional failed, one must be fixed: ['qcom,adreno-640.1', 'qcom,adreno', 'amd,imageon'] is too long 'qcom,adreno-640.1' does not match '^qcom,adreno-[0-9a-f]{8}$' 'qcom,adreno-640.1' does not match '^amd,imageon-200\\.[0-1]$' 'amd,imageon' was expected The incorrect amd,imageon compatible was added in commit f30ac26def18 ("arm64: dts: qcom: add sm8150 GPU nodes") to the SM8150 and later moved to the SM8150 MTP board in commit 1642ab96efa4 ("arm64: dts: qcom: sm8150: Don't start Adreno in headless mode") with an intention to allow headless mode. This should be solved via proper driver quirks, not fake compatibles. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240821140116.436441-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-20arm64: qcom: sa8775p: Add ADSP and CDSP0 fastrpc nodesLing Xu
Add ADSP and CDSP0 fastrpc nodes. Signed-off-by: Ling Xu <quic_lxu5@quicinc.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20240819045052.2405511-1-quic_lxu5@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-20arm64: dts: qcom: x1e80100: Add USB Multiport controllerKonrad Dybcio
X1E80100 has a multiport controller with 2 HS (eUSB) and 2 SS PHYs attached to it. It's commonly used for USB-A ports and internally routed devices. Configure it to support such functionality. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240820-topic-h_mp-v2-2-d88518066372@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-16arm64: dts: qcom: sa8775p: fix the fastrpc labelBartosz Golaszewski
The fastrpc driver uses the label to determine the domain ID and create the device nodes. It should be "cdsp1" as this is the engine we use here. Fixes: df54dcb34ff2 ("arm64: dts: qcom: sa8775p: add ADSP, CDSP and GPDSP nodes") Reported-by: Ekansh Gupta <quic_ekangupt@quicinc.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240816102345.16481-2-brgl@bgdev.pl Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15arm64: dts: qcom: ipq5332: Add icc provider ability to gccVaradarajan Narayanan
IPQ SoCs dont involve RPM in managing NoC related clocks and there is no NoC scaling. Linux itself handles these clocks. However, these should not be exposed as just clocks and align with other Qualcomm SoCs that handle these clocks from a interconnect provider. Hence include icc provider capability to the gcc node so that peripherals can use the interconnect facility to enable these clocks. Change USB to use the icc-clk framework for the iface clock. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20240730054817.1915652-6-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15Merge branch '20240730054817.1915652-2-quic_varada@quicinc.com' into ↵Bjorn Andersson
arm64-for-6.12 Merge IPQ5332 interconnect binding from the topic branch, to gain access to the interconnect path defines.
2024-08-15dt-bindings: interconnect: Add Qualcomm IPQ5332 supportVaradarajan Narayanan
Add interconnect-cells to clock provider so that it can be used as icc provider. Add master/slave ids for Qualcomm IPQ5332 Network-On-Chip interfaces. This will be used by the gcc-ipq5332 driver for providing interconnect services using the icc-clk framework. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20240730054817.1915652-2-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15arm64: dts: qcom: sm8250: move lpass codec macros to use clks directlySrinivas Kandagatla
Move lpass codecs va and wsa macros to use the clks directly from AFE clock controller instead of going via gfm mux like other codec macros and SoCs. This makes it more align with the other SoCs and codec macros in this SoC which take AFE clocks directly. This will also avoid an extra clk mux layer, provides consistency and avoids the buggy mux driver which will be removed. This should also fix RB5 audio. Remove the gfm mux drivers for both audiocc and aoncc. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20240815170542.20754-1-srinivas.kandagatla@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15arm64: dts: qcom: msm8998: Add disabled support for LPASS iommu for Q6AngeloGioacchino Del Regno
Add support for the LPASS (Q6) SMMU and keep it disabled as this is used only when the audio DSP is present and used, which is not mandatory to have. It is expected for board-specific device-trees to enable this node if supported. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr> Link: https://lore.kernel.org/r/20240814-lpass-v1-3-a5bb8f9dfa8b@freebox.fr [bjorn: s/iface/bus in clock-names, to match binding] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15Merge branch '20240814-lpass-v1-1-a5bb8f9dfa8b@freebox.fr' into arm64-for-6.12Bjorn Andersson
Merge MSM8998 GCC binding update, to get access to the newly introduced LPASS clock and GDSC constants.
2024-08-15dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitionsAngeloGioacchino Del Regno
Add definitions for the Q6 BIMC, LPASS core and adsp smmu clocks, required to enable audio functionality on MSM8998. Add the GDSC definitions for the LPASS_ADSP_GDSC and LPASS_CORE_GDSC as a final step to enable the required clock tree for the lpass iommu and for the audio dsp itself. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240814-lpass-v1-1-a5bb8f9dfa8b@freebox.fr Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: msm8976: Add restart nodeBarnabás Czémán
Add a pshold restart node what can be found in downstream for enable to perform restart operations. Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org> Link: https://lore.kernel.org/r/20240807-pshold-v1-1-0fa7927e99ce@mainlining.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: sa8775p: add CPU idle statesBartosz Golaszewski
Add CPU idle-state nodes and power-domains to the .dtsi for SA8775P. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20240807-sa8775p-idle-states-v1-1-f2b5fcdfa0b0@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: x1e80100-yoga: Update panel bindingsRob Clark
Use the correct panel compatible, and wire up enable-gpio. It is wired up in the same way as the x1e80100-crd. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Stephan Gerhold <stephan.gerhold@linaro.org> Link: https://lore.kernel.org/r/20240806202218.9060-1-robdclark@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: msm8916-samsung-gt58: Enable the touchkeysNikita Travkin
The tablet has two capacitive buttons on the scren bezel. Enable them by adding the keycodes in the dt. Signed-off-by: Nikita Travkin <nikita@trvn.ru> Link: https://lore.kernel.org/r/20240806-msm8916-gt58-tkey-v1-1-8987b06c5921@trvn.ru Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: sc8280xp-x13s: Enable RGB sensorBryan O'Donoghue
Enable the main RGB sensor on the Lenovo x13s a five megapixel 2 lane DPHY MIPI sensor connected to cisphy0. With the pm8008 patches recently applied to the x13s dtsi we can now also enable the RGB sensor. Once done we have all upstream support necessary for the RGB sensor on x13s. Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20240806-b4-linux-next-24-07-31-camss-sc8280xp-lenovo-rgb-v2-v3-1-199767fb193d@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: sa8775p-ride: enable remoteprocsBartosz Golaszewski
Enable all remoteproc nodes on the sa8775p-ride board and point to the appropriate firmware files. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20240805-topic-sa8775p-iot-remoteproc-v4-6-86affdc72c04@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: sa8775p: add ADSP, CDSP and GPDSP nodesTengfei Fan
Add nodes for remoteprocs: ADSP, CDSP0, CDSP1, GPDSP0 and GPDSP1 for SA8775p SoCs. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> [Ling: added the fastrcp nodes] Co-developed-by: Ling Xu <quic_lxu5@quicinc.com> Signed-off-by: Ling Xu <quic_lxu5@quicinc.com> [Bartosz: ported to mainline] Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20240805-topic-sa8775p-iot-remoteproc-v4-5-86affdc72c04@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14dt-bindings: mailbox: qcom-ipcc: Add GPDSP0 and GPDSP1 clientsTengfei Fan
Add GPDSP0 and GPDSP1 clients for SA8775p platform. Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20240805-topic-sa8775p-iot-remoteproc-v4-2-86affdc72c04@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: msm8916-samsung-j3ltetw: Add initial device treeLin, Meng-Bo
The dts and dtsi add support for msm8916 variant of Samsung Galaxy J3 SM-J320YZ smartphone released in 2016. Add a device tree for SM-J320YZ with initial support for: - GPIO keys - SDHCI (internal and external storage) - USB Device Mode - UART (on USB connector via the SM5703 MUIC) - WCNSS (WiFi/BT) - Regulators - QDSP6 audio - Speaker/earpiece/headphones/microphones via digital/analog codec in MSM8916/PM8916 - WWAN Internet via BAM-DMUX - Touchscreen - Accelerometer There are different variants of J3, with some differences in MUIC, sensor, NFC and touch key I2C buses. The common parts are shared in msm8916-samsung-j3-common.dtsi to reduce duplication. Signed-off-by: Lin, Meng-Bo <linmengbo06890@proton.me> Link: https://lore.kernel.org/r/20240804065854.42437-3-linmengbo06890@proton.me Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14dt-bindings: qcom: Document samsung,j3ltetwLin, Meng-Bo
Document samsung,j3ltetw bindings used in its device tree. Signed-off-by: Lin, Meng-Bo <linmengbo06890@proton.me> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240804065854.42437-2-linmengbo06890@proton.me Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: sm8350: add refgen regulatorDmitry Baryshkov
On SM8350 platform the DSI internally is using the refgen regulator. Add corresponding device node and link it as a supply to the DSI node. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-10-1149dd8399fe@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: sm8350: add MDSS registers interconnectDmitry Baryshkov
Aside from the MDSS<->MEM interconnect, display devices have separate interconnect for register access. Add this interconnect to the display node. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-9-1149dd8399fe@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: sm7125-xiaomi-common: Add reset-gpios for ufs_mem_hcDanila Tikhonov
The SC7180/SM7125 SoCs have a special pin for UFS reset. Generally, this pin is the same for all devices on the same SoC because it is hardcoded in the pinctrl driver. Therefore, it might seem appropriate to add this pin configuration in sc7180.dtsi. However, this pin is defined in the device-specific DTS files instead of the SoC-level DTS files in all Qualcomm DTS. To maintain consistency with this approach, we will follow the same style. Add reset-gpios to ufs_mem_hc. Signed-off-by: Danila Tikhonov <danila@jiaxyga.com> Link: https://lore.kernel.org/r/20240731182412.27966-1-danila@jiaxyga.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: sa8775p: Add CPU and LLCC BWMONTengfei Fan
Add CPU and LLCC BWMON nodes and their corresponding opp tables for SA8775p SoC. SA8775p has two cpu clusters, with each cluster having a set of CPU-to-LLCC BWMON registers. Consequently, there are two sets of CPU-to-LLCC registers. Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> Link: https://lore.kernel.org/r/20240730-add_sa8775p_bwmon-v1-2-f4f878da29ae@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: msm8939-longcheer-l9100: Add rear flashAndré Apitzsch
The phone has a Silergy SY7802 flash LED controller. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: André Apitzsch <git@apitzsch.eu> Link: https://lore.kernel.org/r/20240729-sy7802-v6-1-86bb9083e40b@apitzsch.eu Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: add generic compat string to RPM glink channelsDmitry Baryshkov
Add the generic qcom,smd-rpm / qcom,glink-smd-rpm compatible to RPM nodes to follow the schema. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/r/20240729-fix-smd-rpm-v2-5-0776408a94c5@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: sdx75-idp: enable MPSS remoteproc nodeNaina Mehta
Enable MPSS remoteproc node on sdx75-idp platform. Signed-off-by: Naina Mehta <quic_nainmeht@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240709064924.325478-6-quic_nainmeht@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: sdx75: Add remoteproc nodeNaina Mehta
Add MPSS remoteproc node for SDX75 SoC. Signed-off-by: Naina Mehta <quic_nainmeht@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240709064924.325478-5-quic_nainmeht@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: sdx75: update reserved memory regions for mpssNaina Mehta
Rename qdss@88800000 memory region as qlink_logging memory region and add qdss_mem memory region at address of 0x88500000, qlink_logging is being added at the memory region at the address of 0x88800000 as the region is being used by modem firmware. Since different DSM region size is required for different modem firmware, split mpss_dsmharq_mem region into 2 separate regions. This would provide the flexibility to remove the region which is not required for a particular platform. Based on the modem firmware either both the regions have to be used or only mpss_dsm_mem has to be used. Also, reduce the size of mpssadsp_mem region. Signed-off-by: Naina Mehta <quic_nainmeht@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240709064924.325478-4-quic_nainmeht@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: sa8295p-adp: Enable the four USB Type-A portsKrishna Kurapati
The multiport USB controller in the SA8295P ADP is connected to four USB Type-A ports. VBUS for each of these ports are provided by a TPS2559QWDRCTQ1 regulator, controlled from PMIC GPIOs. Add the necessary regulators and GPIO configuration to power these. It seems reasonable that these regulators should be referenced as vbus supply of usb-a-connector nodes and controlled by e.g. dwc3, but as this is not supported in Linux today the regulators are left always-on for now. Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240707085624.3411961-1-quic_kriskura@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: x1e80100-qcp: fix wsa soundwire port mappingSrinivas Kandagatla
Existing way of allocating ports dynamically is linear starting from 1 to MAX_PORTS. This will not work for x1e80100 as the master ports are are not mapped in the same order. Without this fix only one speaker in a pair of speakers will function. After this fix along with WSA codec changes both the speakers starts working. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20240626-port-map-v2-6-6cc1c5608cdd@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: x1e80100-crd: fix wsa soundwire port mappingSrinivas Kandagatla
Existing way of allocating ports dynamically is linear starting from 1 to MAX_PORTS. This will not work for x1e80100 as the master ports are are not mapped in the same order. Without this fix only one speaker in a pair of speakers will function. After this fix along with WSA codec changes both the speakers starts working. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20240626-port-map-v2-5-6cc1c5608cdd@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: x1e80100: add soundwire controller resetsSrinivas Kandagatla
Soundwire controllers (WSA, WSA2, RX, TX) require reset lines to enable switching clock control from hardware to software. Add them along with the reset control providers. Without this reset we might hit fifo under/over run when we try to write to soundwire device registers. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240624-x1e-swr-reset-v2-3-8bc677fcfa64@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: sm8650: add description of CCI controllersVladimir Zapolskiy
Qualcomm SM8650 SoC has three CCI controllers with two I2C busses connected to each of them. The CCI controllers on SM8650 are compatible with the ones found on many other older generations of Qualcomm SoCs. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20240612215835.1149199-5-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: sm8550: add description of CCI controllersVladimir Zapolskiy
Qualcomm SM8550 SoC contains 3 Camera Control Interface controllers very similar to the ones found on other Qualcomm SoCs. One noticeable difference is that cci@ac16000 controller provides only one I2C bus and has an additional control over AON CCI pins gpio208 and gpio209, but this feature is not yet supported in the CCI driver. Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20240612215835.1149199-4-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14arm64: dts: qcom: sm4450: add camera, display and gpu clock controllerAjit Pandey
Add device node for camera, display and graphics clock controller on Qualcomm SM4450 platform. Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240611133752.2192401-9-quic_ajipan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14Merge branch '20240611133752.2192401-1-quic_ajipan@quicinc.com' into ↵Bjorn Andersson
arm64-for-6.12 Merge the SM4450 display, camera and GPU bindings from a topic branch, to gain access to the clock defines.
2024-08-14dt-bindings: clock: qcom: add GPUCC clocks on SM4450Ajit Pandey
Add device tree bindings for the graphics clock controller on Qualcomm SM4450 platform. Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20240611133752.2192401-7-quic_ajipan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14dt-bindings: clock: qcom: add CAMCC clocks on SM4450Ajit Pandey
Add device tree bindings for the camera clock controller on Qualcomm SM4450 platform. Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240611133752.2192401-5-quic_ajipan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14dt-bindings: clock: qcom: add DISPCC clocks on SM4450Ajit Pandey
Add device tree bindings for the display clock controller on Qualcomm SM4450 platform. Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240611133752.2192401-3-quic_ajipan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-13arm64: dts: qcom: sc8180x: Enable the power keyBjorn Andersson
No input events are generated from the pressing of the power key on either Primus or Flex 5G, because the device node isn't enabled. Give the power key node a label and enable this for the two devices. Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Tested-by: Steev Klimaszewski <steev@kali.org> Link: https://lore.kernel.org/r/20240812-sc8180x-pwrkey-enable-v1-1-2bcc22133774@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31arm64: dts: qcom: sm8650-qrd: use the PMU to power up bluetoothBartosz Golaszewski
Change the HW model in sm8650-qrd.dts to a one closer to reality - where the WLAN and Bluetooth modules of the WCN7850 are powered by the PMU inside the package. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD Link: https://lore.kernel.org/r/20240709-hci_qca_refactor-v3-6-5f48ca001fed@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit (git 2.34.1) at 2025-07-16 00:11:39 +0000