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2018-05-17drm/i915: Remove unused enable_cmd_parser modparamChris Wilson
The command parser is feature complete, stable and required by userspace. In commit 41736a8e3331 ("drm/i915: Use the precomputed value for whether to enable command parsing") I accidentally removed control from the modparam, and as no one has complained, remove the left over modparam completely! References: 41736a8e3331 ("drm/i915: Use the precomputed value for whether to enable command parsing") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180517150727.10431-1-chris@chris-wilson.co.uk
2018-05-17drm/i915: Nul-terminate legacy debug stringChris Wilson
Make sure that when we don't have any scheduler attributes for the request, the string is terminated. Fixes: 247870ac8ea7 ("drm/i915: Build request info on stack before printk") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180517152824.11619-1-chris@chris-wilson.co.uk
2018-05-17drm/i915/execlists: HWACK checking superseded checking port[0].countChris Wilson
The HWACK bit more generically solves the problem of resubmitting ESLP while the hardware is still processing the current ELSP write. We no longer need to check port[0].count itself. References: ba74cb10c775 ("drm/i915/execlists: Delay writing to ELSP until HW has processed the previous write") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michel Thierry <michel.thierry@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180517115647.17205-1-chris@chris-wilson.co.uk
2018-05-17drm/i915: Clean up DVO pipe select bitsVille Syrjälä
Parametrize the DVO pipe select bits. For consistency with the new way of doing things, let's read out the pipe select bits even when the port is disable, even though we don't need that behaviour for asserts in this case. v2: Order the defines shift,mask,value (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180514172423.9302-5-ville.syrjala@linux.intel.com
2018-05-17drm/i915: Clean up TV pipe select bitsVille Syrjälä
Parametrize the TV pipe select bits. For consistency with the new way of doing things, let's read out the pipe select bits even when the port is disable, even though we don't need that behaviour for asserts in this case. v2: Order the defines shift,mask,value (Jani) Clear the stale pipe select bit in load detection (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180514172423.9302-4-ville.syrjala@linux.intel.com
2018-05-17drm/i915: Clean up SDVO pipe select bitsVille Syrjälä
Clean up the SDVO pipe select bits. To make the whole situation a bit less ugly we'll start to share the same code between .get_hw_state() and the port state asserts. v2: Order the defines shift,mask,value (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180514172423.9302-3-ville.syrjala@linux.intel.com
2018-05-17drm/i915: Clean up LVDS pipe select bitsVille Syrjälä
Clean up the LVDS pipe select bits. To make the whole situation a bit less ugly we'll start to share the same code between .get_hw_state() and the port state asserts. v2: Order the defines shift,mask,value (Jani) Drop ruperfluous braces and whitesapce changes (Jani) Combine masks in compute_is_dual_link_lvds() (Jani) v3: Fix LVDS_PIPE_SEL_MASK_CPT Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180514182827.28629-1-ville.syrjala@linux.intel.com
2018-05-17drm/i915: Clean up ADPA pipe select bitsVille Syrjälä
Clean up the ADPA pipe select bits. To make the whole situation a bit less ugly we'll start to share the same code between .get_hw_state() and the port state asserts. v2: Order the defines shift,mask,value (Jani) Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180514172423.9302-1-ville.syrjala@linux.intel.com
2018-05-16drm/i915: Stop parking the signaler around resetChris Wilson
We cannot call kthread_park() from softirq context, so let's avoid it entirely during the reset. We wanted to suspend the signaler so that it would not mark a request as complete at the same time as we marked it as being in error. Instead of parking the signaling, stop the engine from advancing so that the GPU doesn't emit the breadcrumb for our chosen "guilty" request. v2: Refactor setting STOP_RING so that we don't have the same code thrice Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Michałt Winiarski <michal.winiarski@intel.com> CC: Michel Thierry <michel.thierry@intel.com> Cc: Jeff McGee <jeff.mcgee@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180516183355.10553-8-chris@chris-wilson.co.uk
2018-05-16drm/i915/execlists: Flush pending preemption events during resetChris Wilson
Catch up with the inflight CSB events, after disabling the tasklet before deciding which request was truly guilty of hanging the GPU. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michał Winiarski <michal.winiarski@intel.com> CC: Michel Thierry <michel.thierry@intel.com> Cc: Jeff McGee <jeff.mcgee@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180516183355.10553-7-chris@chris-wilson.co.uk
2018-05-16drm/i915/execlists: Split out CSB processingChris Wilson
Pull the CSB event processing into its own routine so that we can reuse it during reset to flush any missed interrupts/events. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michał Winiarski <michal.winiarski@intel.com> CC: Michel Thierry <michel.thierry@intel.com> Cc: Jeff McGee <jeff.mcgee@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180516183355.10553-6-chris@chris-wilson.co.uk
2018-05-16drm/i915: Split execlists/guc reset preparationsChris Wilson
In the next patch, we will make the execlists reset prepare callback take into account preemption by flushing the context-switch handler. This is not applicable to the GuC submission backend, so split the two into their own backend callbacks. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michał Winiarski <michal.winiarski@intel.com> CC: Michel Thierry <michel.thierry@intel.com> Cc: Jeff McGee <jeff.mcgee@intel.com> Reviewed-by: Jeff McGee <jeff.mcgee@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180516183355.10553-5-chris@chris-wilson.co.uk
2018-05-16drm/i915: Move engine reset prepare/finish to backendsChris Wilson
In preparation to more carefully handling incomplete preemption during reset by execlists, we move the existing code wholesale to the backends under a couple of new reset vfuncs. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Michał Winiarski <michal.winiarski@intel.com> CC: Michel Thierry <michel.thierry@intel.com> Cc: Jeff McGee <jeff.mcgee@intel.com> Reviewed-by: Jeff McGee <jeff.mcgee@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180516183355.10553-4-chris@chris-wilson.co.uk
2018-05-16drm/i915/execlists: Refactor out complete_preempt_context()Chris Wilson
As a complement to inject_preempt_context(), follow up with the function to handle its completion. This will be useful should we wish to extend the duties of the preempt-context for execlists. v2: And do the same for the guc. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jeff McGee <jeff.mcgee@intel.com> Cc: Michał Winiarski <michal.winiarski@intel.com> Reviewed-by: Jeff McGee <jeff.mcgee@intel.com> #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20180516183355.10553-3-chris@chris-wilson.co.uk
2018-05-16drm/i915: Only sync tasklets once for recursive reset preparationChris Wilson
When setting up reset, we may need to recursively prepare an engine. In which case we should only synchronously flush the tasklets on the outer most call, the inner calls will then be inside an atomic section where the tasklet will never be run (and so the sync will never complete). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180516183355.10553-2-chris@chris-wilson.co.uk
2018-05-16drm/i915: Remove tasklet flush before disableChris Wilson
The idea was to try and let the existing tasklet run to completion before we began the reset, but it involves a racy check against anything else that tries to run the tasklet. Rather than acknowledge and ignore the race, let it be and don't try and be too clever. The tasklet will resume execution after reset (after spinning a bit during reset), but before we allow it to resume we will have cleared all the pending state. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180516183355.10553-1-chris@chris-wilson.co.uk
2018-05-16drm/i915/dp: fix spelling mistakes: "seqeuncer" and "seqeuencer"Colin Ian King
Trivial fix to spelling mistakes in WARN warning message text and in comments: "seqeuncer", "seqeuencer" -> "sequencer" Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180509101606.17483-1-colin.king@canonical.com
2018-05-16drm/i915: Shrink search list for active timelinesChris Wilson
When switching to the kernel context, we force the switch to occur after all currently active requests (so that we know the GPU won't switch immediately away and the kernel context remains current as we work). To do so we have to inspect all the timelines and add a fence from the active work to queue our switch afterwards. We can use the tracked set of active rings to shrink our search for active timelines. v2: Use a local to shrink the list_for_each_entry() Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180515143149.4795-1-chris@chris-wilson.co.uk
2018-05-14drm/i915: Update DRIVER_DATE to 20180514Jani Nikula
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2018-05-14drm/i915: Mark up nested spinlocksChris Wilson
When we process the outstanding requests upon banning a context, we need to acquire both the engine and the client's timeline, nesting the locks. This requires explicit markup as the two timelines are now of the same class, since commit a89d1f921c15 ("drm/i915: Split i915_gem_timeline into individual timelines"). Testcase: igt/gem_eio/banned Fixes: a89d1f921c15 ("drm/i915: Split i915_gem_timeline into individual timelines") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180512084957.9829-1-chris@chris-wilson.co.uk
2018-05-14drm/i915/execlists: Relax CSB force-mmio for VT-dChris Wilson
The original switch to use CSB from the HWSP was plagued by the effect of read ordering on VT-d; we would read the WRITE pointer from the HWSP before it had completed writing the CSB contents. The mystery comes down to the lack of rmb() for correct ordering with respect to the writes from HW, and with that resolved we can remove the VT-d special casing. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Michał Winiarski <michal.winiarski@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180511121147.31915-3-chris@chris-wilson.co.uk Tested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
2018-05-14Merge tag 'gvt-next-2018-05-14' of https://github.com/intel/gvt-linux into ↵Jani Nikula
drm-intel-next-queued - Improve the emulation of virtual non-priv register. (Yan) - Reverse the hack of host of preeption of GVT-g. (Weinan) - Improve untracked warning message.(Changbin) Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ebae7cf1-6550-bb44-74a2-d3a014051804@intel.com
2018-05-14Revert "drm/i915/gvt: set max priority for gvt context"Weinan Li
This reverts commit 11474e9091cf2002e948647fd9f63a7f027e488a. There are issues which will block the host preemption before, instead of disabling it use one workaround "setting max priority for gvt context" to avoid the gvt context be preempted by the host. Now the issues have been cleared, so revert this patch to enable host preemption. v2: - refine description(Zhenyu) Signed-off-by: Weinan Li <weinan.z.li@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
2018-05-14Merge branch 'drm-intel-next-queued' into gvt-nextZhi Wang
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
2018-05-14drm/i915/gvt: let force_to_nonpriv cmd handler only valid for LRI cmdZhao Yan
the cmd_reg_handler() is called by cmds LRM, PIPE_CTRL, SRM... for LRM, SRM, we cannot get write data in a simple way. On other side, the force_to_nonpriv reigsters will only be written in LRI in current drivers. so we don't want to bother the handler to handle those memory access cmds, just leave a print message here. Signed-off-by: Zhao Yan <yan.y.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-05-14drm/i915/gvt: do not return error on handling force_to_nonpriv registersZhao Yan
Return error will cause vm hang and enter failsafe mode. However, we don't want that happen on detecting an wrong force_to_nonpriv register write. Therefore, we just omit the wrong write or patch it to default value. v2: only return 0 on detecting lri write of registers outside whitelist, but still return error on other error conditions. (zhenyu wang) Signed-off-by: Zhao Yan <yan.y.zhao@intel.com> Reviewed-by: Zhang Yulei <yulei.zhang@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-05-14drm/i915/gvt: let NOPID be the default value of force_to_nonpriv registersZhao Yan
Each ring has a NOPID register and currently they are regarded as default value of force_to_nonpriv registers in guest drivers Signed-off-by: Zhao Yan <yan.y.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-05-14drm/i915/gvt: Remove disable_warn_untrack and print untracked mmio with ↵Changbin Du
debug level The disable_warn_untrack never prevent gvt from printing untracked mmio errors. We were disturbed by this error storm and the fix is just adding them to the list with no essential new change. This message is only useful for enabling new platform during developing process. So lower the message level to debug and then remove disable_warn_untrack. Signed-off-by: Changbin Du <changbin.du@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
2018-05-13drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glkMichel Thierry
Factor in clear values wherever required while updating destination min/max. References: HSDES#1604444184 Signed-off-by: Michel Thierry <michel.thierry@intel.com> Cc: mesa-dev@lists.freedesktop.org Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180510200708.18097-1-michel.thierry@intel.com Cc: stable@vger.kernel.org
2018-05-13drm/i915/selftests: scrub 64KMatthew Auld
We write all 4K page entries, even when using 64K pages. In order to verify that the HW isn't cheating by using the 4K PTE instead of the 64K PTE, we want to remove all the surplus entries. If the HW skipped the 64K PTE, it will read/write into the scratch page instead - which we detect as missing results during selftests. v2: much improved commentary (Chris) Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Changbin Du <changbin.du@intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180511095140.25590-1-matthew.auld@intel.com
2018-05-11drm/i915/oa: Check that OA is disabled before unpinningChris Wilson
Before we unpin the buffer used for OA reports and return it to the system, we need to be sure that the HW has finished writing into it. For lack of a better idea, poll OACONTROL to check it is switched off. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106379 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: Matthew Auld <matthew.auld@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Tested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180511135207.12880-1-chris@chris-wilson.co.uk
2018-05-11Revert "drm/i915/cnl: Use mmio access to context status buffer"Chris Wilson
In the previous patch (to include a rmb() after readig the CSB WRITE pointer from the HWSP) we believe we have fixed the underlying bug, and so can re-enable using the HWSP on Cannolake. This reverts commit 61bf9719fa17 ("drm/i915/cnl: Use mmio access to context status buffer"). References: https://bugs.freedesktop.org/show_bug.cgi?id=105888 References: https://bugs.freedesktop.org/show_bug.cgi?id=106185 References: 61bf9719fa17 ("drm/i915/cnl: Use mmio access to context status buffer") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Michał Winiarski <michal.winiarski@intel.com> Cc: Rafael Antognolli <rafael.antognolli@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Timo Aaltonen <tjaalton@ubuntu.com> Tested-by: Timo Aaltonen <tjaalton@ubuntu.com> Acked-by: Michel Thierry <michel.thierry@intel.com> Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180511121147.31915-2-chris@chris-wilson.co.uk
2018-05-11drm/i915/execlists: Use rmb() to order CSB readsChris Wilson
We assume that the CSB is written using the normal ringbuffer coherency protocols, as outlined in kernel/events/ring_buffer.c: * (HW) (DRIVER) * * if (LOAD ->data_tail) { LOAD ->data_head * (A) smp_rmb() (C) * STORE $data LOAD $data * smp_wmb() (B) smp_mb() (D) * STORE ->data_head STORE ->data_tail * } So we assume that the HW fulfils its ordering requirements (B), and so we should use a complimentary rmb (C) to ensure that our read of its WRITE pointer is completed before we start accessing the data. The final mb (D) is implied by the uncached mmio we perform to inform the HW of our READ pointer. References: https://bugs.freedesktop.org/show_bug.cgi?id=105064 References: https://bugs.freedesktop.org/show_bug.cgi?id=105888 References: https://bugs.freedesktop.org/show_bug.cgi?id=106185 Fixes: 767a983ab255 ("drm/i915/execlists: Read the context-status HEAD from the HWSP") References: 61bf9719fa17 ("drm/i915/cnl: Use mmio access to context status buffer") Suggested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Michał Winiarski <michal.winiarski@intel.com> Cc: Rafael Antognolli <rafael.antognolli@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Cc: Timo Aaltonen <tjaalton@ubuntu.com> Tested-by: Timo Aaltonen <tjaalton@ubuntu.com> Acked-by: Michel Thierry <michel.thierry@intel.com> Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20180511121147.31915-1-chris@chris-wilson.co.uk
2018-05-11drm/i915/icl: WaForwardProgressSoftResetOscar Mateo
Avoids a hang during soft reset. v2: Rebased on top of the WA refactoring v3: Added References (Mika) v4: - Rebased - C, not lisp (Chris) - Which steppings affected by this are not clear. For the moment, apply unconditionally as per the BSpec (Mika) - Add reference to another HSD also related References: HSDES#1405476379 References: HSDES#2006612137 Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-14-git-send-email-oscar.mateo@intel.com
2018-05-11drm/i915/icl: Wa_1406838659Oscar Mateo
Disable CGPSF unit clock gating to prevent an issue. v2: Rebased on top of the WA refactoring v3: Added References (Mika) v4: - Rebased - C, not lisp (Chris) - Remove unintentional whitespaces (Mika) - Fixed in C0 (Mika) References: HSDES#1406838659 Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-13-git-send-email-oscar.mateo@intel.com
2018-05-11drm/i915/icl: Wa_1604302699Oscar Mateo
Disable I2M Write for performance reasons. v2: Rebased on top of the WA refactoring v3: Added References (Mika) v4: - Rebased - C, not lisp (Chris) - GEN7 chicken bit in the wrong side of the fence (Mika) - Use two spaces to align bit macros References: HSDES#1604302699 Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-12-git-send-email-oscar.mateo@intel.com
2018-05-11drm/i915/icl: Wa_1406680159Oscar Mateo
Disable GWL clock gating to prevent an issue that might cause hangs. v2: Rebased on top of the WA refactoring v3: Wa_2201832410 officially merged with Wa_1406680159 v4: Added References (Mika) v5: - Rebased - C, not lisp (Chris) - Add reference where WA is better explained (Rodrigo) - Add reference to WA that got merged with this References: HSDES#1406681710 References: HSDES#1406680159 References: HSDES#2201832410 Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-11-git-send-email-oscar.mateo@intel.com
2018-05-11drm/i915/icl: Wa_1405779004Oscar Mateo
Disable MSC clock gating to prevent data corruption. BSpec: 19257 v2: Rebased on top of the WA refactoring v3: Added References (Mika) v4: - Rebased - C, not lisp (Chris) - A0 only (Mika) References: HSDES#1405779004 Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-10-git-send-email-oscar.mateo@intel.com
2018-05-11drm/i915/icl: WaDisCtxReloadOscar Mateo
Revert to the legacy implementation to avoid a system hang. v2: Correct the address for GAMW_ECO_DEV_RW_IA_REG v3: Renamed to Wa_220166154 v4: Rebased on top of the WA refactoring v5: Added References (Mika) v6: - Rebased - C, not lisp (Chris) References: HSDES#220166154 Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-9-git-send-email-oscar.mateo@intel.com
2018-05-11drm/i915/icl: WaCL2SFHalfMaxAllocOscar Mateo
This workarounds an issue with insufficient storage for the CL2 and SF units. v2: Renamed to Wa_1405766107 v3: Wrapped the commit message v4: Rebased on top of the WA refactoring v5: Added References (Mika) v6: - Rebased - s/MACALLOC/MAXALLOC (Mika) - C, not lisp (Chris) References: HSDES#1405766107 Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-8-git-send-email-oscar.mateo@intel.com
2018-05-11drm/i915/icl: WaDisableCleanEvictsOscar Mateo
Avoids an undefined LLC behavior. BSpec: 9613 v2: Renamed to Wa_1405733216 v3: Spaces around '<<' and fix surrounding code v4: Rebased on top of the WA refactoring v5: Added References (Mika) v6: - Rebased - C, not lisp (Chris) References: HSDES#1405733216 Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-7-git-send-email-oscar.mateo@intel.com
2018-05-11drm/i915/icl: WaModifyGamTlbPartitioningOscar Mateo
Adjust default GAM TLB partitioning for performance reasons. v2: Only touch the bits that we really need v3: Rebased on top of the WA refactoring v4: - Added References (Mika) - Rebased v5: - Rebased - C, not lisp (Chris) - Correct reference number (Mika) References: HSDES#220160670 Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-6-git-send-email-oscar.mateo@intel.com
2018-05-11drm/i915/icl: WaL3BankAddressHashingOscar Mateo
Revert to an L3 non-hash model, for performance reasons. v2: - Place the WA name above the actual change - Improve the register naming v3: - Rebased - Renamed to Wa_1604223664 v4: Rebased on top of the WA refactoring v5: - Added References (Mika) - Fixed wrong mask and value (Mika) - Do not apply together with another WA for the same register (not worth the hassle) v6: - Rebased - C, not lisp (Chris) References: HSDES#1604223664 Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-5-git-send-email-oscar.mateo@intel.com
2018-05-11drm/i915/icl: WaGAPZPrioritySchemeOscar Mateo
The default GAPZ arbitrer priority value at power-on has been found to be incorrect. v2: Now renamed to Wa_1405543622 v3: Rebased on top of the WA refactoring v4: Added HSDES reference number (Mika) v5: - Rebased - C, not lisp (Chris) References: HSDES#1405543622 Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-4-git-send-email-oscar.mateo@intel.com
2018-05-11drm/i915/icl: Enable Sampler DFROscar Mateo
Sampler Dynamic Frequency Rebalancing (DFR) aims to reduce Sampler power by dynamically changing its clock frequency in low-throughput conditions. This patches enables it by default on Gen11. v2: Wrong operation to clear the bit (Praveen) v3: Rebased on top of the WA refactoring v4: Move to icl_init_clock_gating, since it's not a WA (Rodrigo) v5: C, not lisp (Chris) Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Cc: Praveen Paneri <praveen.paneri@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-3-git-send-email-oscar.mateo@intel.com
2018-05-11drm/i915/icl: Introduce initial Icelake WorkaroundsOscar Mateo
Inherit workarounds from previous platforms that are still valid for Icelake. v2: GEN7_ROW_CHICKEN2 is masked v3: - Since it has been fixed already in upstream, removed the TODO comment about WA_SET_BIT for WaInPlaceDecompressionHang. - Squashed with this patch: drm/i915/icl: add icelake_init_clock_gating() from Paulo Zanoni <paulo.r.zanoni@intel.com> - Squashed with this patch: drm/i915/icl: WaForceEnableNonCoherent from Oscar Mateo <oscar.mateo@intel.com> - WaPushConstantDereferenceHoldDisable is now Wa_1604370585 and applies to B0 as well. - WaPipeControlBefore3DStateSamplePattern WABB was being applied to ICL incorrectly. v4: - Wrap the commit message - s/dev_priv/p to please checkpatch v5: Rebased on top of the WA refactoring v6: Rebased on top of further whitelist registers refactoring (Michel) v7: Added WaRsForcewakeAddDelayForAck v8: s/ICL_HDC_CHICKEN0/ICL_HDC_MODE (Mika) v9: - C, not lisp (Chris) - WaIncreaseDefaultTLBEntries is the same for GEN > 9_LP (Tvrtko) Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tomasz Lis <tomasz.lis@intel.com> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1525814984-20039-2-git-send-email-oscar.mateo@intel.com
2018-05-11drm/i915/gtt: Trust the uncached store to flush wcbMika Kuoppala
Not all architectures guarantee that uncached read will flush the write combining buffer. So marking it explicitly is recommended [1]. However we know the architecture we are operating on and can avoid wmb as the UC store will flush the wcb [2]. Omit the wmb() before invalidate as redudant. v2: squash combining and removal (Chris) v3: remove obsolete comments about posting reads (Chris) References: http://yarchive.net/comp/linux/write_combining.html [1] References: http://download.intel.com/design/PentiumII/applnots/24442201.pdf [2] Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Matthew Auld <matthew.auld@intel.com> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20180508124154.14586-1-mika.kuoppala@linux.intel.com
2018-05-11drm/i915: Add NV12 as supported format for sprite planeChandra Konduru
This patch adds NV12 to list of supported formats for sprite plane. v2: Rebased (me) v3: Review comments by Ville addressed - Removed skl_plane_formats_with_nv12 and added NV12 case in existing skl_plane_formats - Added the 10bpc RGB formats v4: Addressed review comments from Clinton A Taylor "Why are we adding 10 bit RGB formats with the NV12 series patches? Trying to set XR30 or AB30 results in error returned even though the modes are advertised for the planes" - Removed 10bit RGB formats added previously with NV12 series v5: Missed the Tested-by/Reviewed-by in the previous series Adding the same to commit message in this version. Addressed review comments from Clinton A Taylor "Why are we adding 10 bit RGB formats with the NV12 series patches? Trying to set XR30 or AB30 results in error returned even though the modes are advertised for the planes" - Previous version has 10bit RGB format removed from VLV formats by mistake. Fixing that in this version. Removed 10bit RGB formats added previously with NV12 series for SKL. v6: Addressed review comments by Ville Restricting the NV12 to BXT and PIPE A and B v7: Rebased (me) v8: Rebased (me) Restricting NV12 changes to BXT and KBL Restricting NV12 changes for plane 0 (overlay) v9: Rebased (me) v10: Addressed review comments from Maarten. Adding NV12 to skl_plane_formats itself. v11: Addressed review comments from Shashank Sharma v12: Addressed review comments from Shashank Sharma Made the condition in intel_sprite_plane_create simple and easy to read as suggested. v13: Adding reviewed by tag from Shashank Sharma Addressed review comments from Juha-Pekka Heikkila "NV12 not to be supported by SKL" v14: Addressed review comments from Ville Added skl_planar_formats to include NV12 and a check skl_plane_has_planar in sprite create Added NV12 format to skl_mod_supported. These were review comments from Kristian Høgsberg <hoegsberg@gmail.com> v15: Added reviewed by from Juha-Pekka Heikkila v16: Rebased the series v17: Added all tiling under mod supported for NV12 Credits to Megha Aggarwal v18: Added RB by Maarten and Kristian v19: Addressed review comments from Maarten Made modification to skl_mod_supported Credits-to: Megha Aggarwal <megha.aggarwal@intel.com> Credits-to: Kristian Høgsberg <hoegsberg@gmail.com> Reviewed-by: Kristian Høgsberg <hoegsberg@gmail.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1526074397-10457-7-git-send-email-vidya.srinivas@intel.com
2018-05-11drm/i915: Add NV12 as supported format for primary planeChandra Konduru
This patch adds NV12 to list of supported formats for primary plane v2: Rebased (Chandra Konduru) v3: Rebased (me) v4: Review comments by Ville addressed Removed the skl_primary_formats_with_nv12 and added NV12 case in existing skl_primary_formats v5: Rebased (me) v6: Missed the Tested-by/Reviewed-by in the previous series Adding the same to commit message in this version. v7: Review comments by Ville addressed Restricting the NV12 for BXT and on PIPE A and B Rebased (me) v8: Rebased (me) Modified restricting the NV12 support for both BXT and KBL. v9: Rebased (me) v10: Addressed review comments from Maarten. Adding NV12 inside skl_primary_formats itself. v11: Adding Reviewed By tag from Shashank Sharma v12: Addressed review comments from Juha-Pekka Heikkila "NV12 not to be supported by SKL" v13: Addressed review comments from Ville Added skl_pri_planar_formats to include NV12 and skl_plane_has_planar function to check for NV12 support on plane. Added NV12 format to skl_mod_supported. These were review comments from Kristian Høgsberg <hoegsberg@gmail.com> v14: Added reviewed by from Juha-Pekka Heikkila v15: Rebased the series v16: Added all tiling support under mod supported for NV12. Credits to Megha Aggarwal v17: Added RB by Maarten and Kristian v18: Review comments from Maarten addressed - Removing BROXTON support for NV12 due to WA826 v19: Addressed review comments from Maarten Make changes to skl_mod_supported Credits-to: Megha Aggarwal megha.aggarwal@intel.com Credits-to: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com> Reviewed-by: Kristian Høgsberg <hoegsberg@gmail.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1526074397-10457-6-git-send-email-vidya.srinivas@intel.com
2018-05-11drm/i915: Add NV12 support to intel_framebuffer_initChandra Konduru
This patch adds NV12 as supported format to intel_framebuffer_init and performs various checks. v2: -Fix an issue in checks added (Chandra Konduru) v3: rebased (me) v4: Review comments by Ville addressed Added platform check for NV12 in intel_framebuffer_init Removed offset checks for NV12 case v5: Addressed review comments by Clinton A Taylor This NV12 support only correctly works on SKL. Plane color space conversion is different on GLK and later platforms causing the colors to display incorrectly. Ville's plane color space property patch series in review will fix this issue. - Restricted the NV12 case in intel_framebuffer_init to SKL and BXT only. v6: Rebased (me) v7: Addressed review comments by Ville Restricting the NV12 to BXT for now. v8: Rebased (me) Restricting the NV12 changes to BXT and KBL for now. v9: Rebased (me) v10: NV12 supported by all GEN >= 9. Making this change in intel_framebuffer_init. This is part of addressing Maarten's review comments. Comment under v8 no longer applicable v11: Addressed review comments from Shashank Sharma v12: Adding Reviewed By from Shashank Sharma v13: Addressed review comments from Juha-Pekka Heikkila "NV12 not to be supported by SKL" v14: Addressed review comments from Maarten. Add checks for fb width height for NV12 and fail the fb creation if check fails. Added reviewed by from Juha-Pekka Heikkila v15: Rebased the series v16: Setting the minimum value during fb creating to 16 as per Bspec for NV12. Earlier minimum was expected to be > 16. Now changed it to >=16. v17: Adding restriction to framebuffer_init - the fb width and height should be a multiplier of 4 v18: Added RB from Maarten. Included Maarten's review comments Dont allow CCS formats for fb creation of NV12 v19: Review comments from Maarten addressed - Removing BROXTON support for NV12 due to WA826 Credits-to: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Shashank Sharma <shashank.sharma@intel.com> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1526074397-10457-5-git-send-email-vidya.srinivas@intel.com
generated by cgit (git 2.34.1) at 2025-07-15 13:21:29 +0000