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2025-11-13accel/amdxdna: Fix deadlock between context destroy and job timeoutLizhi Hou
Hardware context destroy function holds dev_lock while waiting for all jobs to complete. The timeout job also needs to acquire dev_lock, this leads to a deadlock. Fix the issue by temporarily releasing dev_lock before waiting for all jobs to finish, and reacquiring it afterward. Fixes: 4fd6ca90fc7f ("accel/amdxdna: Refactor hardware context destroy routine") Reviewed-by: Maciej Falkowski <maciej.falkowski@linux.intel.com> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Link: https://patch.msgid.link/20251107181050.1293125-1-lizhi.hou@amd.com
2025-11-13accel/amdxdna: Clear mailbox interrupt register during channel creationLizhi Hou
The mailbox interrupt register is not always cleared when a mailbox channel is created. This can leave stale interrupt states from previous operations. Fix this by explicitly clearing the interrupt register in the mailbox channel creation function. Fixes: b87f920b9344 ("accel/amdxdna: Support hardware mailbox") Reviewed-by: Maciej Falkowski <maciej.falkowski@linux.intel.com> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Link: https://patch.msgid.link/20251107181115.1293158-1-lizhi.hou@amd.com
2025-11-13drm/imx/ipuv3: Fix dumb-buffer allocation for non-RGB formatsThomas Zimmermann
Align pitch to multiples of 8 pixels for bpp values that do not map to RGB formats. The call to drm_driver_color_mode_format() fails with DRM_INVALID_FORMAT in these cases. Fall back to manually computing the pitch alignment from which drm_mode_size_dumb() can compute the correct pitch. Fixes userspace that allocates dumb buffers for YUV formats, where bpp equals 12. A common example is the IGT kms_getfb test. v2: - ignore width in calculation Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Fixes: b1d0e470f881 ("drm/imx/ipuv3: Compute dumb-buffer sizes with drm_mode_size_dumb()") Cc: Thomas Zimmermann <tzimmermann@suse.de> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org Tested-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://patch.msgid.link/20251104153832.189666-1-tzimmermann@suse.de
2025-11-12drm/nouveau: fully define nvfw_hs_load_header_v2Timur Tabi
Add the missing fields of the nvfw_hs_load_header_v2 struct, so that the struct matches the actual contents of the firmware images. nvfw_hs_load_header_v2 is a struct that defines a header for some firmware images used by Nouveau. The current structure definition is incomplete; it omits the last two fields because they are unused. To maintain consistency between Nouveau, OpenRM, and Nova, and to make it easier to support possible future images, we should fully define the struct. Also add a __counted_by tag for the flex array. Signed-off-by: Timur Tabi <ttabi@nvidia.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patch.msgid.link/20251010223957.1078525-1-ttabi@nvidia.com
2025-11-12drm/nouveau/drm: Bump the driver version to 1.4.1 to report new featuresMohamed Ahmed
The HW can only do compression on large and huge pages, and enabling it on 4K pages leads to a MMU fault. Compression also needs kernel support for handling the compressed kinds and managing the compression tags. This increments the nouveau version number which allows NVK to enable it only when the kernel actually supports both features and avoid breaking the system if a newer mesa version is paired with an older kernel version. For the associated userspace MR, please see !36450: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36450 Signed-off-by: Mohamed Ahmed <mohamedahmedegypt2001@gmail.com> Signed-off-by: Mary Guillemard <mary@mary.zone> Reviewed-by: Lyude Paul <lyude@redhat.com> Reviewed-by: James Jones <jajones@nvidia.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patch.msgid.link/20251110-nouveau-compv6-v6-5-83b05475f57c@mary.zone
2025-11-12drm/nouveau/mmu/tu102: Add support for compressed kindsBen Skeggs
Allow compressed PTE kinds to be written into PTEs when GSP-RM is present, rather than reverting to their non-compressed versions. Signed-off-by: Ben Skeggs <bskeggs@nvidia.com> Signed-off-by: Mohamed Ahmed <mohamedahmedegypt2001@gmail.com> Signed-off-by: Mary Guillemard <mary@mary.zone> Reviewed-by: Lyude Paul <lyude@redhat.com> Reviewed-by: James Jones <jajones@nvidia.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patch.msgid.link/20251110-nouveau-compv6-v6-4-83b05475f57c@mary.zone
2025-11-12drm/nouveau/mmu/gp100: Remove unused/broken support for compressionBen Skeggs
From GP100 onwards it's not possible to initialise comptag RAM without PMU firmware, which nouveau has no support for. As such, this code is essentially a no-op and will always revert to the equivalent non-compressed kind due to comptag allocation failure. It's also broken for the needs of VM_BIND/Vulkan. Remove the code entirely to make way for supporting compression on GPUs that support GSM-RM. Signed-off-by: Ben Skeggs <bskeggs@nvidia.com> Signed-off-by: Mohamed Ahmed <mohamedahmedegypt2001@gmail.com> Signed-off-by: Mary Guillemard <mary@mary.zone> Reviewed-by: Lyude Paul <lyude@redhat.com> Reviewed-by: James Jones <jajones@nvidia.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patch.msgid.link/20251110-nouveau-compv6-v6-3-83b05475f57c@mary.zone
2025-11-12drm/nouveau/uvmm: Allow larger pagesMary Guillemard
Now that everything in UVMM knows about the variable page shift, we can select larger values. The proposed approach relies on nouveau_bo::page unless if it would cause alignment issues (in which case we fall back to searching for an appropriate shift) Signed-off-by: Mary Guillemard <mary@mary.zone> Co-developed-by: Mohamed Ahmed <mohamedahmedegypt2001@gmail.com> Signed-off-by: Mohamed Ahmed <mohamedahmedegypt2001@gmail.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Reviewed-by: James Jones <jajones@nvidia.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patch.msgid.link/20251110-nouveau-compv6-v6-2-83b05475f57c@mary.zone
2025-11-12drm/nouveau/uvmm: Prepare for larger pagesMary Guillemard
Currently memory allocated by VM_BIND uAPI can only have a granuality matching PAGE_SIZE (4KiB in common case) To have a better memory management and to allow big (64KiB) and huge (2MiB) pages later in the series, we are now passing the page shift all around the internals of UVMM. Signed-off-by: Mary Guillemard <mary@mary.zone> Co-developed-by: Mohamed Ahmed <mohamedahmedegypt2001@gmail.com> Signed-off-by: Mohamed Ahmed <mohamedahmedegypt2001@gmail.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Reviewed-by: James Jones <jajones@nvidia.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patch.msgid.link/20251110-nouveau-compv6-v6-1-83b05475f57c@mary.zone
2025-11-12drm/tidss: Move OLDI mode validation to OLDI bridge mode_valid hookJayesh Choudhary
After integrating OLDI support[0], it is necessary to identify which VP instances use OLDI, since the OLDI driver owns the video port clock (as a serial clock). Clock operations on these VPs must be delegated to the OLDI driver, not handled by the TIDSS driver. This issue also emerged in upstream discussions when DSI-related clock management was attempted in the TIDSS driver[1]. To address this, add an 'is_ext_vp_clk' array to the 'tidss_device' structure, marking a VP as 'true' during 'tidss_oldi_init()' and as 'false' during 'tidss_oldi_deinit()'. TIDSS then uses 'is_ext_vp_clk' to skip clock validation checks in 'dispc_vp_mode_valid()' for VPs under OLDI control. Since OLDI uses the DSS VP clock directly as a serial interface and manages its own rate, mode validation should be implemented in the OLDI bridge's 'mode_valid' hook. This patch adds that logic, ensuring proper delegation and avoiding spurious clock handling in the TIDSS driver. [0]: https://lore.kernel.org/all/20250528122544.817829-1-aradhya.bhatia@linux.dev/ [1]: https://lore.kernel.org/all/DA6TT575Z82D.3MPK8HG5GRL8U@kernel.org/ Fixes: 7246e0929945 ("drm/tidss: Add OLDI bridge support") Tested-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Swamil Jain <s-jain1@ti.com> Link: https://patch.msgid.link/20251104151422.307162-3-s-jain1@ti.com Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Link: https://patch.msgid.link/ffd5ebe03391b3c01e616c0c844a4b8ddecede36.1762513240.git.jani.nikula@intel.com
2025-11-12drm/tidss: Remove max_pclk_khz and min_pclk_khz from tidss display featuresJayesh Choudhary
The TIDSS hardware does not have independent maximum or minimum pixel clock limits for each video port. Instead, these limits are determined by the SoC's clock architecture. Previously, this constraint was modeled using the 'max_pclk_khz' and 'min_pclk_khz' fields in 'dispc_features', but this approach is static and does not account for the dynamic behavior of PLLs. This patch removes the 'max_pclk_khz' and 'min_pclk_khz' fields from 'dispc_features'. The correct way to check if a requested mode's pixel clock is supported is by using 'clk_round_rate()' in the 'mode_valid()' hook. If the best frequency match for the mode clock falls within the supported tolerance, it is approved. TIDSS supports a 5% pixel clock tolerance, which is now reflected in the validation logic. This change allows existing DSS-compatible drivers to be reused across SoCs that only differ in their pixel clock characteristics. The validation uses 'clk_round_rate()' for each mode, which may introduce additional delay (about 3.5 ms for 30 modes), but this is generally negligible. Users desiring faster validation may bypass these calls selectively, for example, checking only the highest resolution mode, as shown here[1]. [1]: https://lore.kernel.org/all/20250704094851.182131-3-j-choudhary@ti.com/ Tested-by: Michael Walle <mwalle@kernel.org> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Swamil Jain <s-jain1@ti.com> Link: https://patch.msgid.link/20251104151422.307162-2-s-jain1@ti.com [Tomi: dropped 'inline' from check_pixel_clock] Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
2025-11-12drm/sun4i: Nuke mixer pointer from layer codeJernej Skrabec
It's not used anymore, so remove it. This allows trully independent layer state from mixer. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-31-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: vi_scaler: Find mixer from crtcJernej Skrabec
With "floating" planes in DE33, mixer can't be stored in layer structure anymore. Find mixer using currently bound crtc. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-30-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: layer: replace mixer with layer structJernej Skrabec
This allows to almost completely decouple layer code from mixer. This is important for DE33. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-29-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: mixer: split out layer configJernej Skrabec
Later special plane only driver for DE33 will provide separate configuration. This change will also help layer driver migrate away from mixer structure. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-28-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: mixer: Add quirk for number of VI scalersJernej Skrabec
On DE2 and DE3, UI scalers are located right after VI scalers. So in order to calculate proper UI scaler base address, number of VI scalers must be known. In practice, it is same as number of VI channels, but it doesn't need to be. Let's make a quirk for this number. Code for configuring channels and associated functions won't have access to vi_num quirk anymore after rework for independent planes. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-27-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: ui_scaler: drop sanity checksJernej Skrabec
They can't be triggered if mixer configuration is properly specified in quirks. Additionally, number of VI channels won't be available in future due to rework for DE33 support. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-26-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: mixer: Convert heuristics to quirkJernej Skrabec
Determination if FCC unit can be used for VI layer alpha depends on number of VI channels. This info won't be available anymore in future to VI layer driver because of DE33 way of allocating planes from same pool to different mixers. While order is slightly changed, it doesn't affect anything due to double buffering of registers. New order keeps related registers together and quirk separate. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-25-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: vi_scaler: Update DE33 base calculationJernej Skrabec
Now that channel base calculation is straightforward, let's update VI scaler base calculation to be simpler. At the same time, also introduce macro to avoid magic numbers. Note, reason why current magic value and new macro value isn't the same is because sun8i_channel_base() already introduces offset to channel registers. Previous value is just the difference to VI scaler registers. However, new code calculates scaler base from channel base. This is also easier to understand when looking into BSP driver. Macro value can be easily found whereas old diff value was not. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-24-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: layers: add physical index argJernej Skrabec
This avoids plane mapping in layers code, which allows future refactoring, when layer code will move away from accessing mixer structure. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-23-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: csc: use layer arg instead of mixerJernej Skrabec
Layer will be more universal, due to DE33 support. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-22-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: layers: Make regmap for layers configurableJernej Skrabec
Till DE33, there were no reason to decouple registers from mixer. However, with future new plane driver, this will be necessary. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-21-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: vi_scaler: use layer instead of mixer for argsJernej Skrabec
Layer related peripherals should take layer struct as a input. This looks cleaner and also necessary for proper DE33 support later. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-20-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: ui_scaler: use layer instead of mixer for argsJernej Skrabec
Layer related peripherals should take layer struct as a input. This looks cleaner and also necessary for proper DE33 support later. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-19-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: vi_layer: use layer struct instead of multiple argsJernej Skrabec
This change is equally a cleanup (less arguments) and preparation for DE33 separate plane driver. It will introduce additional register space. No functional changes. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-18-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: ui_layer: use layer struct instead of multiple argsJernej Skrabec
This change is equally a cleanup (less arguments) and preparation for DE33 separate plane driver. It will introduce additional register space. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-17-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: layer: move num of planes calc out of layer codeJernej Skrabec
With DE33, number of planes no longer depends on mixer because layers are shared between all mixers. Get this value via parameter, so DE specific code can fill in proper value. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-16-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: ui_layer: Change index meaningJernej Skrabec
In the pursuit of making UI/VI layer code independent of DE version, change meaning of UI index to index of the plane within mixer. DE33 can split amount of VI and UI planes between multiple mixer in whatever way it deems acceptable, so simple calculation VI num + UI index won't be meaningful anymore. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-15-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: de2/de3: Move plane type determination to mixerJernej Skrabec
Plane type determination logic inside layer init functions doesn't allow index register to be repurposed to plane sequence, which it almost is. So move out the logic to mixer, which allows further rework for DE33 support. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-14-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: csc: Simplify arguments with taking plane stateJernej Skrabec
Taking plane state directly reduces number of arguments, avoids copying values and allows making additional decisions. For example, when plane is disabled, CSC should be turned off. This is also cleanup for later patches which will move call to another place. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-13-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: de2/de3: Simplify CSC config interfaceJernej Skrabec
Merging both function into one lets this one decide on it's own if CSC should be enabled or not. Currently heuristics for that is pretty simple - enable it for YUV formats and disable for RGB. DE3 and newer allows YUV pipeline, which will be easier to implement these way. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-12-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: mixer: Move layer enabling to atomic_updateJernej Skrabec
Enable or disable layer only in layer atomic update callback. Doing so will enable having separate layer driver later for DE33. There is no fear that enable bit would be set incorrectly, as all read-modify-write sequences for that register are now eliminated. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-11-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: vi layer: Write attributes in one goJernej Skrabec
It turns out that none of the VI channel registers were meant to be read. Mostly it works fine but sometimes it returns incorrect values. Rework VI layer code to write all registers in one go to avoid reads. This rework will also allow proper code separation. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-10-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: ui layer: Write attributes in one goJernej Skrabec
It turns out that none of the UI channel registers were meant to be read. Mostly it works fine but sometimes it returns incorrect values. Rework UI layer code to write all registers in one go to avoid reads. This rework will also allow proper code separation. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-9-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: Move blender config from layers to mixerJernej Skrabec
With upcoming DE33 support, layer management must be decoupled from other operations like blender configuration. There are two reasons: - DE33 will have separate driver for planes and thus it will be harder to manage different register spaces - Architecturaly it's better to split access by modules. Blender is now exclusively managed by mixer. Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-8-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: layers: Make atomic commit functions voidJernej Skrabec
Functions called by atomic_commit callback should not fail. None of them actually returns error, so make them void. No functional change. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-7-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: vi_layer: Move check from update to check callbackJernej Skrabec
DRM requires that all check are done in atomic_check callback. Move one check from atomic_commit to atomic_check callback. Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Chen-Yu Tsai <wens@kernel.org> Link: https://patch.msgid.link/20251104180942.61538-6-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: ui_layer: Move check from update to check callbackJernej Skrabec
DRM requires that all checks are done in atomic_check callback. Move one check from atomic_commit to atomic_check callback. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-5-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: de2: Initialize layer fields earlierJernej Skrabec
drm_universal_plane_init() can already call some callbacks, like format_mod_supported, during initialization. Because of that, fields should be initialized beforehand. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-4-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: mixer: Remove ccsc cfg for >= DE3Jernej Skrabec
Those engine versions don't need ccsc argument, since CSC units are located on different position and for each layer. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-3-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12drm/sun4i: mixer: Fix up DE33 channel macrosJernej Skrabec
Properly define macros. Till now raw numbers and inappropriate macro was used. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Ryan Walklin <ryan@testtoast.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20251104180942.61538-2-jernej.skrabec@gmail.com Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
2025-11-12accel/ivpu: Fix warning due to undefined CONFIG_PROC_FSKarol Wachowski
Change #if to #ifdef CONFIG_PROC_FS to fix warning reported by test robot: drivers/accel/ivpu/ivpu_drv.c:458:5: warning: "CONFIG_PROC_FS" is not defined, evaluates to 0 [-Wundef] Fixes: 63cc028484ab ("accel/ivpu: Add fdinfo support for memory statistics") Reviewed-by: Maciej Falkowski <maciej.falkowski@linux.intel.com> Reviewed-by: Andrzej.Kacprowski@linux.intel.com Signed-off-by: Karol Wachowski <karol.wachowski@linux.intel.com> Link: https://patch.msgid.link/20251112071911.1136934-1-karol.wachowski@linux.intel.com
2025-11-12accel/ivpu: Count only resident buffers in memory utilizationKarol Wachowski
Do not count buffer objects that have no backing pages, including imported buffers where pages are set by VM faults triggered by userspace or pinned by other drivers. Instead, return information about actual memory used by the NPU. Counting imported buffers results in incorrect calculations when the same pages are counted multiple times, giving overly high results. Fixes: 7bfc9fa99580 ("accel/ivpu: Expose NPU memory utilization info in sysfs") Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Signed-off-by: Karol Wachowski <karol.wachowski@linux.intel.com> Link: https://patch.msgid.link/20251106101052.1050348-3-karol.wachowski@linux.intel.com
2025-11-12accel/ivpu: Add fdinfo support for memory statisticsKarol Wachowski
Implement DRM fdinfo interface to expose memory usage statistics for NPU device file descriptors. Exclude unpinned and imported buffers from resident memory calculations to provide accurate memory usage reporting. Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Signed-off-by: Karol Wachowski <karol.wachowski@linux.intel.com> Link: https://patch.msgid.link/20251106101052.1050348-2-karol.wachowski@linux.intel.com
2025-11-10accel/qaic: Format DBC states table in sysfs ABI documentationBagas Sanjaya
Stephen Rothwell reports htmldocs warnings when merging drm-misc tree: Documentation/ABI/stable/sysfs-driver-qaic:1: ERROR: Unexpected indentation. [docutils] Documentation/ABI/stable/sysfs-driver-qaic:1: WARNING: Block quote ends without a blank line; unexpected unindent. [docutils] Documentation/ABI/stable/sysfs-driver-qaic:1: WARNING: Definition list ends without a blank line; unexpected unindent. [docutils] These are caused by DMA Bridge channel (DBC) states list in sysfs ABI docs. Format it as a table to fix them. Fixes: f286066ed9df38 ("accel/qaic: Add DMA Bridge Channel(DBC) sysfs and uevents") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Closes: https://lore.kernel.org/linux-next/20251110135038.29e96051@canb.auug.org.au/ Signed-off-by: Bagas Sanjaya <bagasdotme@gmail.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Signed-off-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Link: https://patch.msgid.link/20251110035952.25778-4-bagasdotme@gmail.com
2025-11-10accel/qaic: Separate DBC_STATE_* definition listBagas Sanjaya
Stephen Rothwell reports htmldocs warnings when merging drm-misc tree: Documentation/accel/qaic/aic100.rst:502: ERROR: Unexpected indentation. [docutils] Documentation/accel/qaic/aic100.rst:504: WARNING: Block quote ends without a blank line; unexpected unindent. [docutils] Fix these by separating DBC_STATE_* definition list from preceding paragraph. Fixes: 9675093acea04c ("accel/qaic: Implement basic SSR handling") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Closes: https://lore.kernel.org/linux-next/20251110132401.200d88bd@canb.auug.org.au/ Signed-off-by: Bagas Sanjaya <bagasdotme@gmail.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Signed-off-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Link: https://patch.msgid.link/20251110035952.25778-3-bagasdotme@gmail.com
2025-11-10drm/panthor: Fix potential memleak of vma structureAkash Goel
This commit addresses a memleak issue of panthor_vma (or drm_gpuva) structure in Panthor driver, that can happen if the GPU page table update operation to map the pages fail. The issue is very unlikely to occur in practice. v2: Add panthor_vm_op_ctx_return_vma() helper (Boris) v3: Add WARN_ON_ONCE (Boris) Fixes: 647810ec2476 ("drm/panthor: Add the MMU/VM logical block") Signed-off-by: Akash Goel <akash.goel@arm.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Steven Price <steven.price@arm.com> Signed-off-by: Steven Price <steven.price@arm.com> Link: https://patch.msgid.link/20251021081042.1377406-1-akash.goel@arm.com
2025-11-10drm/ast: Handle framebuffer from dma-bufJocelyn Falempe
In the atomic update callback, ast should call drm_gem_fb_begin_cpu_access() to make sure it can read the framebuffer from the CPU, otherwise the data might not be there due to cache, and synchronization. Tested on a Lenovo SE100, while rendering on the ArrowLake GPU with i915 driver, and using ast for display. Suggested-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patch.msgid.link/20251030091627.340780-1-jfalempe@redhat.com Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
2025-11-10Merge remote-tracking branch 'drm/drm-next' into drm-misc-nextMaarten Lankhorst
Backmerge to prevent getting out of sync with drm-next too much. Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
2025-11-10drm/msm: use drm_crtc_vblank_waitqueue()Jani Nikula
We have drm_crtc_vblank_waitqueue() to get the wait_queue_head_t pointer for a vblank. Use it instead of poking at dev->vblank[] directly. Due to the macro maze of wait_event_timeout() that uses the address-of operator on the argument, we have to pass it in with the indirection operator. Cc: Rob Clark <robin.clark@oss.qualcomm.com> Cc: Dmitry Baryshkov <lumag@kernel.org> Cc: Abhinav Kumar <abhinav.kumar@linux.dev> Cc: Jessica Zhang <jesszhan0024@gmail.com> Cc: Sean Paul <sean@poorly.run> Cc: Marijn Suijten <marijn.suijten@somainline.org> Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Acked-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://patch.msgid.link/5917fd537f4a775a1c135a68f294df3917980943.1762513240.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
generated by cgit (git 2.34.1) at 2026-01-06 06:56:33 +0000