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2021-06-01drm/amdgpu: optimize code about format string in gfx_v10_0_init_microcode()Kevin Wang
the memset() and snprintf() is not necessary. Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-01drm/amdgpu: fix sdma firmware version error in sriovKevin Wang
Re-adjust the function return order to avoid empty sdma version in the sriov environment. (read amdgpu_firmware_info) Signed-off-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-01drm/amdgpu: enable smart shift on dGPU (v5)Sathishkumar S
enable smart shift on dGPU if it is part of HG system and the platform supports ATCS method to handle power shift. V2: avoid psc updates in baco enter and exit (Lijo) fix alignment (Shashank) V3: rebased on unified ATCS handling. (Alex) V4: check for return value and warn on failed update (Shashank) return 0 if device does not support smart shift. (Lizo) V5: rebased on ATPX/ATCS structures global (Alex) Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-01drm/amdgpu: flush gart changes after all BO recoveryNirmoy Das
Don't flush gart changes after recovering each BO instead do it after recovering all the BOs. Flishing gart also needed for amdgpu_ttm_alloc_gart(). v4: use containerof to retrieve adev struct. v3: rename amdgpu_gart_tlb_flush() -> amdgpu_gart_invalidate_tlb(). v2: abstract out gart tlb flushing logic to amdgpu_gart.c Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-01drm/amdgpu: do not allocate entries separatelyNirmoy Das
Allocate PD/PT entries while allocating VM BOs and use that instead of allocating those entries separately. v2: create a new var for num entries. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-01drm/amdgpu: remove unused codeNirmoy Das
Remove unused code related to shadow BO. v2: removing shadow bo ptr from base class. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-01drm/amdgpu: switch to amdgpu_bo_vm for vm codeNirmoy Das
The subclass, amdgpu_bo_vm is intended for PT/PD BOs which are also shadowed, so switch to amdgpu_bo_vm BO for PT/PD BOs. v4: update amdgpu_vm_update_funcs to accept amdgpu_bo_vm. v3: simplify code. check also if shadow bo exist instead of checking bo only type. v2: squash three related patches. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-01drm/admgpu: add two shadow BO helper functionsNirmoy Das
Add amdgpu_bo_add_to_shadow_list() to handle shadow list additions and amdgpu_bo_shadowed() to check if a BO is shadowed. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-01drm/amdgpu: move shadow bo validation to VM codeNirmoy Das
Do the shadow bo validation in the VM code as VM code knows/owns shadow BOs. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-01drm/amdgpu: add amdgpu_bo_vm bo typeNirmoy Das
Add new BO subclass that will be used by amdgpu vm code. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-01drm/amdgpu: make sure we unpin the UVD BONirmoy Das
Releasing pinned BOs is illegal now. UVD 6 was missing from: commit 2f40801dc553 ("drm/amdgpu: make sure we unpin the UVD BO") Fixes: 2f40801dc553 ("drm/amdgpu: make sure we unpin the UVD BO") Cc: stable@vger.kernel.org Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-01drm/amd/pm: retain the fine grain tuning parameters after resumeXiaojian Du
This patch is to retain the fine grain tuning parameters after resume for legacy APU, it will cover Raven/Raven2/Picasso. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-01drm/amd/display: WARN_ON cleanupsNirmoy Das
Use WARN_ON() inside if-condition when possible. v2: Squash in coding style fix (Alex) Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-02Merge tag 'drm-misc-next-2021-06-01' of ↵Dave Airlie
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 5.14: UAPI Changes: * Use DRM driver names for fbdev Cross-subsystem Changes: Core Changes: * Fix leaked DMA handles * Improve documentation around DRM_CLIENT_CAP_* * Cleanups * dp_mst: Use kHz as link-rate unit during init * fourcc: Remove drm_gem_format_name() and drm_format_name_buf * gem-cma: Fix mmap for buffers with write combining * ttm: Don't override pre-set vm_ops; ttm_bo_mmap() removal and cleanups Driver Changes: * drm/amdgpu: Fix hot unplug during suspend; Implement mmap as GEM object function; Use %p4cc format-string modifier; Cleanups * drm/bridge: Cdns: Fix PM reference leak, Cleanups; Lt8912b: Fix Coccinelle warnings; Fix Kconfig dependencies; Fixes and cleanups * drm/hisilicon/kirin: Cleanups * drm/nouveau: Implement mmap as GEM object function * drm/radeon: Implement mmap as GEM object function * drm/rockchip: Remove generic drivers during init; Add scaling for RK3036 win1; Fix missing registers for RK3066 and 3188; Add alpha support for RK3036, RK3066, RK3126 and RK3188; Fixes and cleanups * drm/simpledrm: Use %p4cc: format-string modifier * drm/vmwgfx: Cleanups * fbdev/matrox: Use modern module_init() Signed-off-by: Dave Airlie <airlied@redhat.com> From: Thomas Zimmermann <tzimmermann@suse.de> Link: https://patchwork.freedesktop.org/patch/msgid/YLZOKiYE6XFmE/MH@linux-uq9g.fritz.box
2021-06-01drm/amd/display: do not dereference on NULLNirmoy Das
WARN_ON() will not kill the process so the second WARN_ON() will try to dereference NULL pointer. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-01drm/amdgpu: support atcs method powershift (v4)Sathishkumar S
add support to handle ATCS method for power shift control. used to communicate dGPU device state to SBIOS. V2: use defined acpi func for checking psc support (Lijo) fix alignment (Shashank) V3: rebased on unified ATCS handling (Alex) V4: rebased on ATPX/ATCS structures global (Alex) Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-01drm/amd/pm: use attr_update if the attr has itSathishkumar S
use attr_update if its available as part of the attribute. default_attr_update was used even if attr->attr_update is true. Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com> Reviewed-by: Shashank Sharma <Shashank.sharma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-01drm/amdgpu: free the metadata buffer for sg type BOs as wellShiwu Zhang
Since both sg and device type BOs have metadata buffer, free the buffer in both cases when to destroy BOs Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com> Acked-by: Nirmoy Das <Nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-06-01drm/amdgpu: fix metadata_size for ubo ioctl queriesShiwu Zhang
Although the kfd_ioctl_get_dmabuf_info() still fail it will indicate the caller right metadat_size useful for the same kfd ioctl next time. Signed-off-by: Shiwu Zhang <shiwu.zhang@amd.com> Reviewed-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-31drm: document minimum kernel version for DRM_CLIENT_CAP_*Simon Ser
The kernel versions including the following commits are referenced: DRM_CLIENT_CAP_STEREO_3D 61d8e3282541 ("drm: Add a STEREO_3D capability to the SET_CLIENT_CAP ioctl") DRM_CLIENT_CAP_UNIVERSAL_PLANES 681e7ec73044 ("drm: Allow userspace to ask for universal plane list (v2)") c7dbc6c9ae5c ("drm: Remove command line guard for universal planes") DRM_CLIENT_CAP_ATOMIC 88a48e297b3a ("drm: add atomic properties") 8b72ce158cf0 ("drm: Always enable atomic API") DRM_CLIENT_CAP_ASPECT_RATIO 7595bda2fb43 ("drm: Add DRM client cap for aspect-ratio") DRM_CLIENT_CAP_WRITEBACK_CONNECTORS d67b6a206507 ("drm: writeback: Add client capability for exposing writeback connectors") Signed-off-by: Simon Ser <contact@emersion.fr> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Daniel Stone <daniels@collabora.com> Acked-by: Pekka Paalanen <pekka.paalanen@collabora.com> Link: https://patchwork.freedesktop.org/patch/434202/
2021-05-31drm: clarify and linkify DRM_CLIENT_CAP_WRITEBACK_CONNECTORS docsSimon Ser
Make it clear that the client is responsible for enabling ATOMIC prior to enabling WRITEBACK_CONNECTORS. Linkify the reference to ATOMIC. Signed-off-by: Simon Ser <contact@emersion.fr> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Daniel Stone <daniels@collabora.com> Acked-by: Pekka Paalanen <pekka.paalanen@collabora.com> Link: https://patchwork.freedesktop.org/patch/434200/
2021-05-31drm: reference mode flags in DRM_CLIENT_CAP_* docsSimon Ser
In the docs for DRM_CLIENT_CAP_STEREO_3D and DRM_CLIENT_CAP_ASPECT_RATIO, reference the DRM_MODE_FLAG_* defines that get set when the cap is enabled. Signed-off-by: Simon Ser <contact@emersion.fr> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by: Daniel Stone <daniels@collabora.com> Acked-by: Pekka Paalanen <pekka.paalanen@collabora.com> Link: https://patchwork.freedesktop.org/patch/434201/
2021-05-31drm: bridge: cdns-mhdp8546: Fix PM reference leak inYu Kuai
pm_runtime_get_sync will increment pm usage counter even it failed. Forgetting to putting operation will result in reference leak here. Fix it by replacing it with pm_runtime_resume_and_get to keep usage counter balanced. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Yu Kuai <yukuai3@huawei.com> Reviewed-by: Robert Foss <robert.foss@linaro.org> Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20210531135622.3348252-1-yukuai3@huawei.com
2021-05-31drm/bridge: lt8912b: Drop unused includesLinus Walleij
The Lontium bridge is including legacy header files for GPIO but not using them. Delete the includes. Cc: Adrien Grassein <adrien.grassein@gmail.com> Cc: Robert Foss <robert.foss@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Adren Grassein <adrien.grassein@gmail.com> Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://patchwork.freedesktop.org/patch/msgid/20210529002759.468964-1-linus.walleij@linaro.org
2021-05-28drm/rockchip: vop: add PX30 version infoJohan Jonker
To reduce memory various Rockchip VOP versions share common reg structures. However more recent added SoCs not always have to same futures as the old ones. Add PX30 missing version info, so all VOP version checks work correct if needed in the future. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20210131125016.10837-1-jbx6244@gmail.com
2021-05-28drm/rockchip: cdn-dp: fix sign extension on an int multiply for a u64 resultColin Ian King
The variable bit_per_pix is a u8 and is promoted in the multiplication to an int type and then sign extended to a u64. If the result of the int multiplication is greater than 0x7fffffff then the upper 32 bits will be set to 1 as a result of the sign extension. Avoid this by casting tu_size_reg to u64 to avoid sign extension and also a potential overflow. Fixes: 1a0f7ed3abe2 ("drm/rockchip: cdn-dp: add cdn DP support for rk3399") Signed-off-by: Colin Ian King <colin.king@canonical.com> Reviewed-by: Guenter Roeck <groeck@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20200915162049.36434-1-colin.king@canonical.com
2021-05-28drm/rockchip: lvds: Fix an error handling pathChristophe JAILLET
'ret' is know to be 0 a this point. Checking the return value of 'phy_init()' and 'phy_set_mode()' was intended instead. So add the missing assignments. Fixes: cca1705c3d89 ("drm/rockchip: lvds: Add PX30 support") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/248220d4815dc8c8088cebfab7d6df5f70518438.1619881852.git.christophe.jaillet@wanadoo.fr
2021-05-28drm/rockchip: remove unused functionJiapeng Chong
Fix the following clang warning: drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c:320:20: warning: unused function 'dsi_set' [-Wunused-function]. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/1618476421-114429-1-git-send-email-jiapeng.chong@linux.alibaba.com
2021-05-28drm/rockchip: dsi: remove extra component_del() callThomas Hebb
commit cf6d100dd238 ("drm/rockchip: dsi: add dual mipi support") added this devcnt field and call to component_del(). However, these both appear to be erroneous changes left over from an earlier version of the patch. In the version merged, nothing ever modifies devcnt, meaning component_del() runs unconditionally and in addition to the component_del() calls in dw_mipi_dsi_rockchip_host_detach(). The second call fails to delete anything and produces a warning in dmesg. If we look at the previous version of the patch[1], however, we see that it had logic to calculate devcnt and call component_add() in certain situations. This was removed in v6, and the fact that the deletion code was not appears to have been an oversight. [1] https://patchwork.kernel.org/project/dri-devel/patch/20180821140515.22246-8-heiko@sntech.de/ Fixes: cf6d100dd238 ("drm/rockchip: dsi: add dual mipi support") Cc: stable@vger.kernel.org Signed-off-by: Thomas Hebb <tommyhebb@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/201385acb0eeb5dfb037afdc6a94bfbcdab97f99.1618797778.git.tommyhebb@gmail.com
2021-05-28drm/rockchip: dsi: move all lane config except LCDC mux to bind()Thomas Hebb
When we first enable the DSI encoder, we currently program some per-chip configuration that we look up in rk3399_chip_data based on the device tree compatible we match. This data configures various parameters of the MIPI lanes, including on RK3399 whether DSI1 is slaved to DSI0 in a dual-mode configuration. It also selects which LCDC (i.e. VOP) to scan out from. This causes a problem in RK3399 dual-mode configurations, though: panel prepare() callbacks run before the encoder gets enabled and expect to be able to write commands to the DSI bus, but the bus isn't fully functional until the lane and master/slave configuration have been programmed. As a result, dual-mode panels (and possibly others too) fail to turn on when the rockchipdrm driver is initially loaded. Because the LCDC mux is the only thing we don't know until enable time (and is the only thing that can ever change), we can actually move most of the initialization to bind() and get it out of the way early. That's what this change does. (Rockchip's 4.4 BSP kernel does it in mode_set(), which also avoids the issue, but bind() seems like the more correct place to me.) Tested on a Google Scarlet board (Acer Chromebook Tab 10), which has a Kingdisplay KD097D04 dual-mode panel. Prior to this change, the panel's backlight would turn on but no image would appear when initially loading rockchipdrm. If I kept rockchipdrm loaded and reloaded the panel driver, it would come on. With this change, the panel successfully turns on during initial rockchipdrm load as expected. Fixes: 2d4f7bdafd70 ("drm/rockchip: dsi: migrate to use dw-mipi-dsi bridge driver") Signed-off-by: Thomas Hebb <tommyhebb@gmail.com> Tested-by: Jonathan Liu <net147@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/55fe7f3454d8c91dc3837ba5aa741d4a0e67378f.1618797813.git.tommyhebb@gmail.com
2021-05-28drm/rockchip: cdn-dp-core: add MODULE_FIRMWARE macroPeter Robinson
The CDP DP component of the rockchip GPU driver requires firmware so define MODULE_FIRMWARE for rockchip/dptx.bin so the details are available in the module info. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20210506092951.515813-1-pbrobinson@gmail.com
2021-05-28drm/rockchip: cdn-dp-core: add missing clk_disable_unprepare() on error in ↵Yang Yingliang
cdn_dp_grf_write() After calling clk_prepare_enable(), clk_disable_unprepare() need be called when calling regmap_write() failed. Fixes: 1a0f7ed3abe2 ("drm/rockchip: cdn-dp: add cdn DP support for rk3399") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20210519134928.2696617-1-yangyingliang@huawei.com
2021-05-28drm: rockchip: set alpha_en to 0 if it is not usedAlex Bee
alpha_en should be set to 0 if it is not used, i.e. to disable alpha blending if it was enabled before and should be disabled now. Fixes: 2aae8ed1f390 ("drm/rockchip: Add per-pixel alpha support for the PX30 VOP") Signed-off-by: Alex Bee <knaerzche@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20210528130554.72191-6-knaerzche@gmail.com
2021-05-28drm: rockchip: add alpha support for RK3036, RK3066, RK3126 and RK3188Alex Bee
With commit 2aae8ed1f390 ("drm/rockchip: Add per-pixel alpha support for the PX30 VOP") alpha support was introduced for PX30's VOP. RK3036, RK3066, RK3126 and RK3188 VOPs support alpha blending in the same manner. With the exception of RK3066 all of them support pre-multiplied alpha. Signed-off-by: Alex Bee <knaerzche@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20210528130554.72191-5-knaerzche@gmail.com
2021-05-28drm: rockchip: add missing registers for RK3066Alex Bee
Add dither_up, dsp_lut_en and data_blank registers to enable their respective functionality for RK3066's VOP. While at that also fix .rb_swap and .format registers for all windows, which have to be set though RK3066_SYS_CTRL1 register. Also remove .scl from win1: Scaling is only supported on the primary plane. Signed-off-by: Alex Bee <knaerzche@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20210528130554.72191-4-knaerzche@gmail.com
2021-05-28drm: rockchip: add missing registers for RK3188Alex Bee
Add dither_up, dsp_lut_en and data_blank registers to enable their respective functionality for RK3188's VOP. While at that also fix .dsp_blank register which is (only) set with BIT24 (same as RK3066) Signed-off-by: Alex Bee <knaerzche@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20210528130554.72191-3-knaerzche@gmail.com
2021-05-28drm: rockchip: add scaling for RK3036 win1Alex Bee
Add the registers needed to make scaling work on RK3036's win1. Signed-off-by: Alex Bee <knaerzche@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20210528130554.72191-2-knaerzche@gmail.com
2021-05-28drm/rockchip: remove existing generic drivers to take over the deviceJavier Martinez Canillas
There are drivers that register framebuffer devices very early in the boot process and make use of the existing framebuffer as setup by the firmware. If one of those drivers has registered a fbdev, then the fallback fbdev of the DRM driver won't be bound to the framebuffer console. To avoid that, remove any existing generic driver and take over the graphics device. By doing that, the fb mapped to the console is switched correctly from the early fbdev to the one registered by the rockchip DRM driver: [ 40.752420] fb0: switching to rockchip-drm-fb from EFI VGA Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Tested-by: Peter Robinson <pbrobinson@gmail.com> Acked-by: Thomas Zimmermann <tzimmermann@suse.de> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://patchwork.freedesktop.org/patch/msgid/20210516074833.451643-1-javierm@redhat.com
2021-05-28drm: Fix for GEM buffers with write-combine memoryPaul Cercueil
The previous commit wrongly assumed that dma_mmap_wc() could be replaced by pgprot_writecombine() + dma_mmap_pages(). It did work on my setup, but did not work everywhere. Use dma_mmap_wc() when the buffer has the write-combine cache attribute, and dma_mmap_pages() when it has the non-coherent cache attribute. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reported-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Tested-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Fixes: cf8ccbc72d61 ("drm: Add support for GEM buffers backed by non-coherent memory") Link: https://patchwork.freedesktop.org/patch/msgid/20210527230334.151947-1-paul@crapouillou.net
2021-05-27drm/dp_mst: Use kHz as link rate units when settig source max link caps at initNikola Cornij
[why] Link rate in kHz is what is eventually required to calculate the link bandwidth, which makes kHz a more generic unit. This should also make forward-compatibility with new DP standards easier. [how] - Replace 'link rate DPCD code' with 'link rate in kHz' when used with drm_dp_mst_topology_mgr_init() - Add/remove related DPCD code conversion from/to kHz where applicable Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Acked-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210512210011.8425-2-nikola.cornij@amd.com
2021-05-27drm/amd/display: Enable support for 16 bpc fixed-point framebuffers.Mario Kleiner
This is intended to enable direct high-precision scanout and pageflip of Vulkan swapchain images in format VK_FORMAT_R16G16B16A16_UNORM. Expose DRM_FORMAT_XRGB16161616, DRM_FORMAT_ARGB16161616, DRM_FORMAT_XBGR16161616 and DRM_FORMAT_ABGR16161616 as 16 bpc unsigned normalized formats. These allow to take full advantage of the maximum precision of the display hardware, ie. currently up to 12 bpc. Searching through old AMD M56, M76 and RV630 hw programming docs suggests that these 16 bpc formats are supported by all DCE and DCN display engines, so we can expose the formats unconditionally. Successfully tested on AMD Polaris11 DCE-11.2 an RavenRidge DCN-1.0 with a HDR-10 monitor over 10 bpc DP output with spatial dithering enabled by the driver. Picture looks good, and my photometer measurement procedure confirms an effective 12 bpc color reproduction. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-27drm/amd/display: Make assert in DCE's program_bit_depth_reduction more lenient.Mario Kleiner
This is needed to avoid warnings with linebuffer depth 36 bpp. Testing on a Polaris11, DCE-11.2 on a 10 bit HDR-10 monitor showed no obvious problems, and this 12 bpc limit is consistent with what other function in the DCE bit depth reduction path use. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-27drm/amd/display: Increase linebuffer pixel depth to 36bpp.Mario Kleiner
Testing with the photometer shows that at least Raven Ridge DCN-1.0 does not achieve more than 10 bpc effective output precision with a 16 bpc unorm surface of type SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616, unless linebuffer depth is increased from LB_PIXEL_DEPTH_30BPP to LB_PIXEL_DEPTH_36BPP. Otherwise precision gets truncated somewhere to 10 bpc effective depth. Strangely this increase was not needed on Polaris11 DCE-11.2 during testing to get 12 bpc effective precision. It also is not needed for fp16 framebuffers. Tested on DCN-1.0 and DCE-11.2. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-27drm/amd/display: Add support for SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616.Mario Kleiner
Add the necessary format definition, bandwidth and pixel size mappings, prescaler setup, and pixelformat selection, following the logic already present for SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616. The new SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 is implemented as the old SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 format, but with swapped red <-> green color channel, by use of the hardware xbar. Please note that on the DCN 1/2/3 display engines, the pixelformat in hubp and dpp setup for the old SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and the new SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 was changed from format id 22 to id 26. See amd/include/navi10_enum.h for the meaning of the id's. For format 22, the display engine read the framebuffer in 16 bpc format, but truncated to the 12 bpc actually supported by later pipeline stages. However, the engine took the 12 LSB of each color component for truncation, which is incompatible with rendering at least under Vulkan, where content is 16 bit wide, and a 12 MSB alignment would be appropriate, if any. Format 20 for ARGB16161616_12MSB does work, but even better, we can choose format 26 for ARGB16161616_UNORM, keeping all 16 bits around until later stages of the display pipeline. This allows to directly consume what the rendering hw produces under Vulkan for swapchain format VK_FORMAT_R16G16B16A16_UNORM, as tested with a patched version of the current AMD open-source amdvlk driver which maps swapchain format VK_FORMAT_R16G16B16A16_UNORM onto DRM_FORMAT_XBGR16161616. The old id 22 would cause colorful pixeltrash to be displayed instead. Tested under DCN-1.0 and DCE-11.2. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-27drm/fourcc: Add 16 bpc fixed point framebuffer formats.Mario Kleiner
These are 16 bits per color channel unsigned normalized formats. They are supported by at least AMD display hw, and suitable for direct scanout of Vulkan swapchain images in the format VK_FORMAT_R16G16B16A16_UNORM. Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-27drm/i915: Add Wa_14010733141Aditya Swarup
The WA requires the following procedure for VDBox SFC reset: If (MFX-SFC usage is 1) { 1.Issue a MFX-SFC forced lock 2.Wait for MFX-SFC forced lock ack 3.Check the MFX-SFC usage bit If (MFX-SFC usage bit is 1) Reset VDBOX and SFC else Reset VDBOX Release the force lock MFX-SFC } else if(HCP+SFC usage is 1) { 1.Issue a VE-SFC forced lock 2.Wait for SFC forced lock ack 3.Check the VE-SFC usage bit If (VE-SFC usage bit is 1) Reset VDBOX else Reset VDBOX and SFC Release the force lock VE-SFC. } else Reset VDBOX - Restructure: the changes to the original code flow should stay relatively minimal; we only need to do an extra HCP check after the usual VD-MFX check and, if true, switch the register/bit we're performing the lock on.(MattR) v2: - Assign unlock mask using paired_engine->mask instead of using BIT(paired_vecs->id). (Daniele) Bspec: 52890, 53509 Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Co-developed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210526094852.286424-2-aditya.swarup@intel.com
2021-05-27drm/amdgpu/acpi: make ATPX/ATCS structures global (v2)Alex Deucher
They are global ACPI methods, so maybe the structures global in the driver. This simplified a number of things in the handling of these methods. v2: reset the handle if verify interface fails (Lijo) v3: fix compilation when ACPI is not defined. Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-27drm/amd/amdgpu:save psp ring wptr to avoid attackVictor Zhao
[Why] When some tools performing psp mailbox attack, the readback value of register can be a random value which may break psp. [How] Use a psp wptr cache machanism to aovid the change made by attack. v2: unify change and add detailed reason Signed-off-by: Victor Zhao <Victor.Zhao@amd.com> Signed-off-by: Jingwen Chen <Jingwen.Chen2@amd.com> Reviewed-by: Monk Liu <monk.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-05-27drm/amdgpu/swsmu/aldebaran: fix check in is_dpm_runningAlex Deucher
If smu_cmn_get_enabled_mask() fails, return false to be consistent with other asics. Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Lee Jones <lee.jones@linaro.org> Reviewed-by: Lee Jones <lee.jones@linaro.org>
2021-05-27drm/amd/display/modules/hdcp/hdcp_psp: Remove unused function ↵Lee Jones
'mod_hdcp_hdcp1_get_link_encryption_status()' Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/modules/hdcp/hdcp_psp.c:374:22: warning: no previous prototype for ‘mod_hdcp_hdcp1_get_link_encryption_status’ [-Wmissing-prototypes] Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-07-15 16:49:29 +0000