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2024-10-22rtnetlink: Allocate linkinfo[] as struct rtnl_newlink_tbs.Kuniyuki Iwashima
We will move linkinfo to rtnl_newlink() and pass it down to other functions. Let's pack it into rtnl_newlink_tbs. Signed-off-by: Kuniyuki Iwashima <kuniyu@amazon.com> Reviewed-by: Eric Dumazet <edumazet@google.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21Merge branch 'net-mlx5-refactor-esw-qos-to-support-generalized-operations'Paolo Abeni
Tariq Toukan says: ==================== net/mlx5: Refactor esw QoS to support generalized operations This patch series from the team to mlx5 core driver consists of one main QoS part followed by small misc patches. This main part (patches 1 to 11) by Carolina refactors the QoS handling to generalize operations on scheduling groups and vports. These changes are necessary to support new features that will extend group functionality, introduce new group types, and support deeper hierarchies. Additionally, this refactor updates the terminology from "group" to "node" to better reflect the hardware’s rate hierarchy and its use of scheduling element nodes. Simplify group scheduling element creation: - net/mlx5: Refactor QoS group scheduling element creation Refactor to support generalized operations for QoS: - net/mlx5: Introduce node type to rate group structure - net/mlx5: Add parent group support in rate group structure - net/mlx5: Restrict domain list insertion to root TSAR ancestors - net/mlx5: Rename vport QoS group reference to parent - net/mlx5: Introduce node struct and rename group terminology to node - net/mlx5: Refactor vport scheduling element creation function - net/mlx5: Refactor vport QoS to use scheduling node structure - net/mlx5: Remove vport QoS enabled flag Support generalized operations for QoS elements: - net/mlx5: Simplify QoS scheduling element configuration - net/mlx5: Generalize QoS operations for nodes and vports On top, patch 12 by Moshe handles FW request to move to drop mode. In patch 13, Benjamin Poirier removes an empty eswitch flow table when not used, which improves packet processing performance. Patches 14 and 15 by Moshe are small field renamings as preparation for future fields addition to these structures. Series generated against: commit c531f2269a53 ("net: bcmasp: enable SW timestamping") ==================== Link: https://patch.msgid.link/20241016173617.217736-1-tariqt@nvidia.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net/mlx5: fs, rename modify header struct member actionMoshe Shemesh
As preparation for HW Steering support, rename modify header struct member action to fs_dr_action, to distinguish from fs_hws_action which will be added. Add a pointer where needed to keep code line shorter and more readable. Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net/mlx5: fs, rename packet reformat struct member actionMoshe Shemesh
As preparation for HW Steering support, rename packet reformat struct member action to fs_dr_action, to distinguish from fs_hws_action which will be added. Add a pointer where needed to keep code line shorter and more readable. Reviewed-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Moshe Shemesh <moshe@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net/mlx5: Only create VEPA flow table when in VEPA modeBenjamin Poirier
Currently, when VFs are created, two flow tables are added for the eswitch: the "fdb" table, which contains rules for each VF and the "vepa_fdb" table. In the default VEB mode, the vepa_fdb table is empty. When switching to VEPA mode, flow steering rules are added to vepa_fdb. Even though the vepa_fdb table is empty in VEB mode, its presence adds some cost to packet processing. In some workloads, this leads to drops which are reported by the rx_discards_phy ethtool counter. In order to improve performance, only create vepa_fdb when in VEPA mode. Tests were done on a ConnectX-6 Lx adapter forwarding 64B packets between both ports using dpdk-testpmd. Numbers are Rx-pps for each port, as reported by testpmd. Without changes: traffic to unknown mac testpmd on PF numvfs=0,0 35257998,35264499 numvfs=1,1 24590124,24590888 testpmd on VF with numvfs=1,1 20434338,20434887 traffic to VF mac testpmd on VF with numvfs=1,1 30341014,30340749 With changes: traffic to unknown mac testpmd on PF numvfs=0,0 35404361,35383378 numvfs=1,1 29801247,29790757 testpmd on VF with numvfs=1,1 24310435,24309084 traffic to VF mac testpmd on VF with numvfs=1,1 34811436,34781706 Signed-off-by: Benjamin Poirier <bpoirier@nvidia.com> Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com> Reviewed-by: Saeed Mahameed <saeedm@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net/mlx5: Add sync reset drop mode supportMoshe Shemesh
On sync reset flow, firmware may request a PF, which already acknowledged the unload event, to move to drop mode. Drop mode means that this PF will reduce polling frequency, as this PF is not going to have another active part in the reset, but only reload back after the reset. Signed-off-by: Moshe Shemesh <moshe@nvidia.com> Reviewed-by: Aya Levin <ayal@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net/mlx5: Generalize QoS operations for nodes and vportsCarolina Jubran
Refactor QoS normalization and rate calculation functions to operate on mlx5_esw_sched_node, allowing for generalized handling of both vports and nodes. Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net/mlx5: Simplify QoS scheduling element configurationCarolina Jubran
Simplify the configuration of QoS scheduling elements by removing the separate functions `esw_qos_node_config` and `esw_qos_vport_config`. Instead, directly use the existing `esw_qos_sched_elem_config` function for both nodes and vports. This unification helps in generalizing operations on scheduling elements nodes. Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net/mlx5: Remove vport QoS enabled flagCarolina Jubran
Remove the `enabled` flag from the `vport->qos` struct, as QoS now relies solely on the `sched_node` pointer to determine whether QoS features are in use. Currently, the vport `qos` struct consists only of the `sched_node`, introducing an unnecessary two-level reference. However, the qos struct is retained as it will be extended in future patches to support new QoS features. Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net/mlx5: Refactor vport QoS to use scheduling node structureCarolina Jubran
Refactor the vport QoS structure by moving group membership and scheduling details into the `mlx5_esw_sched_node` structure. This change consolidates the vport into the rate hierarchy by unifying the handling of different types of scheduling element nodes. In addition, add a direct reference to the mlx5_vport within the mlx5_esw_sched_node structure, to ensure that the vport is easily accessible when a scheduling node is associated with a vport. Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net/mlx5: Refactor vport scheduling element creation functionCarolina Jubran
Modify the vport scheduling element creation function to get the parent node directly, aligning it with the group creation function. This ensures a consistent flow for scheduling elements creation, as the parent nodes already contain the device and parent element index. Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net/mlx5: Introduce node struct and rename group terminology to nodeCarolina Jubran
Introduce the `mlx5_esw_sched_node` struct, consolidating all rate hierarchy related details, including membership and scheduling parameters. Since the group concept aligns with the `mlx5_esw_sched_node`, replace the `mlx5_esw_rate_group` struct with it and rename the "group" terminology to "node" throughout the rate hierarchy. All relevant code paths and structures have been updated to use the "node" terminology accordingly, laying the groundwork for future patches that will unify the handling of different types of members within the rate hierarchy. Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net/mlx5: Rename vport QoS group reference to parentCarolina Jubran
Rename the `group` field in the `mlx5_vport` structure to `parent` to clarify the vport's role as a member of a parent group and distinguish it from the concept of a general group. Additionally, rename `group_entry` to `parent_entry` to reflect this update. This distinction will be important for handling more complex group structures and scheduling elements. Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net/mlx5: Restrict domain list insertion to root TSAR ancestorsCarolina Jubran
Update the logic for adding rate groups to the E-Switch domain list, ensuring only groups with the root Transmit Scheduling Arbiter as their parent are included. Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net/mlx5: Add parent group support in rate group structureCarolina Jubran
Introduce a `parent` field in the `mlx5_esw_rate_group` structure to support hierarchical group relationships. The `parent` can reference another group or be set to `NULL`, indicating the group is connected to the root TSAR. This change enables the ability to manage groups in a hierarchical structure for future enhancements. Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net/mlx5: Introduce node type to rate group structureCarolina Jubran
Introduce the `sched_node_type` enum to represent both the group and its members as scheduling nodes in the rate hierarchy. Add the `type` field to the rate group structure to specify the type of the node membership in the rate hierarchy. Generalize comments to reflect this flexibility within the rate group structure. Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net/mlx5: Refactor QoS group scheduling element creationCarolina Jubran
Introduce `esw_qos_create_group_sched_elem` to handle the creation of group scheduling elements for E-Switch QoS, Transmit Scheduling Arbiter (TSAR). This reduces duplication and simplifies code for TSAR setup. Signed-off-by: Carolina Jubran <cjubran@nvidia.com> Reviewed-by: Cosmin Ratiu <cratiu@nvidia.com> Signed-off-by: Tariq Toukan <tariqt@nvidia.com> Reviewed-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21Merge branch 'add-support-of-hibmcge-ethernet-driver'Paolo Abeni
Jijie Shao says: ==================== Add support of HIBMCGE Ethernet Driver This patch set adds the support of Hisilicon BMC Gigabit Ethernet Driver. This patch set includes basic Rx/Tx functionality. It also includes the registration and interrupt codes. This work provides the initial support to the HIBMCGE and would incrementally add features or enhancements. ==================== Link: https://patch.msgid.link/20241015123516.4035035-1-shaojijie@huawei.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net: hibmcge: Add maintainer for hibmcgeJijie Shao
Add myself as the maintainer for the hibmcge ethernet driver. Signed-off-by: Jijie Shao <shaojijie@huawei.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net: hibmcge: Add a Makefile and update Kconfig for hibmcgeJijie Shao
Add a Makefile and update Kconfig to build hibmcge driver. Signed-off-by: Jijie Shao <shaojijie@huawei.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net: hibmcge: Implement some ethtool_ops functionsJijie Shao
Implement the .get_drvinfo .get_link .get_link_ksettings to get the basic information and working status of the driver. Implement the .set_link_ksettings to modify the rate, duplex, and auto-negotiation status. Signed-off-by: Jijie Shao <shaojijie@huawei.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net: hibmcge: Implement rx_poll function to receive packetsJijie Shao
Implement rx_poll function to read the rx descriptor after receiving the rx interrupt. Adjust the skb based on the descriptor to complete the reception of the packet. Signed-off-by: Jijie Shao <shaojijie@huawei.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net: hibmcge: Implement .ndo_start_xmit functionJijie Shao
Implement .ndo_start_xmit function to fill the information of the packet to be transmitted into the tx descriptor, and then the hardware will transmit the packet using the information in the tx descriptor. In addition, we also implemented the tx_handler function to enable the tx descriptor to be reused, and .ndo_tx_timeout function to print some information when the hardware is busy. Signed-off-by: Jijie Shao <shaojijie@huawei.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net: hibmcge: Implement some .ndo functionsJijie Shao
Implement the .ndo_open() .ndo_stop() .ndo_set_mac_address() and .ndo_change_mtu functions(). And .ndo_validate_addr calls the eth_validate_addr function directly Signed-off-by: Jijie Shao <shaojijie@huawei.com> Reviewed-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net: hibmcge: Add interrupt supported in this moduleJijie Shao
The driver supports four interrupts: TX interrupt, RX interrupt, mdio interrupt, and error interrupt. Actually, the driver does not use the mdio interrupt. Therefore, the driver does not request the mdio interrupt. The error interrupt distinguishes different error information by using different masks. To distinguish different errors, the statistics count is added for each error. To ensure the consistency of the code process, masks are added for the TX interrupt and RX interrupt. This patch implements interrupt request, and provides a unified entry for the interrupt handler function. However, the specific interrupt handler function of each interrupt is not implemented currently. Because of pcim_enable_device(), the interrupt vector is already device managed and does not need to be free actively. Signed-off-by: Jijie Shao <shaojijie@huawei.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net: hibmcge: Add mdio and hardware configuration supported in this moduleJijie Shao
Implements the C22 read and write PHY registers interfaces. Some hardware interfaces related to the PHY are also implemented in this patch. Signed-off-by: Jijie Shao <shaojijie@huawei.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net: hibmcge: Add read/write registers supported through the bar spaceJijie Shao
Add support for to read and write registers through the pic bar space. Some driver parameters, such as mac_id, are determined by the board form. Therefore, these parameters are initialized from the register as device specifications. the device specifications register are initialized and written by bmc. driver will read these registers when loading. Signed-off-by: Jijie Shao <shaojijie@huawei.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net: hibmcge: Add pci table supported in this moduleJijie Shao
Add pci table supported in this module, and implement pci_driver function to initialize this driver. hibmcge is a passthrough network device. Its software runs on the host side, and the MAC hardware runs on the BMC side to reduce the host CPU area. The software interacts with the MAC hardware through the PCIe. ┌─────────────────────────┐ │ HOST CPU network device │ │ ┌──────────────┐ │ │ │hibmcge driver│ │ │ └─────┬─┬──────┘ │ │ │ │ │ │HOST ┌───┴─┴───┐ │ │ │ PCIE RC │ │ └──────┴───┬─┬───┴────────┘ │ │ PCIE │ │ ┌──────┬───┴─┴───┬────────┐ │ │ PCIE EP │ │ │BMC └───┬─┬───┘ │ │ │ │ │ │ ┌────────┴─┴──────────┐ │ │ │ GE │ │ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ MAC │ │ MAC │ │ │ └─┴─┼─────┼────┼─────┼──┴─┘ │ PHY │ │ PHY │ └─────┘ └─────┘ Signed-off-by: Jijie Shao <shaojijie@huawei.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21net: sfp: change quirks for Alcatel Lucent G-010S-PShengyu Qu
Seems Alcatel Lucent G-010S-P also have the same problem that it uses TX_FAULT pin for SOC uart. So apply sfp_fixup_ignore_tx_fault to it. Signed-off-by: Shengyu Qu <wiagn233@outlook.com> Link: https://patch.msgid.link/TYCPR01MB84373677E45A7BFA5A28232C98792@TYCPR01MB8437.jpnprd01.prod.outlook.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-21Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netPaolo Abeni
Cross-merge networking fixes after downstream PR (net-6.12-rc4). Conflicts: 107a034d5c1e ("net/mlx5: qos: Store rate groups in a qos domain") 1da9cfd6c41c ("net/mlx5: Unregister notifier on eswitch init failure") Signed-off-by: Paolo Abeni <pabeni@redhat.com>
2024-10-20net: ftgmac100: correct the phy interface of NC-SI modeJacky Chou
In NC-SI specification, NC-SI is using RMII, not MII. Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Message-ID: <20241018053331.1900100-1-jacky_chou@aspeedtech.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-20eth: Fix typo 'accelaration'. 'exprienced' and 'rewritting'WangYuli
There are some spelling mistakes of 'accelaration', 'exprienced' and 'rewritting' in comments which should be 'acceleration', 'experienced' and 'rewriting'. Suggested-by: Simon Horman <horms@kernel.org> Link: https://lore.kernel.org/all/20241017162846.GA51712@kernel.org/ Signed-off-by: WangYuli <wangyuli@uniontech.com> Reviewed-by: Donald Hunter <donald.hunter@gmail.com> Reviewed-by: Simon Horman <horms@kernel.org> Message-ID: <90D42CB167CA0842+20241018021910.31359-1-wangyuli@uniontech.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-20r8169: enable EEE at 2.5G per default on RTL8125BHeiner Kallweit
Register a6d/12 is shadowing register MDIO_AN_EEE_ADV2. So this line disables advertisement of EEE at 2.5G. Latest vendor driver r8125 doesn't do this (any longer?), so this mode seems to be safe. EEE saves quite some energy, therefore enable this mode per default. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Simon Horman <horms@kernel.org> Message-ID: <95dd5a0c-09ea-4847-94d9-b7aa3063e8ff@gmail.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-20net: phy: realtek: add RTL8125D-internal PHYHeiner Kallweit
The first boards show up with Realtek's RTL8125D. This MAC/PHY chip comes with an integrated 2.5Gbps PHY with ID 0x001cc841. It's not clear yet whether there's an external version of this PHY and how Realtek calls it, therefore use the numeric id for now. Link: https://lore.kernel.org/netdev/2ada65e1-5dfa-456c-9334-2bc51272e9da@gmail.com/T/ Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Message-ID: <7d2924de-053b-44d2-a479-870dc3878170@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-20net: airoha: Reset BQL stopping the netdeviceLorenzo Bianconi
Run airoha_qdma_cleanup_tx_queue() in ndo_stop callback in order to unmap pending skbs. Moreover, reset BQL txq state stopping the netdevice, Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Reviewed-by: Hariprasad Kelam <hkelam@marvell.com> Message-ID: <20241017-airoha-en7581-reset-bql-v1-1-08c0c9888de5@kernel.org> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-20net: phy: mediatek-ge-soc: Propagate error code correctly in cal_cycle()SkyLake.Huang
This patch propagates error code correctly in cal_cycle() and improve with FIELD_GET(). Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> Reviewed-by: Simon Horman <horms@kernel.org> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-20net: phy: mediatek-ge-soc: Shrink line wrapping to 80 charactersSkyLake.Huang
This patch shrinks line wrapping to 80 chars. Also, in tx_amp_fill_result(), use FIELD_PREP() to prettify code. Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> Reviewed-by: Simon Horman <horms@kernel.org> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-20net: phy: mediatek-ge-soc: Fix coding styleSkyLake.Huang
This patch fixes spelling errors, re-arrange vars with reverse Xmas tree and remove unnecessary parens in mediatek-ge-soc.c. Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> Reviewed-by: Simon Horman <horms@kernel.org> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-20r8169: remove rtl_dash_loop_wait_high/lowHeiner Kallweit
Remove rtl_dash_loop_wait_high/low to simplify the code. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Simon Horman <horms@kernel.org> Message-ID: <fb8c490c-2d92-48f5-8bbf-1fc1f2ee1649@gmail.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-20r8169: avoid duplicated messages if loading firmware fails and switch to ↵Heiner Kallweit
warn level In case of a problem with firmware loading we inform at the driver level, in addition the firmware load code itself issues warnings. Therefore switch to firmware_request_nowarn() to avoid duplicated error messages. In addition switch to warn level because the firmware is optional and typically just fixes compatibility issues. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Simon Horman <horms@kernel.org> Message-ID: <d9c5094c-89a6-40e2-b5fe-8df7df4624ef@gmail.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-20r8169: replace custom flag with disable_work() et alHeiner Kallweit
So far we use a custom flag to define when a task can be scheduled and when not. Let's use the standard mechanism with disable_work() et al instead. Note that in rtl8169_close() we can remove the call to cancel_work() because we now call disable_work_sync() in rtl8169_down() already. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-20r8169: don't take RTNL lock in rtl_task()Heiner Kallweit
There's not really a benefit here in taking the RTNL lock. The task handler does exception handling only, so we're in trouble anyway when we come here, and there's no need to protect against e.g. a parallel ethtool call. A benefit of removing the RTNL lock here is that we now can synchronously cancel the workqueue from a context holding the RTNL mutex. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-20eth: fbnic: add CONFIG_PTP_1588_CLOCK_OPTIONAL dependencyArnd Bergmann
fbnic fails to link as built-in when PTP support is in a loadable module: aarch64-linux-ld: drivers/net/ethernet/meta/fbnic/fbnic_ethtool.o: in function `fbnic_get_ts_info': fbnic_ethtool.c:(.text+0x428): undefined reference to `ptp_clock_index' aarch64-linux-ld: drivers/net/ethernet/meta/fbnic/fbnic_time.o: in function `fbnic_time_start': fbnic_time.c:(.text+0x820): undefined reference to `ptp_schedule_worker' aarch64-linux-ld: drivers/net/ethernet/meta/fbnic/fbnic_time.o: in function `fbnic_ptp_setup': fbnic_time.c:(.text+0xa68): undefined reference to `ptp_clock_register' Add the appropriate dependency to enforce this. Fixes: 6a2b3ede9543 ("eth: fbnic: add RX packets timestamping support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Vadim Fedorenko <vadim.fedorenko@linux.dev> Message-ID: <20241016062303.2551686-1-arnd@kernel.org> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-18net: vxlan: update the document for vxlan_snoop()Menglong Dong
The function vxlan_snoop() returns drop reasons now, so update the document of it too. Signed-off-by: Menglong Dong <dongml2@chinatelecom.cn> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-10-18net: vxlan: replace VXLAN_INVALID_HDR with VNI_NOT_FOUNDMenglong Dong
Replace the drop reason "SKB_DROP_REASON_VXLAN_INVALID_HDR" with "SKB_DROP_REASON_VXLAN_VNI_NOT_FOUND" in encap_bypass_if_local(), as the latter is more accurate. Fixes: 790961d88b0e ("net: vxlan: use kfree_skb_reason() in encap_bypass_if_local()") Signed-off-by: Menglong Dong <dongml2@chinatelecom.cn> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2024-10-17net: airoha: Fix typo in REG_CDM2_FWD_CFG configurationLorenzo Bianconi
Fix typo in airoha_fe_init routine configuring CDM2_OAM_QSEL_MASK field of REG_CDM2_FWD_CFG register. This bug is not introducing any user visible problem since Frame Engine CDM2 port is used just by the second QDMA block and we currently enable just QDMA1 block connected to the MT7530 dsa switch via CDM1 port. Introduced by commit 23020f049327 ("net: airoha: Introduce ethernet support for EN7581 SoC") Reported-by: ChihWei Cheng <chihwei.cheng@airoha.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Reviewed-by: Simon Horman <horms@kernel.org> Message-ID: <20241015-airoha-eth-cdm2-fixes-v1-1-9dc6993286c3@kernel.org> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-17net: ravb: Add VLAN checksum supportPaul Barker
The GbEth IP supports offloading checksum calculation for VLAN-tagged packets, provided that the EtherType is 0x8100 and only one VLAN tag is present. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-17net: ravb: Enable IPv6 TX checksum offload for GbEthPaul Barker
The GbEth IP supports offloading IPv6 TCP, UDP & ICMPv6 checksums in the TX path. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-17net: ravb: Enable IPv6 RX checksum offloading for GbEthPaul Barker
The GbEth IP supports offloading IPv6 TCP, UDP & ICMPv6 checksums in the RX path. Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru> Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
2024-10-17net: ravb: Simplify UDP TX checksum offloadPaul Barker
The GbEth IP will pass through a zero UDP checksum without asserting any error flags so we do not need to resort to software checksum calculation in this case. Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru> Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Signed-off-by: Andrew Lunn <andrew@lunn.ch>
generated by cgit (git 2.34.1) at 2025-07-18 00:03:28 +0000