summaryrefslogtreecommitdiff
path: root/Documentation
AgeCommit message (Collapse)Author
2025-05-19arm64: errata: Work around AmpereOne's erratum AC04_CPU_23D Scott Phillips
On AmpereOne AC04, updates to HCR_EL2 can rarely corrupt simultaneous translations for data addresses initiated by load/store instructions. Only instruction initiated translations are vulnerable, not translations from prefetches for example. A DSB before the store to HCR_EL2 is sufficient to prevent older instructions from hitting the window for corruption, and an ISB after is sufficient to prevent younger instructions from hitting the window for corruption. Signed-off-by: D Scott Phillips <scott@os.amperecomputing.com> Reviewed-by: Oliver Upton <oliver.upton@linux.dev> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Link: https://lore.kernel.org/r/20250513184514.2678288-1-scott@os.amperecomputing.com Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-05-19dt-bindings: mmc: spacemit,sdhci: add support for K1 SoCYixun Lan
Add support for the SD/eMMC Host Controller found in SpacemiT K1 SoC, The controller supports data transmission of MMC, SDIO, SD protocol. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Yixun Lan <dlan@gentoo.org> Link: https://lore.kernel.org/r/20250509-20-k1-sdhci-v3-1-526c35feaa20@gentoo.org Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-05-19Fix spelling error for 'parallel'Anish Dabhane
Signed-off-by: Anish Dabhane <anishdabhane71@gmail.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Message-ID: <20250518140107.21310-1-anishdabhane71@gmail.com>
2025-05-19docs: admin-guide: fix typos in reporting-issues.rstShivam Sharma
Correct pin-point to pinpoint, If that the case to If that is the case, and its only slightly modified to it's only slightly modified in Documentation/admin-guide/reporting-issues.rst for proper spelling and grammar. Signed-off-by: Shivam Sharma <10sharmashivam@gmail.com> Acked-by: Thorsten Leemhuis <linux@leemhuis.info> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Message-ID: <20250518172658.6983-1-10sharmashivam@gmail.com>
2025-05-19ASoC: dt-bindings: qcom,sm8250: Add QCS9100 and QCS9075 sound cardMohammad Rafi Shaik
Document the bindings for the Qualcomm QCS9100 and QCS9075 board specific sound card. The bindings are the same as for other newer Qualcomm ADSP sound cards, thus keep them in existing qcom,sm8250.yaml file, even though Linux driver is separate. Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com> Link: https://patch.msgid.link/20250519083244.4070689-2-mohammad.rafi.shaik@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19dt-binding: mmc: microchip,sdhci-pic32: convert text based binding to json ↵Charan Pedumuru
schema Update text binding to YAML. Changes during conversion: Add appropriate include statements for interrupts and clock-names to resolve errors identified by `dt_binding_check` and `dtbs_check`. Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250507-mchp-sdhci-v1-2-ed29de05295a@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2025-05-19KVM: arm64: Document NV caps and vcpu flagsMarc Zyngier
Describe the two new vcpu flags that control NV, together with the capabilities that advertise them. Reviewed-by: Oliver Upton <oliver.upton@linux.dev> Reviewed-by: Joey Gouly <joey.gouly@arm.com> Link: https://lore.kernel.org/r/20250514103501.2225951-18-maz@kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2025-05-19dt-bindings: crypto: Convert Marvell CESA to DT schemaRob Herring (Arm)
Convert the Marvell CESA binding to DT schema format. The marvell-cesa.txt and mv_cesa.txt are duplicate bindings. The clock properties are quite varied for each platform hence the if/then schemas. The old binding was fairly accurate with reality. The original binding didn't mention there is 1 interrupt per CESA engine. Based on users, there's a maximum of 2 engines. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-05-19dt-bindings: crypto: Convert img,hash-accelerator to DT schemaRob Herring (Arm)
Convert the Imagination Technologies hardware hash accelerator binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-05-19dt-bindings: crypto: Convert hisilicon,hip0{6,7}-sec to DT schemaRob Herring (Arm)
Convert the HiSilicon HIP06/7 Security Accelerator binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-05-19dt-bindings: crypto: Convert brcm,spum-crypto to DT schemaRob Herring (Arm)
Convert the Broadcom SPUM/SPU2 binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-05-19dt-bindings: crypto: Convert axis,artpec6-crypto to DT schemaRob Herring (Arm)
Convert the Axis Crypto engine binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-05-19dt-bindings: crypto: Convert amd,ccp-seattle-v1a to DT schemaRob Herring (Arm)
Convert the AMD Cryptographic Coprocessor binding to DT schema format. It's a straight forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-05-19dt-bindings: crypto: Drop obsolete mediatek,eip97-cryptoRob Herring (Arm)
The mediatek,eip97-crypto binding is half abandoned. The driver was dropped in 2020 as the Mediatek platforms use InsideSecure block and the driver for it. All the platforms except MT7623 were updated. A patch to update it was submitted, but never addressed the review comments. Link: https://lore.kernel.org/all/20210303080923.16761-1-vic.wu@mediatek.com/ Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-05-19dt-bindings: crypto: fsl,sec-v4.0: Add fsl,sec-v6.0Rob Herring (Arm)
The fsl,sec-v6.0 binding is the same as the fsl,sec-v4.0 binding, so add it to the existing schema and drop the old .txt binding. The compatibles in the .txt binding don't match the 1 user. Follow the user for the schema. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-05-19crypto: qat - enable reporting of error counters for GEN6 devicesSuman Kumar Chakraborty
Enable the reporting of error counters through sysfs for QAT GEN6 devices and update the ABI documentation. This enables the reporting of the following: - errors_correctable - hardware correctable errors that allow the system to recover without data loss. - errors_nonfatal: errors that can be isolated to specific in-flight requests. - errors_fatal: errors that cannot be contained to a request, requiring a Function Level Reset (FLR) upon occurrence. Signed-off-by: Suman Kumar Chakraborty <suman.kumar.chakraborty@intel.com> Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2025-05-19Merge tag 'drm-msm-next-2025-05-16' of ↵Dave Airlie
https://gitlab.freedesktop.org/drm/msm into drm-next Updates for v6.16 CI: - uprev mesa GPU: - ACD (Adaptive Clock Distribution) support for X1-85. This is required enable the higher frequencies. - Drop fictional `address_space_size`. For some older devices, the address space size is limited to 4GB to avoid potential 64b rollover math problems in the fw. For these, an `ADRENO_QUIRK_4GB_VA` quirk is added. For everyone else we get the address space size from the SMMU `ias` (input address sizes), which is usually 48b. - Improve robustness when GMU HFI responses time out - Fix crash when throttling GPU immediately during boot - Fix for rgb565_predicator on Adreno 7c3 - Remove `MODULE_FIRMWARE()`s for GPU, the GPU can load the firmware after probe and having partial set of fw (ie. sqe+gmu but not zap) causes problems MDSS: - Added SAR2130P support to MDSS driver DPU: - Changed to use single CTL path for flushing on DPU 5.x+ - Improved SSPP allocation code to allow sharing of SSPP between planes - Enabled SmartDMA on SM8150, SC8180X, SC8280XP, SM8550 - Added SAR2130P support - Disabled DSC support on MSM8937, MSM8917, MSM8953, SDM660 - Misc fixes DP: - Switch to use new helpers for DP Audio / HDMI codec handling - Fixed LTTPR handling DSI: - Added support for SA8775P - Added SAR2130P support MDP4: - Fixed LCDC / LVDS controller on HDMI: - Switched to use new helpers for ACR data - Fixed old standing issue of HPD not working in some cases Signed-off-by: Dave Airlie <airlied@redhat.com> From: Rob Clark <robdclark@gmail.com> Link: https://lore.kernel.org/r/CAF6AEGv2Go+nseaEwRgeZbecet-h+Pf2oBKw1CobCF01xu2XVg@mail.gmail.com
2025-05-19Merge tag 'amd-drm-next-6.16-2025-05-16' of ↵Dave Airlie
https://gitlab.freedesktop.org/agd5f/linux into drm-next amdgpu: - Misc code cleanups - UserQ fixes - MALL reporting fix - DP AUX fixes - DCN 3.5 fixes - DP MST fixes - DC DMI quirks cleanup - RAS fixes - SR-IOV updates - GC 9.5 updates - Misc display fixes - VCN 4.0.5 powergating race fix - SMU 13.x updates - Paritioning fixes - VCN 5.0.1 SR-IOV updates - JPEG 5.0.1 SR-IOV updates amdkfd: - Fix spurious warning in interrupt code - XNACK fixes radeon: - CIK doorbell cleanup Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexander.deucher@amd.com> Link: https://lore.kernel.org/r/20250516204609.2437472-1-alexander.deucher@amd.com
2025-05-19dt-bindings: riscv: sophgo: Add SG2044 compatible stringInochi Amaoto
Add compatible string for the Sophgo SG2044 SoC and the SRD3-10 board. Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/20250413223507.46480-10-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-05-19dt-bindings: interrupt-controller: Add Sophgo SG2044 PLICInochi Amaoto
The SG2044 implement a standard T-HEAD C900 PLIC, which is already supported by the kernel. Add compatible string for Sophgo SG2044 plic. Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250413223507.46480-5-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-05-19dt-bindings: interrupt-controller: Add Sophgo SG2044 CLINT mswiInochi Amaoto
As SG2044 also implements an enhanced ACLINT as SG2042, add necessary compatible string for SG2044 SoC. Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250413223507.46480-4-inochiama@gmail.com Signed-off-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-05-17x86/mm/64: Make 5-level paging support unconditionalKirill A. Shutemov
Both Intel and AMD CPUs support 5-level paging, which is expected to become more widely adopted in the future. All major x86 Linux distributions have the feature enabled. Remove CONFIG_X86_5LEVEL and related #ifdeffery for it to make it more readable. Suggested-by: Borislav Petkov <bp@alien8.de> Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: https://lore.kernel.org/r/20250516123306.3812286-4-kirill.shutemov@linux.intel.com
2025-05-16netlink: specs: rt-link: add C naming info for ovpnJakub Kicinski
C naming info for OVPN which was added since I adjusted the existing attrs. Also add missing reference to a header needed for a bridge struct. Reviewed-by: Donald Hunter <donald.hunter@gmail.com> Link: https://patch.msgid.link/20250515231650.1325372-2-kuba@kernel.org Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2025-05-16irqdomain: Fix kernel-doc and add it to DocumentationJiri Slaby (SUSE)
irqdomain.c's kernel-doc exists, but is not plugged into Documentation/ yet. Before plugging it in, fix it first: irq_domain_get_irq_data() and irq_domain_set_info() were documented twice. Identically, by both definitions for CONFIG_IRQ_DOMAIN_HIERARCHY and !CONFIG_IRQ_DOMAIN_HIERARCHY. Therefore, switch the second kernel-doc into an ordinary comment -- change "/**" to simple "/*". This avoids sphinx's: WARNING: Duplicate C declaration Next, in commit b7b377332b96 ("irqdomain: Fix the kernel-doc and plug it into Documentation"), irqdomain.h's (header) kernel-doc was added into core-api/genericirq.rst. But given the amount of irqdomain functions and structures, move all these to core-api/irq/irq-domain.rst now. Finally, add these newly fixed irqdomain.c's (source) docs there as well. Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250319092951.37667-58-jirislaby@kernel.org
2025-05-16Documentation: irqdomain: Update itJiri Slaby (SUSE)
The irqdomain documentaion became obsolete over time. Update and extend it a bit with respect to the current code and HW. Most notably the doubled documentation of irq_domain (from .rst and .h) was unified and let only in .rst. A reference link was added to .h. Furthermore: * Add some 'struct' keywords, so that the respective structs are hyperlinked * :c:member: use where appropriate to mark a member of a struct * Rephrase some wording to improve readability/understanding Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250319092951.37667-57-jirislaby@kernel.org
2025-05-16Documentation: irq-domain.rst: Simple improvementsJiri Slaby (SUSE)
The improvements include: * Capitals in headlines. * Add commas: for easier reading, it is always desired to add commas at some places in text. Like before adverbs or after fronted sentences. * 3rd person -> add 's' to verbs. * End some sentences with period and start a new one. Avoid thus heavy sentences. [ tglx: Fix up subject prefix ] Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250319092951.37667-56-jirislaby@kernel.org
2025-05-16Documentation: irq/concepts: Minor improvementsJiri Slaby (SUSE)
Just note in the docs: 1) A PCI device as an example for shared interrupts 2) A sparse tree can be used for interrupts too 3) i8259s which have 8 pins [ tglx: Fix up subject prefix ] Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250319092951.37667-55-jirislaby@kernel.org
2025-05-16Documentation: irq/concepts: Add commas and reflowJiri Slaby (SUSE)
For easier reading, it is always desired to add commas at some places in text. Like before adverbs or after fronted sentences. [ tglx: Fix up subject prefix ] Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250319092951.37667-54-jirislaby@kernel.org
2025-05-16irqdomain: Drop irq_linear_revmap()Jiri Slaby (SUSE)
irq_linear_revmap() is deprecated and unused now. So remove it. Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250319092951.37667-50-jirislaby@kernel.org
2025-05-16irqdomain: Drop irq_domain_add_*() functionsJiri Slaby (SUSE)
Most irq_domain_add_*() functions are unused now, so drop them. The remaining ones are moved to the deprecated section and will be removed during the merge window after the patches in various trees have been merged. Note: The Chinese docs are touched but unfinished. I cannot parse those. [ tglx: Remove the leftover in irq-domain.rst and handle merge logistics ] Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250319092951.37667-41-jirislaby@kernel.org
2025-05-16powerpc: Switch irq_domain_add_nomap() to use fwnodeJiri Slaby (SUSE)
All irq_domain_add_*() functions are going away. PowerPC is the only user of irq_domain_add_nomap() and there is no irq_domain_create_nomap() complement. Therefore, to align with the rest of the kernel, rename irq_domain_add_nomap() to irq_domain_create_nomap() and accept a fwnode_handle instead of a device_node. [ tglx: Fix up subject prefix ] Signed-off-by: Jiri Slaby (SUSE) <jirislaby@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/all/20250319092951.37667-40-jirislaby@kernel.org
2025-05-16Merge branches 'rcu/misc-for-6.16', 'rcu/seq-counters-for-6.16' and ↵Joel Fernandes
'rcu/torture-for-6.16' into rcu/for-next
2025-05-16rcutorture: Perform more frequent testing of ->gpwrapJoel Fernandes
Currently, the ->gpwrap is not tested (at all per my testing) due to the requirement of a large delta between a CPU's rdp->gp_seq and its node's rnp->gpseq. This results in no testing of ->gpwrap being set. This patch by default adds 5 minutes of testing with ->gpwrap forced by lowering the delta between rdp->gp_seq and rnp->gp_seq to just 8 GPs. All of this is configurable, including the active time for the setting and a full testing cycle. By default, the first 25 minutes of a test will have the _default_ behavior there is right now (ULONG_MAX / 4) delta. Then for 5 minutes, we switch to a smaller delta causing 1-2 wraps in 5 minutes. I believe this is reasonable since we at least add a little bit of testing for usecases where ->gpwrap is set. [ Apply fix for Dan Carpenter's bug report on init path cleanup. ] [ Apply kernel doc warning fix from Akira Yokosawa. ] Tested-by: Paul E. McKenney <paulmck@kernel.org> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com>
2025-05-16cxl/Documentation: Fix typo in sysfs write_bandwidth attribute pathAlok Tiwari
Fix a typo in the sysfs documentation for the CXL "write_bandwidth" attribute path. The attribute was incorrectly documented as write_banwidth. Update it to the correct write_bandwidth to align with the actual implementation. Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com> Link: https://patch.msgid.link/20250516103855.3820882-1-alok.a.tiwari@oracle.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
2025-05-16doc/RCU/listRCU: refine example code for eliminating stale dataWei Yang
This patch adjust the example code with following two purpose: * reduce the confusion on not releasing e->lock * emphasize e is valid and not stale with e->lock held Signed-off-by: Wei Yang <richard.weiyang@gmail.com> CC: Boqun Feng <boqun.feng@gmail.com> CC: Alan Huang <mmpgouride@gmail.com> Reviewed-by: Alan Huang <mmpgouride@gmail.com> Link: https://lore.kernel.org/r/20250218005047.27258-1-richard.weiyang@gmail.com Signed-off-by: Boqun Feng <boqun.feng@gmail.com> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com>
2025-05-16doc: Update LWN RCU API links in whatisRCU.rstPaul E. McKenney
This commit adds the 2024 LWN RCU API article set. Signed-off-by: Paul E. McKenney <paulmck@kernel.org> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com>
2025-05-16dt-bindings: PCI: microchip,pcie-host: Fix DMA coherency propertyConor Dooley
PolarFire SoC may be configured in a way that requires non-coherent DMA handling. On RISC-V, buses are coherent by default & the dma-noncoherent property is required to denote buses or devices that are non-coherent. For some reason, instead of adding dma-noncoherent to the binding the pointless, NOP, property dma-coherent was. Swap dma-coherent for dma-noncoherent. Fixes: 04aa999eb96fd ("dt-bindings: PCI: microchip,pcie-host: Allow dma-noncoherent") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Link: https://lore.kernel.org/r/20250516-datebook-senator-ff7a1c30cbd5@spud
2025-05-16x86,fs/resctrl: Move the resctrl filesystem code to live in /fs/resctrlJames Morse
Resctrl is a filesystem interface to hardware that provides cache allocation policy and bandwidth control for groups of tasks or CPUs. To support more than one architecture, resctrl needs to live in /fs/. Move the code that is concerned with the filesystem interface to /fs/resctrl. Signed-off-by: James Morse <james.morse@arm.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Reviewed-by: Reinette Chatre <reinette.chatre@intel.com> Reviewed-by: Fenghua Yu <fenghuay@nvidia.com> Tested-by: Fenghua Yu <fenghuay@nvidia.com> Tested-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/20250515165855.31452-25-james.morse@arm.com
2025-05-16dt-bindings: timer: renesas,ostm: Document RZ/V2N (R9A09G056) supportLad Prabhakar
Document support for the Renesas OS Timer (OSTM) found on the Renesas RZ/V2N (R9A09G056) SoC. The OSTM IP on RZ/V2N is identical to that on other RZ families, so no driver changes are required as `renesas,ostm` will be used as fallback compatible. Also update the bindings to require the "resets" property for RZ/V2N by inverting the logic: all SoCs except RZ/A1 and RZ/A2 now require the "resets" property. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250515182207.329176-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2025-05-16dt-bindings: thermal: qcom-tsens: Add ipq5018 compatibleSricharan Ramabadhran
IPQ5018 has tsens v1.0 block with 5 sensors of which 4 are in use and 1 interrupt. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://lore.kernel.org/r/DS7PR19MB88835BD1063C4D5451E14B0E9DCC2@DS7PR19MB8883.namprd19.prod.outlook.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2025-05-16dt-bindings: thermal: Add support for Airoha EN7581 thermal sensorChristian Marangi
Add support for Airoha EN7581 thermal sensor and monitor. This is a simple sensor for the CPU or SoC Package that provide thermal sensor and trip point for hot low and critical condition to fire interrupt and react on the abnormal state. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250511185003.3754495-1-ansuelsmth@gmail.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2025-05-16vsprintf: remove redundant and unused %pCn format specifierLuca Ceresoli
%pC and %pCn print the same string, and commit 900cca294425 ("lib/vsprintf: add %pC{,n,r} format specifiers for clocks") introducing them does not clarify any intended difference. It can be assumed %pC is a default for %pCn as some other specifiers do, but not all are consistent with this policy. Moreover there is now no other suffix other than 'n', which makes a default not really useful. All users in the kernel were using %pC except for one which has been converted. So now remove %pCn and all the unnecessary extra code and documentation. Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Reviewed-by: Petr Mladek <pmladek@suse.com> Tested-by: Petr Mladek <pmladek@suse.com> Reviewed-by: Yanteng Si <si.yanteng@linux.dev> Link: https://lore.kernel.org/r/20250311-vsprintf-pcn-v2-2-0af40fc7dee4@bootlin.com Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2025-05-16dt-bindings: timer: Convert marvell,armada-370-timer to DT schemaRob Herring (Arm)
Convert the Marvell Armada 37x/380/XP Timer binding to DT schema format. Update the compatible entries to match what is in use. "marvell,armada-380-timer" in particular was missing. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20250506022301.2588282-1-robh@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2025-05-16dt-bindings: timer: Convert ti,keystone-timer to DT schemaRob Herring (Arm)
Convert the TI Keystone Timer binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250506022330.2589598-1-robh@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2025-05-16dt-bindings: timer: Convert st,spear-timer to DT schemaRob Herring (Arm)
Convert the ST SPEAr Timer binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250506022326.2589389-1-robh@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2025-05-16dt-bindings: timer: Convert socionext,milbeaut-timer to DT schemaRob Herring (Arm)
Convert the Socionext Milbeaut Timer binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250506022322.2589193-1-robh@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2025-05-16dt-bindings: timer: Convert snps,arc-timer to DT schemaRob Herring (Arm)
Convert the Synopsys ARC Local Timer binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250506022317.2589010-1-robh@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2025-05-16dt-bindings: timer: Convert snps,archs-rtc to DT schemaRob Herring (Arm)
Convert the Synopsys ARC HS RTC Timer binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250506022313.2588796-1-robh@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2025-05-16dt-bindings: timer: Convert snps,archs-gfrc to DT schemaRob Herring (Arm)
Convert the Synopsys ARC HS 64-bit Timer binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250506022309.2588605-1-robh@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2025-05-16dt-bindings: timer: Convert lsi,zevio-timer to DT schemaRob Herring (Arm)
Convert the TI NSPIRE Timer binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250506022257.2588136-1-robh@kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
generated by cgit (git 2.34.1) at 2025-07-18 11:42:20 +0000