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Add Device Tree for sama7d65 SoC.
Co-developed-by: Dharma Balasubiramani <dharma.b@microchip.com>
Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com>
Co-developed-by: Romain Sioen <romain.sioen@microchip.com>
Signed-off-by: Romain Sioen <romain.sioen@microchip.com>
Co-developed-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/20250107160850.120537-5-Ryan.Wanner@microchip.com
[claudiu.beznea: dropped comma typo from copyright, dropped space in
front of slow_xtal node, dropped empty space after slow_xtal node]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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The system1 uses Intel common redundant (crps185) power supplies so move
to correct new crps driver.
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Link: https://patch.msgid.link/20241217173537.192331-5-ninad@linux.ibm.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:
1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.
2. On older targets like SM8150/SM8250/SM8350, there have been
throughput issues seen during tethering use cases.
3. On targets like SDX75, intermittent disconnects were observed
with certain cables due to impedence variations.
Disabling these intermittent power states enhances device stability
without affecting power usage.
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241231080932.3149448-3-quic_prashk@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:
1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.
2. On older targets like SM8150/SM8250/SM8350, there have been
throughput issues seen during tethering use cases.
3. On targets like SDX75, intermittent disconnects were observed
with certain cables due to impedence variations.
Disabling these intermittent power states enhances device stability
without affecting power usage.
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241231080932.3149448-2-quic_prashk@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Enable the GPU on the stih410-b2260 board.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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Add the entry for the GPU (Mali400) on the stih410.dtsi
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
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Since these properties are common for all spi subnodes,
add them to SoC dtsi instead of board dts.
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Link: https://lore.kernel.org/r/20241218080333.2225-3-mihai.sain@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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Since these properties are common for all spi subnodes,
add them to SoC dtsi instead of board dts.
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Link: https://lore.kernel.org/r/20241218080333.2225-2-mihai.sain@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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Add no-1-8-v property to sdmmc0 node to keep VDDSDMMC power rail at 3.3V.
This property will stop the LDO regulator from switching to 1.8V when the
MMC core detects an UHS SD Card. VDDSDMMC power rail is used by all the
SDMMC interface pins in GPIO mode (PA0 - PA13).
On this board, PA10 is used as GPIO to enable the power switch controlling
USB Vbus for the USB Host. The change is needed to fix the PA10 voltage
level to 3.3V instead of 1.8V.
Fixes: 5d4c3cfb63fe ("ARM: dts: at91: sama5d27_wlsom1: add SAMA5D27 wlsom1 and wlsom1-ek")
Suggested-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com>
Tested-by: Andrei Simion <andrei.simion@microchip.com>
Link: https://lore.kernel.org/r/20241119160107.598411-3-cristian.birsan@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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Add no-1-8-v property to sdmmc0 node to keep VDDSDMMC power rail at 3.3V.
This property will stop the LDO regulator from switching to 1.8V when the
MMC core detects an UHS SD Card. VDDSDMMC power rail is used by all the
SDMMC interface pins in GPIO mode (PA0 - PA13).
On this board, PA6 is used as GPIO to enable the power switch controlling
USB Vbus for the USB Host. The change is needed to fix the PA6 voltage
level to 3.3V instead of 1.8V.
Fixes: d85c4229e925 ("ARM: dts: at91: sama5d29_curiosity: Add device tree for sama5d29_curiosity board")
Suggested-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com>
Tested-by: Andrei Simion <andrei.simion@microchip.com>
Link: https://lore.kernel.org/r/20241119160107.598411-2-cristian.birsan@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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Add sama7d65 pin descriptions.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/a8f880b89cd4470526a2955a0b6aaaaa24ba65b8.1733505542.git.Ryan.Wanner@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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The only board that actually requires these properties is
meson8b-odroidc1.dts but that already sets it on it's own. Drop these
properties from meson.dtsi because otherwise they can cause dtc
warnings:
/soc/usb@c9040000: unnecessary #address-cells/#size-cells without
"ranges", "dma-ranges" or child "reg" property
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241226220352.965505-1-martin.blumenstingl@googlemail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
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mdio-gpio is not a valid pattern according to mdio-gpio.yaml.
Use the generic 'mdio' name to fix the following dt-schema warnings:
'mdio-gpio' does not match '^mdio(-(bus|external))?(@.+|-([0-9]+))?$'
Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Currently there are 3 type of boards (imx6q|imx6qp|imx6dl-sabresd)
based on imx6qdl-sabresd.dtsi, they all do not set the dr_mode for
usbotg device node. The chipidea usb driver will configure it to otg
mode by default if the dr_mode is not set, but some testcases need to
parse the dr_mode from DT and decide the follow-up test strategy, here
set the dr_mode to otg explicitly for these 3 imx6qdl-sabresd based
boards.
Signed-off-by: Hui Wang <hui.wang@canonical.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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According to adv7180.yaml, the correct property name is
"adi,force-bt656-4".
Update it accordingly to fix several dt-schema warnings:
adv7280@21: 'adv,force-bt656-4' does not match any of the regexes: ...
imx6qdl-apalis.dtsi is the only in-tree kernel user of this property.
BSD does have a adv7180 driver, so should not be impacted.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The integrated usb phys are supplied by the 3p0 regulator, which has a
voltage range of 2.625V to 3.4V. Thus the min and max values are
corrected and the regulator added as a proper supply for the usb phys.
This fixes the following warnings during the probe of the mxs_phy
driver:
mxs_phy 20c9000.usbphy: supply phy-3p0 not found, using dummy regulator
mxs_phy 20ca000.usbphy: supply phy-3p0 not found, using dummy regulator
The regulator handling was introduced by commit `966d73152078 (usb: phy:
mxs: enable regulator phy-3p0 to improve signal qualilty, 2024-07-26)`.
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The integrated usb phys are supplied by the 3p0 regulator, which has a
voltage range of 2.625V to 3.4V. Thus the min and max values are
corrected and the regulator added as a proper supply for the usb phys.
This fixes the following warnings during the probe of the mxs_phy
driver:
mxs_phy 20c9000.usbphy: supply phy-3p0 not found, using dummy regulator
mxs_phy 20ca000.usbphy: supply phy-3p0 not found, using dummy regulator
The 3p0 regulator handling was introduced by commit 966d73152078 ("usb:
phy: mxs: enable regulator phy-3p0 to improve signal qualilty")`.
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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The integrated usb phys are supplied by the 3p0 regulator, which has a
voltage range of 2.625V to 3.4V. Thus the min and max values are
corrected and the regulator added as a proper supply for the usb phys.
This fixes the following warnings during the probe of the mxs_phy
driver:
mxs_phy 20c9000.usbphy: supply phy-3p0 not found, using dummy regulator
mxs_phy 20ca000.usbphy: supply phy-3p0 not found, using dummy regulator
The 3p0 regulator handling was introduced by commit 966d73152078 ("usb:
phy: mxs: enable regulator phy-3p0 to improve signal qualilty")`.
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This was initially copied from the Midas DTSI, but there is no
proof that the same interrupt is also used on the Tab 3. The pin
listed as the interrupt here is GPIO_HDMI_CEC on the Midas,
but for the Tab 3 it is the headset button GPIO - GPIO_EAR_SEND_END.
Drop the interrupt, since there is no proof that it is used.
Signed-off-by: Artur Weber <aweber.kernel@gmail.com>
Link: https://lore.kernel.org/r/20240816-midas-audio-tab3-v2-5-48ee7f2293b3@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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In the schematics, the MCLK2 pin is shown as connected to CODEC_CLK32K,
which is derived from the same 32KHZ_PMIC clock as Bluetooth/WiFi and
GPS clocks. 32KHZ_PMIC is connected to the BTCLK pin, represented in
mainline as S2MPS11_CLK_BT.
Add the MCLK2 clock to the WM1811 codec clock property to properly
describe the hardware.
Signed-off-by: Artur Weber <aweber.kernel@gmail.com>
Link: https://lore.kernel.org/r/20240816-midas-audio-tab3-v2-4-48ee7f2293b3@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Set up headset mic bias regulator and add the necessary properties to
the samsung,midas-audio node to allow for headset jack detection.
Signed-off-by: Artur Weber <aweber.kernel@gmail.com>
Link: https://lore.kernel.org/r/20240816-midas-audio-tab3-v2-3-48ee7f2293b3@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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There is no Rohm DAC on the CycloneV devkit according to the online
documentation for it that I could find, and it definitely does not have
a dh2228fv as this device does not actually exist! Remove the DAC node
from the devicetree as it is not acceptable to pretend to have a device
on a board in order to bind the spidev driver in Linux.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240717-partake-antivirus-3347e415fb7d@spud
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Add cpu-pcie interconnect path for PCIe EP to sdx55 platform.
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/1689751218-24492-4-git-send-email-quic_krichai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add pcie-mem & cpu-pcie interconnect path ifor PCIe EP to sdx65 platform.
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Link: https://lore.kernel.org/r/1689751218-24492-3-git-send-email-quic_krichai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.14
- Add more serial (SCIF), power monitor, ADC, and sound support for
the RZ/G3S SoC and the RZ/G3S SMARC SoM and development board,
- Add support for the R-Car V4H ES3.0 (R8A779G3) SoC on the White Hawk
Single development board,
- Add display support for the R-Car V4M SoC and the Gray Hawk Single
development board,
- Add video capture support for the Gray Hawk Single development
board,
- Add initial support for the RZ/G3E (R9A09G047) SoC and the RZ/G3E
SMARC SoM and Carrier-II EVK development board,
- Add support for 5-port MATEnet on the Falcon Ethernet sub-board,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.14-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (33 commits)
arm64: dts: renesas: r9a09g047: Add I2C nodes
arm64: dts: renesas: rzg3s-smarc: Add sound card
arm64: dts: renesas: rzg3s-smarc: Enable SSI3
arm64: dts: renesas: Add da7212 audio codec node
arm64: dts: renesas: rzg3s-smarc-som: Add versa3 clock generator node
arm64: dts: renesas: r9a08g045: Add SSI nodes
arm64: dts: renesas: rzg3s-smarc-som: Enable ADC
arm64: dts: renesas: r9a08g045: Add ADC node
arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board
arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM
arm64: dts: renesas: r9a09g047: Add OPP table
arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC
arm64: dts: renesas: falcon-ethernet: Describe PHYs connected on the breakout board
arm64: dts: renesas: r8a779a0: Remove address- and size-cells from AVB[1-5]
dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK
dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
arm64: dts: renesas: gray-hawk-single: Add video capture support
arm64: dts: renesas: gray-hawk-single: Add DisplayPort support
arm64: dts: renesas: r8a779h0: Add display support
...
Link: https://lore.kernel.org/r/cover.1734689803.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
STM32 DT for v6.14, round 1
Highlights:
----------
- MPU:
- STM32MP13:
- Populate all timer counter nodes in Soc file.
- Enable counter (timers) on stm32mp135f-dk.
- DH core: increase CPU voltage to fit with STM32MP135F datasheet.
- STMP32MP15:
- Populate all timer counter nodes in Soc file.
- Enable counter (timers) on stm32mp15 EV1 and DK boards.
- OCTAVO:
- LXA-TAC (gen1/2): disable RTC, update aliases and
adjust USB gadget.
- Add LXA-TAC gen3 based on OSD32MP153x SIP:
STMP32MP153, RAM, PMIC.
- DH: minor fixes.
- STM32MP25:
- Enable imx335/CSI/DCMIPP pipeline on stm32mp257f-ev1.
- Add I2S, SAI, SPDIFRX supports.
- Add and enable COMBOPHY on stm32mp257f-ev1. Combophy is used
by PCIe and USB3.
* tag 'stm32-dt-for-v6.14-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (23 commits)
arm64: dts: st: enable imx335/csi/dcmipp pipeline on stm32mp257f-ev1
arm64: dts: st: add csi & dcmipp node in stm32mp25
ARM: dts: stm32: Swap USART3 and UART8 alias on STM32MP15xx DHCOM SoM
ARM: dts: stm32: add counter subnodes on stm32mp157 dk boards
ARM: dts: stm32: add counter subnodes on stm32mp157c-ev1
ARM: dts: stm32: add counter subnodes on stm32mp135f-dk
ARM: dts: stm32: populate all timer counter nodes on stm32mp15
ARM: dts: stm32: populate all timer counter nodes on stm32mp13
ARM: dts: stm32: lxa-tac: Add support for generation 3 devices
ARM: dts: stm32: lxa-tac: move adc and gpio{e,g} to gen{1,2} boards
dt-bindings: arm: stm32: add compatible strings for Linux Automation LXA TAC gen 3
ARM: dts: stm32: lxa-tac: adjust USB gadget fifo sizes for multi function
ARM: dts: stm32: lxa-tac: extend the alias table
ARM: dts: stm32: lxa-tac: disable the real time clock
ARM: dts: stm32: Fix IPCC EXTI declaration on stm32mp151
ARM: dts: stm32: Sort M24256E write-lockable page in DH STM32MP13xx DHCOR SoM DT
ARM: dts: stm32: Increase CPU core voltage on STM32MP13xx DHCOR SoM
ARM: dts: stm32: Deduplicate serial aliases and chosen node for STM32MP15xx DHCOM SoM
arm64: dts: st: Enable COMBOPHY on the stm32mp257f-ev1 board
arm64: dts: st: Add combophy node on stm32mp251
...
Link: https://lore.kernel.org/r/7ffcca65-3953-413a-bcf3-0702a6b0518b@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Swap USART3 and UART8 aliases on STM32MP15xx DHCOM SoM,
make sure UART8 is listed first, USART3 second, because
the UART8 is labeled as UART2 on the SoM pinout, while
USART3 is labeled as UART3 on the SoM pinout.
Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Enable the counter nodes without dedicated pins. With such configuration,
the counter interface can be used on internal clock to generate events.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Enable the counter nodes without dedicated pins. With such configuration,
the counter interface can be used on internal clock to generate events.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Enable the counter nodes without dedicated pins. With such configuration,
the counter interface can be used on internal clock to generate events.
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Counter driver originally had support limited to quadrature interface
and simple counter. It has been improved[1], so add the remaining
stm32 timer counter nodes.
[1] https://lore.kernel.org/linux-arm-kernel/20240307133306.383045-1-fabrice.gasnier@foss.st.com/
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Counter driver originally had support limited to quadrature interface
and simple counter. It has been improved[1], so add the remaining
stm32 timer counter nodes.
[1] https://lore.kernel.org/linux-arm-kernel/20240307133306.383045-1-fabrice.gasnier@foss.st.com/
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Currently this needs to be done in userspace.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://lore.kernel.org/r/20241021015147.172700-1-rosenp@gmail.com
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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This adds a device tree for the Genexis XG6846B router.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20241019-genexis-xg6846b-base-v3-9-8375a0e1f89f@linaro.org
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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The ARM PL081 DMA controller can be found in the BCM6846
memory map, and it turns out to work.
The block may be used as DMA engine for some of the
peripherals (maybe the EMMC controller found in the same
group of peripherals?) but it can always be used as a
memcpy engine, which is a generic "blitter".
I tested it with the dmatest module, and it copies
lots of data very fast and fires hundreds of thousands
of interrupts so it works just fine.
Add it to the BCM6846 DTSI file.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20241019-genexis-xg6846b-base-v3-6-8375a0e1f89f@linaro.org
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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Add the BCMBCA LED controller to the BCM6846 DTSI.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20241019-genexis-xg6846b-base-v3-5-8375a0e1f89f@linaro.org
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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This adds the MDIO block found in the BCM6846. Use the new
"brcm,bcm6846-mdio" compatible (merged to the networking tree)
for this block.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20241019-genexis-xg6846b-base-v3-4-8375a0e1f89f@linaro.org
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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The BCM6846 has the same simplistic GPIOs as some other
Broadcom SoCs: plain memory-mapped registers with up to
8 blocks of 32 GPIOs each totalling 256 GPIOs.
Users of the SoC can selectively enable the GPIO blocks
actually used with a certain design.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20241019-genexis-xg6846b-base-v3-3-8375a0e1f89f@linaro.org
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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The BCM6846 has a BCM7038-compatible watchdog timer, just
add it to the device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20241019-genexis-xg6846b-base-v3-2-8375a0e1f89f@linaro.org
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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The bcm6846 has a standard iproc 200 RNG which is already
fully supported by bindings, so just add it to the DTS file.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20241019-genexis-xg6846b-base-v3-1-8375a0e1f89f@linaro.org
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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Remove properties which are both unused in the kernel and undocumented.
Most likely they are leftovers from downstream.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241115193904.3624350-1-robh@kernel.org
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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Add PAC1934 support in order to monitor the board power consumption.
Device is connected on flexcom7 in twi mode.
[root@SAM9X75 ~]$ awk -f pac1934.awk
VDD3V3 current: 10.675 mA, voltage: 3295.41 mV
VDDOUT4 current: 5.7625 mA, voltage: 1196.78 mV
VDDCORE current: 115.442 mA, voltage: 1243.65 mV
VDDIODDR current: 29.585 mA, voltage: 1345.21 mV
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Link: https://lore.kernel.org/r/20241122080523.3941-3-mihai.sain@microchip.com
[claudiu.beznea: s/VDDOUT4/DCDC4 to comply with schematics]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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Since these properties are common for all i2c subnodes,
move them to SoC dtsi from board dts.
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/20241122080523.3941-2-mihai.sain@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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The ahb reset is deasserted in probe before first register access, while the
stmmacheth-ocp reset needs to be asserted every time before changing the phy
mode in Arria10[1].
Changed in Upstream to "ahb"(331085a423b arm64: dts: socfpga: change the
reset-name of "stmmaceth-ocp" to "ahb" ).This change was intended for arm64
socfpga and it is not applicable to Arria10.
Further with STMMAC-SELFTEST Driver enabled, ethtool test also FAILS.
$ ethtool -t eth0
[ 322.946709] socfpga-dwmac ff800000.ethernet eth0: entered promiscuous mode
[ 323.374558] socfpga-dwmac ff800000.ethernet eth0: left promiscuous mode
The test result is FAIL
The test extra info:
1. MAC Loopback 0
2. PHY Loopback -110
3. MMC Counters -110
4. EEE -95
5. Hash Filter MC 0
6. Perfect Filter UC -110
7. MC Filter -110
8. UC Filter 0
9. Flow Control -110
10. RSS -95
11. VLAN Filtering -95
12. VLAN Filtering (perf) -95
13. Double VLAN Filter -95
14. Double VLAN Filter (perf) -95
15. Flexible RX Parser -95
16. SA Insertion (desc) -95
17. SA Replacement (desc) -95
18. SA Insertion (reg) -95
19. SA Replacement (reg) -95
20. VLAN TX Insertion -95
21. SVLAN TX Insertion -95
22. L3 DA Filtering -95
23. L3 SA Filtering -95
24. L4 DA TCP Filtering -95
25. L4 SA TCP Filtering -95
26. L4 DA UDP Filtering -95
27. L4 SA UDP Filtering -95
28. ARP Offload -95
29. Jumbo Frame -110
30. Multichannel Jumbo -95
31. Split Header -95
32. TBS (ETF Scheduler) -95
[ 324.881327] socfpga-dwmac ff800000.ethernet eth0: Link is Down
[ 327.995360] socfpga-dwmac ff800000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
Link:[1] https://www.intel.com/content/www/us/en/docs/programmable/683711/21-2/functional-description-of-the-emac.html
Fixes: 331085a423b ("arm64: dts: socfpga: change the reset-name of "stmmaceth-ocp" to "ahb")
Signed-off-by: Mamta Shukla <mamta.shukla@leica-geosystems.com>
Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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The properties #address-cells and #size-cells are only useful if there
is a ranges property or child nodes with "reg" properties.
This fixes a W=1 warning:
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dts:51.22-72.4: Warning (avoid_unnecessary_addr_size): /soc/i2c@ffc04000/stmpe811@41: unnecessary #address-cells/#size-cells without "ranges", "dma-ranges" or child "reg" property
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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at24.yaml defines the node name for at24 EEPROMs as 'eeprom'.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20240910215905.823337-1-robh@kernel.org
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Add second source RTC on i2c bus 9.
Signed-off-by: Yang Chen <yangchen.openbmc@gmail.com>
Link: https://patch.msgid.link/20241212133226.342937-5-yangchen.openbmc@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Add GPIO BMC_READY on LED and give it active value and transitory flag.
Signed-off-by: Yang Chen <yangchen.openbmc@gmail.com>
Link: https://patch.msgid.link/20241212133226.342937-4-yangchen.openbmc@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Add four I/O expanders on each i2c of fan control board (FCB), assign the
GPIO line name to each GPIO in use, and specify the interrupt GPIO number
for each FCB's i/o expander.
Signed-off-by: Yang Chen <yangchen.openbmc@gmail.com>
Link: https://patch.msgid.link/20241212133226.342937-3-yangchen.openbmc@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Add three I/O expanders on i2c bus 0, assign the GPIO line name to each
GPIO in use, and specify the interrupt GPIO that has been used on it and
give the interrupt gpio number.
Signed-off-by: Yang Chen <yangchen.openbmc@gmail.com>
Link: https://patch.msgid.link/20241212133226.342937-2-yangchen.openbmc@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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