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path: root/drivers/clk/renesas
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2025-01-07clk: renesas: rzv2h: Add support for RZ/G3E SoCBiju Das
The clock structure for RZ/G3E is almost identical to RZ/V2H SoC with more IP blocks compared to RZ/V2H. For eg: VSPI, LVDS, DPI and LCDC1 are present only on the RZ/G3E SoC. Add minimal clock and reset entries required to boot the Renesas RZ/G3E SMARC EVK and binds it with the RZ/V2H CPG core driver. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/20241213123550.289193-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: rzv2h: Add MSTOP supportBiju Das
Add MSTOP support to control buses for the individual units on RZ/V2H. Use per-bit (instead of group-based) configuration and atomic counters, to ensure precise control over individual MSTOP bits, and to prevent issues with shared dependencies between module clocks. Co-developed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Co-developed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241213123550.289193-2-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/20250102181839.352599-2-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/20250102181839.352599-3-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/20250102181839.352599-4-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/20250102181839.352599-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-10clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ↵Claudiu Beznea
ADC IP Add clocks, resets and power domains for ADC IP available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/20241206111337.726244-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-10clk: renesas: r8a779h0: Add display clocksTomi Valkeinen
Add display related clocks for DU, DSI, FCPVD, and VSPD. Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241206-rcar-gh-dsi-v3-5-d74c2166fa15@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-10clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resetsLad Prabhakar
Add support for the PLLVDO clock and its related CRU clocks and reset entries in the r9a09g057 CPG driver. Introduce `CLK_PLLVDO` and associated clocks like `CLK_PLLVDO_CRU0`, `CLK_PLLVDO_CRU1`, `CLK_PLLVDO_CRU2`, and `CLK_PLLVDO_CRU3`, along with their corresponding dividers. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241202203916.48668-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-10clk: renesas: rzv2h: Add selective Runtime PM support for clocksLad Prabhakar
Update `rzv2h_cpg_attach_dev` to prevent external and core clocks not tied to the power domain from being managed by Runtime PM. This ensures that only clocks originating from the domain are controlled, thereby avoiding unintended handling of external and core clocks. Additionally, introduce a `no_pm` flag in `mod_clock` and `rzv2h_mod_clk` structures to exclude specific clocks from Runtime PM when needed. Some clocks, such as those in the CRU block, require unique enable/disable sequences that are incompatible with standard Runtime PM. For example, the CSI-2 D-PHY clock initialization requires toggling individual clocks, making Runtime PM unsuitable. The helper function `rzv2h_cpg_is_pm_clk()` checks whether a clock should be managed by Runtime PM based on this `no_pm` flag. New macros, such as `DEF_MOD_NO_PM`, allow straightforward declaration of clocks that bypass PM. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241202203916.48668-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-10clk: renesas: r9a06g032: Use BIT macro consistentlyWolfram Sang
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241128091113.24116-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-10clk: renesas: r9a06g032: Add restart handlerWolfram Sang
The SYSCTRL module also does reset handling. Start supporting that by allowing software resets which can then be utilized by a restart handler. Finally 'reboot' will do something useful on RZ/N1D. Watchdog support to be added later. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241128091113.24116-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-03clk: renesas: r9a08g045: Add clock, reset and power domain for the remaining ↵Claudiu Beznea
SCIFs The Renesas RZ/G3S SoC has 6 SCIF interfaces. SCIF0 is used as debug console and is already enabled. Add clock, reset and power domain support for the remaining ones. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241115134401.3893008-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-03clk: renesas: r9a08g045: Add clocks, resets and power domains support for SSIClaudiu Beznea
Add SSI clocks, resets and power domains support for the SSI blocks available on the Renesas RZ/G3S SoC. Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241113133540.2005850-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-12-03clk: renesas: cpg-mssr: Fix 'soc' node handling in cpg_mssr_reserved_init()Javier Carrasco
A device_node reference obtained via of_find_node_by_path() requires explicit calls to of_node_put() after it is no longer required to avoid leaking the resource. Instead of adding the missing calls to of_node_put() in all execution paths, use the cleanup attribute for 'soc' by means of the __free() macro, which automatically calls of_node_put() when the variable goes out of scope. Fixes: 6aa175476490 ("clk: renesas: cpg-mssr: Ignore all clocks assigned to non-Linux system") Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241031-clk-renesas-cpg-mssr-cleanup-v2-1-0010936d1154@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-11-06clk: renesas: vbattb: Add VBATTB clock driverClaudiu Beznea
The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used by the RTC. The input to the VBATTB could be a 32KHz crystal or an external clock device. The HW block diagram for the clock generator is as follows: +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ , After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: vbattb-xtal xbyp xc mux vbattbclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. If the crystal is connected on RTXIN, RTXOUT pins the XC will be selected as mux input. If an external clock device is connected on RTXIN, RTXOUT pins the XBYP will be selected as mux input. The load capacitance of the internal crystal can be configured with renesas,vbattb-load-nanofarads DT property. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20241101095720.2247815-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-11-03clk: renesas: rzg2l: Fix FOUTPOSTDIV clkBiju Das
While computing foutpostdiv_rate, the value of params->pl5_fracin is discarded, which results in the wrong refresh rate. Fix the formula for computing foutpostdiv_rate. Fixes: 1561380ee72f ("clk: renesas: rzg2l: Add FOUTPOSTDIV clk support") Signed-off-by: Hien Huynh <hien.huynh.px@renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241024134236.315289-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-25clk: renesas: r9a08g045: Add power domain for RTCClaudiu Beznea
The RTC and VBATTB don't share the MSTOP control bit (but only the bus clock and the reset signal). As the MSTOP control is modeled though power domains add power domain support for the RTC device available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241019084738.3370489-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-25clk: renesas: r9a08g045: Mark the watchdog and always-on PM domains as IRQ safeClaudiu Beznea
If the watchdog is part of a dedicated power domain (as it may be on RZ/G3S) the watchdog PM domain need to be powered on in the watchdog restart handler. Currently, only the clocks are enabled in the watchdog restart handler. To be able to also power on the PM domain we need to call pm_runtime_resume_and_get() on the watchdog restart handler, mark the watchdog device as IRQ safe and register the watchdog PM domain with GENPD_FLAG_IRQ_SAFE. Register watchdog PM domain as IRQ safe. Along with it the always-on PM domain (parent of the watchdog domain) was marked as IRQ safe. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/20241015164732.4085249-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-25clk: renesas: rzg2l-cpg: Use GENPD_FLAG_* flags instead of local onesClaudiu Beznea
For watchdog PM domain it is necessary to provide GENPD_FLAG_IRQ_SAFE flag to be able to power on the watchdog PM domain from atomic context. For this, adjust the current infrastructure to be able to provide GENPD_FLAG_* for individual PM domains. With this, remove the always_on flag from rzg2l_cpg_add_pm_domains() as it is not necessary anymore. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/20241015164732.4085249-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-25clk: renesas: rzg2l-cpg: Move PM domain power on in rzg2l_cpg_pd_setup()Claudiu Beznea
Move the PM domain power on in rzg2l_cpg_pd_setup(). With this the previously always-on power domains got struct generic_pm_domain::{power_on, power_off} populated (and registered with simple_qos_governor if #power-domain-cells = <1> and with pm_domain_always_on_gov if #power-domain-cells = <0>). The values for struct generic_pm_domain::{power_on, power_off} are now populated for all registered domains but used by core only for the domains that can use them (the PM domain should be non always-on and registered with simple_qos_governor). Moreover, the power on/off functions check if the mstop support is valid. The mstop is populated only by the RZ/G3S initialization code at the moment. This approach was chosen to keep the code simple and use the same code across different implementations. There should be no issues with this approach as the always on domains are registered with GENPD_FLAG_ALWAYS_ON and the PM domain core takes care of it. This approach allows doing further cleanups on the rzg2l_cpg power domain registering code that will be handled by the next commit. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/20241015164732.4085249-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-14clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocksGeert Uytterhoeven
Early revisions of the R-Car V4M Series Hardware User’s Manual contained an incorrect formula for the CPU core clocks: ZCnφ = (PLL2VCO x 1/2) x mult/32 Dang-san fixed this by using CLK_PLL2_DIV2 instead of CLK_PLL2 as the parent clock. In Rev.0.70 of the documentation, the formula was corrected to: ZCnφ = (PLL2VCO x 1/4) x mult/32 As the CPG Block Diagram now shows a separate 1/4 post-divider for PLL2, the use of CLK_PLL2_DIV2 is a recurring source of confusion. Hence get rid of CLK_PLL2_DIV2, and include the proper 1/4 post-divider in the invocation of the DEF_GEN4_Z() macro, like is done on other R-Car Gen4 (and Gen3) SoCs. Reported-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/0d2789cac2bf306145fe0bbf269c2da5942bb68f.1728377724.git.geert+renesas@glider.be
2024-10-07clk: renesas: r9a09g057: Add clock and reset entries for ICUFabrizio Castro
Add clock and reset entries for the Renesas RZ/V2H(P) ICU IP block. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240930145244.356565-4-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-07clk: renesas: r9a09g057: Add CA55 core clocksLad Prabhakar
Add CA55 core clocks which are derived from PLLCA55. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240918135957.290101-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-01clk: renesas: Remove duplicate and trailing empty linesMarek Vasut
Remove the duplicate and trailing empty lines. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240908211056.230784-1-marek.vasut+renesas@mailbox.org Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-21clk: Switch back to struct platform_driver::remove()Uwe Kleine-König
After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all clk drivers to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://lore.kernel.org/r/20240909144026.870565-2-u.kleine-koenig@baylibre.com Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-09-21Merge branches 'clk-assigned-rates', 'clk-renesas' and 'clk-scmi' into clk-nextStephen Boyd
* clk-assigned-rates: clk: clk-conf: support assigned-clock-rates-u64 * clk-renesas: (34 commits) clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT clk: renesas: rzv2h: Add support for dynamic switching divider clocks clk: renesas: r9a08g045: Add clocks, resets and power domains for USB dt-bindings: clock: renesas,cpg-clocks: Add top-level constraints clk: renesas: r8a779h0: Add CANFD clock clk: renesas: Add RZ/V2H(P) CPG driver clk: renesas: Add family-specific clock driver for RZ/V2H(P) dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG clk: renesas: r8a779h0: Add PWM clock dt-bindings: clock: renesas,cpg-mssr: Document RZ/G2M v3.0 (r8a774a3) clock clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs clk: renesas: rcar-gen4: Remove unused fixed PLL clock types clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs clk: renesas: r8a779a0: Use defines for PLL control registers clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs clk: renesas: rcar-gen4: Add support for fixed variable PLLs clk: renesas: rcar-gen4: Add support for variable fractional PLLs ... * clk-scmi: clk: scmi: add is_prepared hook
2024-09-02clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDTLad Prabhakar
Add clock and reset entries for Generic Timer (GTM), I2C Bus Interface (RIIC), SD/MMC Host Interface (SDHI) and Watchdog Timer (WDT) IP blocks. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828093822.162855-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02clk: renesas: rzv2h: Add support for dynamic switching divider clocksLad Prabhakar
Add support for dynamic switching divider clocks. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240828093822.162855-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-09-02clk: renesas: r9a08g045: Add clocks, resets and power domains for USBClaudiu Beznea
Add clocks, resets and power domains for USB modules available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240822152801.602318-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-20clk: renesas: r8a779h0: Add CANFD clockCong Dang
Add the CANFD module clock on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/9bf71bfda338ee5411751174b03b9e870cc818e3.1722519424.git.geert+renesas@glider.be
2024-08-20clk: renesas: Add RZ/V2H(P) CPG driverLad Prabhakar
Add RZ/V2H(P) CPG driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240729202645.263525-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-02clk: Use of_property_present()Rob Herring (Arm)
Use of_property_present() to test for property presence rather than of_(find|get)_property(). This is part of a larger effort to remove callers of of_find_property() and similar functions. of_(find|get)_property() leak the DT struct property and data pointers which is a problem for dynamically allocated nodes which may be freed. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240731191312.1710417-4-robh@kernel.org Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> # clk-mstp.c Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-08-02clk: renesas: Add family-specific clock driver for RZ/V2H(P)Lad Prabhakar
Add family-specific clock driver for RZ/V2H(P) SoCs. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240729202645.263525-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-08-02clk: renesas: r8a779h0: Add PWM clockCong Dang
Add the module clock used by the PWM timers on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Cong Dang <cong.dang.xn@renesas.com> [wsa: rebased] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240725194906.14644-9-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-07-30clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configsGeert Uytterhoeven
The default PLL2/3/4/6 multiplier and divider configurations are no longer used after the conversion to fixed or variable fractional PLL clock types. Note that the default configurations are still documented in the comments above the individual rcar_gen4_cpg_pll_config instances. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/d13526a86066992d6afdf9bee7c1a18da72f914f.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Remove unused fixed PLL clock typesGeert Uytterhoeven
All users of the fixed default PLL2/3/4/6 clock types have been converted to fixed or variable fractional PLL clock types. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/c0229eb3518444f61173c6fb83bdcedb058dd079.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Remove unused variable PLL2 clock typeGeert Uytterhoeven
The variable PLL2 clock type was superseded by the more generic variable fractional 8.25 PLL clock type, and its sole user was converted. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/8e5564958002351f29435f63de1304fb3b51a725.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLsGeert Uytterhoeven
Currently, all PLLs are modelled as fixed divider clocks, based on the state of the mode pins. However, the boot loader stack may have changed the actual PLL configuration from the default, leading to incorrect clock frequencies. Describe PLL1 as a fixed fractional PLL instead, and PLL2, PLL3, PLL4, and PLL6 as variable fractional PLLs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/3beac7c44534ed153ce7cea5c31f4b0bb7b16ab0.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLsGeert Uytterhoeven
Currently, all PLLs but PLL2 are modelled as fixed divider clocks, based on the state of the mode pins. However, the boot loader stack may have changed the actual PLL configuration from the default, leading to incorrect clock frequencies. Describe PLL1 as a fixed fractional PLL instead, and PLL2, PLL3, PLL4, and PLL6 as variable fractional PLLs. Reformat nearby lines to retain a consistent layout. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/b98523ed08de7386944c5ae860eae107dc28be3e.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLsGeert Uytterhoeven
Currently, all PLLs are modelled as fixed divider clocks, based on the state of the mode pins. However, the boot loader stack may have changed the actual PLL configuration from the default, leading to incorrect clock frequencies. Describe PLL1 as a fixed fractional PLL instead, and PLL2, PLL3, and PLL6 as variable fractional PLLs. Note that the R-Car Gen4 clock driver does not support variable 9.24 PLLs yet, so the driver will downgrade them to fixed fractional PLLs, too. Reformat nearby lines to retain a consistent layout. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/8544571f507e00ed6fc61617d27c9e19de5e9d11.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: r8a779a0: Use defines for PLL control registersGeert Uytterhoeven
Add symbolic definitions for the various PLL control registers. Replace hardcoded register offsets by the new definitions. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/8cac464c7dfb15ecd299b8ab4ba88a16135f8123.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLsGeert Uytterhoeven
The custom clock driver that models the PLL clocks on R-Car Gen4 supports only fractional 8.25 PLLs, as used on R-Car V4H/V4M. R-Car S4-8 uses integer and fractional multiplication fields that are one bit larger resp. smaller, and a slightly different formula. Extend the existing support to fractional 9.24 PLL, and introduce new clock types and helper macros to describe these PLLs. Note that there is no use case for variable fractional 9.24 PLLs yet, as the Cortex-A55 cores on R-Car S4-8 do not support High Performance mode. Hence the PLL is always modeled as a fixed PLL, regardless of the description, Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/5684eda1260435c8eceabc274e0b18cb280a6341.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Add support for fixed variable PLLsGeert Uytterhoeven
The custom clock driver that models PLL clocks on R-Car Gen4 supports variable clocks, while PLL1 uses a similar control register layout, but is read-only. Extend the existing support to fixed clocks and PLL1, and introduce a new clock type and helper macro to describe a fixed PLL. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/841fbb63d472c357b3ce291a5991db3b847f96d8.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Add support for variable fractional PLLsGeert Uytterhoeven
The custom clock driver that models PLL clocks on R-Car Gen4 supports PLL2 on R-Car V4H/V4M only, while PLL3, PLL4, and PLL6 use the same control register layout. Extend the existing support to PLL3, PLL4, and PLL6, and introduce a new clock type and helper macro to describe these PLLs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/84ead759782560ec5643711e6bdd787a751053ce.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Add support for fractional multiplicationGeert Uytterhoeven
R-Car Gen4 PLLs support fractional multiplication, which can improve accuracy when configuring a specific frequency. Add support for fractional multiplication to the custom clock driver for PLLs, which is currently used only for PLL2 on R-Car V4H. While at it, add the missing blank line after the function. Note that Fractional Multiplication is not enabled by the driver, but used only if the boot loaded enabled it before. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/1a58ebef6f54460f49fb81ba9bbf288164de2646.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Use defines for common CPG registersGeert Uytterhoeven
Add symbolic definitions for common CPG registers. Replace hardcoded register offsets by the new definitions. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/8ae48a5dac59cb5723fbca3842b93a9e51ffe1ca.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Use FIELD_GET()Geert Uytterhoeven
Improve readability by using the FIELD_GET() helper instead of open-coding the same operation, and by adding field definitions to get rid of hardcoded values. While at it, move register definitions that are only used inside the rcar-gen4-cpg.c source file out of the rcar-gen4-cpg.h header file. Add a "CPG_" prefix to SD0CKCR1. Add comments where appropriate. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/fb19ad829738f02effa340fa04c178a162d41202.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Clarify custom PLL clock supportGeert Uytterhoeven
The custom clock driver that models the PLL clocks on R-Car Gen4 assumes the integer and fractional[*] multiplication field sizes as used on R-Car V4H and V4M, representing a fractional 8.25 number. Rename the related definitions, functions, and structures to clarify this, and to prepare for the advent of support for the different field sizes on R-Car S4-8. [*] The fractional part is not yet supported. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/2ce9f9c75bfb6312129d416672f9691bbd11c0e7.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rcar-gen4: Removed unused SSMODE_* definitionsGeert Uytterhoeven
All SSMODE operations are done using CPG_PLLxCR0_SSMODE*. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/19f84bfec94eab5f301a9c33563c285ab59b9b2a.1721648548.git.geert+renesas@glider.be
2024-07-30clk: renesas: rzg2l-cpg: Refactor to use priv for clks and base in clock ↵Lad Prabhakar
register functions Simplify the `rzg2l-cpg` driver by removing explicit passing of `clks` and `base` parameters in various clock registration functions. These values are now accessed directly from the `priv` structure. While at it, drop masking of parent clocks with 0xffff as nothing is ever stored in the high bits. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240715103555.507767-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-07-30clk: renesas: rzg2l-cpg: Use devres API to register clocksLad Prabhakar
We are using devres APIs for divider, mux and pll5 clocks so for consistency use the devres APIs for module, fixed factor and PLL clocks. While at it switched to clk_hw_register() instead of clk_register() as this has been marked as deprecated interface. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240715103555.507767-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-07-30clk: renesas: r8a779h0: Initial clock descriptions should be __initconstGeert Uytterhoeven
r8a779h0_core_clks[], r8a779h0_mod_clks[], and cpg_pll_configs[] are only used during initialization. Hence make them __initconst, so they will be freed later. Fixes: f077cab34df3010d ("clk: renesas: cpg-mssr: Add support for R-Car V4M") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/35bbcfb914ddb377fa77e3425e4e7e232c7c2cf9.1720794214.git.geert+renesas@glider.be
2024-07-30clk: renesas: r8a779g0: cpg_pll_configs should be __initconstGeert Uytterhoeven
cpg_pll_configs[] is only used during initialization. Hence make it __initconst, so it will be freed later. Fixes: 0ab55cf1834177a2 ("clk: renesas: cpg-mssr: Add support for R-Car V4H") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/ea806a096d47382f4f560b20f1038f03b4e44e0e.1720794214.git.geert+renesas@glider.be
generated by cgit (git 2.34.1) at 2025-07-18 08:09:00 +0000