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path: root/drivers/clk
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2025-03-12clk: sunxi-ng: a523: add reset linesAndre Przywara
Allwinner SoCs do not contain a separate reset controller, instead the reset lines for the various devices are integrated into the "BGR" (Bus Gate / Reset) registers, for each device group: one for all UARTs, one for all SPI interfaces, and so on. The Allwinner CCU driver also doubles as a reset provider, and since the reset lines are indeed just single bits in those BGR register, we can represent them easily in an array of structs, just containing the register offset and the bit number. Add the location of the reset bits for all devices in the A523/T527 SoCs, using the existing sunxi CCU infrastructure. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307002628.10684-14-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-03-12clk: sunxi-ng: a523: add bus clock gatesAndre Przywara
Add the various bus clock gates that control access to the devices' register interface. These clocks are each just one bit, typically the lower bits in some "BGR" (Bus Gate / Reset) registers, for each device group: one for all UARTs, one for all SPI interfaces, and so on. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307002628.10684-13-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-03-12clk: sunxi-ng: a523: remaining mod clocksAndre Przywara
Add the remaining mod clocks, driving various parts of the SoC: the "LEDC" LED controller, the "CSI" camera interface, the "ISP" image processor, the DSP clock, and the "fanout" clocks, which allow to put clock signals on external pins. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307002628.10684-12-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-03-12clk: sunxi-ng: a523: add USB mod clocksAndre Przywara
Add the clocks driving the USB subsystem: this just covers the two clocks creating the 12 MHz rate for the OHCI (USB 1.x) device. The rest of the USB clocks are either gate clocks (added later) or created internal to the USB IP. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307002628.10684-11-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-03-12clk: sunxi-ng: a523: add interface mod clocksAndre Przywara
Add the clocks driving what the user manual summarises under "interface" devices: raw NAND flash, MMC, SPI, EMAC, "IR" infrared, and the "GPADC" general purpose analogue/digital converter. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307002628.10684-10-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-03-12clk: sunxi-ng: a523: add system mod clocksAndre Przywara
Add the clocks driving some core system related subsystems of the SoC: the "CE" crypto engine, the high speed timers, the DRAM and the associated MBUS clock, and the PCIe clock. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307002628.10684-9-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-03-12clk: sunxi-ng: a523: add video mod clocksAndre Przywara
Add the clocks driving the various video subsystems of the SoC: the "DE" display engine, the "DI" deinterlacer, the "G2D" 2D graphics system, the Mali "GPU", the "VE" video engine, its associated IOMMU, as well as the clocks for the various video output drivers (HDMI, DP, LCDs). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307002628.10684-8-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-03-12clk: sunxi-ng: a523: Add support for bus clocksAndre Przywara
Add the basic bus clocks for the Allwinner A523 and T527 SoCs. This covers the AHB, APB0 and APB1 clocks. Linux is not supposed to change those clocks, but they are needed as parents for many other mod clocks. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307002628.10684-7-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-03-12clk: sunxi-ng: Add support for the A523/T527 CCU PLLsAndre Przywara
Add the PLL clocks of the main CCU of the Allwinner A523 and T527 SoCs. The clocks were modelled after the A523 and T527 manual, and double checked by writing all 1's into the respective register, to spot all implemented bits. The PLL and mod clocks for the two CPU clusters and the DSU are part of a separate CCU, also most audio clocks are collected in a DSP CCU, so both of these clock groups are missing from this driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307002628.10684-6-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-03-12clk: sunxi-ng: Add support for update bitAndre Przywara
Some clocks in the Allwinner A523 SoC contain an "update bit" (bit 27), which must be set to apply any register changes, namely the mux selector, the divider and the gate bit. Add a new CCU feature bit to mark those clocks, and set bit 27 whenever we are applying any changes. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307002628.10684-4-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-03-12clk: sunxi-ng: mp: provide wrappers for setting feature flagsAndre Przywara
So far our sunxi clock instantiation macros set the required clock features depending on the clock type, but the new "dual divider MP clock" requires us to pass that piece of information in by the user. Add new wrapper macros that allow to specify a "features" field, to allow marking those dual-divider clocks accordingly. Also add two convenience macros that deal with the most common cases. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://patch.msgid.link/20250307002628.10684-3-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-03-12clk: sunxi-ng: mp: introduce dual-divider clockAndre Przywara
The Allwinner A523 SoC introduces some new MP-style mod clock, where the second "P" divider is an actual numerical divider value, and not the numbers of bits to shift (1..32 instead of 1,2,4,8). The rest of the clock is the same as the existing MP clock, so enhance the existing code to accommodate for this. Introduce the new CCU feature bit CCU_FEATURE_DUAL_DIV to mark an MP clock as having two dividers, and change the dividing and encoding code to differentiate the two cases. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Link: https://patch.msgid.link/20250307002628.10684-2-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2025-03-11Merge tag 'samsung-clk-fixes-6.14' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-fixes Pull Samsung clk driver fixes from Krzysztof Kozlowski: - Google GS101: Fix synchronous external abort during system suspend. The driver access registers not available for OS, although issue would not be visible in earlier kernels due to missing suspend support. - Tesla FSD: Correct PLL142XX lock time * tag 'samsung-clk-fixes-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: update PLL locktime for PLL142XX used on FSD platform clk: samsung: gs101: fix synchronous external abort in samsung_clk_save()
2025-03-07clk: mmp: Fix NULL vs IS_ERR() checkCharles Han
The devm_kzalloc() function returns NULL on error, not error pointers. Fix the check. Fixes: 03437e857b0a ("clk: mmp: Add Marvell PXA1908 APMU driver") Signed-off-by: Charles Han <hanchunchao@inspur.com> Link: https://lore.kernel.org/r/20250307064708.209511-1-hanchunchao@inspur.com Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-03-07clk: samsung: Drop unused clk.h and of.h headersKrzysztof Kozlowski
<clk.h> header is for clock consumers, so drop its include from the Samsung clock controller drivers which do not use the consumer API (there are few which do, so leave it there). Drop including of <of.h> and <of_address.h> headers for all drivers which do not use anything from generic OF API or of_iomap(). Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250305-clk-samsung-headers-cleanup-v2-2-ea1ae8e9e2bf@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-03-07clk: samsung: Add missing mod_devicetable.h headerKrzysztof Kozlowski
Add an include for <mod_devicetable.h> in the drivers which use of_device_id table to bring its declaration directly, not through some other headers. Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20250305-clk-samsung-headers-cleanup-v2-1-ea1ae8e9e2bf@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-03-06clk: renesas: r9a09g047: Add clock and reset signals for the TSU IPJohn Madieu
Add required clocks and resets signals for the TSU IP available on the Renesas RZ/G3E SoC Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250227122453.30480-3-john.madieu.xa@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-03-06clk: renesas: rzv2h: Adjust for CPG_BUS_m_MSTOP starting from m = 1Biju Das
Avoid using the "- 1" for finding mstop_index in all functions accessing priv->mstop_count, by adjusting its pointer in rzv2h_cpg_probe(). While at it, drop the intermediate local variable index. Reported-by: Geert Uytterhoeven <geert+renesas@glider.be> Closes: https://lore.kernel.org/all/CAMuHMdX1gPNCFddg_DyK7Bv0BeFLOLi=5eteT_HhMH=Ph2wVvA@mail.gmail.com/ Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250222142009.41324-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-03-05clk: qcom: gcc-sm8650: Do not turn off USB GDSCs during gdsc_disable()Neil Armstrong
With PWRSTS_OFF_ON, USB GDSCs are turned off during gdsc_disable(). This can happen during scenarios such as system suspend and breaks the resume of USB controller from suspend. So use PWRSTS_RET_ON to indicate the GDSC driver to not turn off the GDSCs during gdsc_disable() and allow the hardware to transition the GDSCs to retention when the parent domain enters low power state during system suspend. Fixes: c58225b7e3d7 ("clk: qcom: add the SM8650 Global Clock Controller driver, part 1") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250305-topic-sm8650-upstream-fix-usb-suspend-v1-1-649036ab0557@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-03-05clk: samsung: update PLL locktime for PLL142XX used on FSD platformVarada Pavani
Currently PLL142XX locktime is 270. As per spec, it should be 150. Hence update PLL142XX controller locktime to 150. Cc: stable@vger.kernel.org Fixes: 4f346005aaed ("clk: samsung: fsd: Add initial clock support") Signed-off-by: Varada Pavani <v.pavani@samsung.com> Link: https://lore.kernel.org/r/20250225131918.50925-3-v.pavani@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-03-05clk: samsung: gs101: fix synchronous external abort in samsung_clk_save()Peter Griffin
EARLY_WAKEUP_SW_TRIG_*_SET and EARLY_WAKEUP_SW_TRIG_*_CLEAR registers are only writeable. Attempting to read these registers during samsung_clk_save() causes a synchronous external abort. Remove these 8 registers from cmu_top_clk_regs[] array so that system suspend gets further. Note: the code path can be exercised using the following command: echo mem > /sys/power/state Fixes: 2c597bb7d66a ("clk: samsung: clk-gs101: Add cmu_top, cmu_misc and cmu_apm support") Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20250303-clk-suspend-fix-v1-1-c2edaf66260f@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-03-04clk: Print an error when clk registration failsStephen Boyd
We have a lot of driver code that prints an error message when registering a clk fails. Do that in the core function instead to consolidate code. This also helps drivers avoid the anti-pattern of accessing the struct clk_hw::init pointer after registration. Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20250226235408.1339266-1-sboyd@kernel.org
2025-03-04clk: Correct the data types of the variables in clk_calc_new_ratesChuan Liu
In clk_calc_new_rates, the "ret" is only used to store the return value of clk_core_determine_round_nolock, and the data type of the return value of clk_core_determine_round_nolock is int. Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> Link: https://lore.kernel.org/r/20250207-correct_data_types-v1-1-f22bc7ea220d@amlogic.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-03-04clk: imgtec: use %pe for better readability of errors while printingOnkarnath
instead of printing errros as a number(%ld), it's better to print in string format for better readability of logs. Signed-off-by: Onkarnath <onkarnath.1@samsung.com> Link: https://lore.kernel.org/r/20240412090749.15392-1-onkarnath.1@samsung.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-03-04clk: stm32f4: fix an uninitialized variableDario Binacchi
The variable s, used by pr_debug() to print the mnemonic of the modulation depth in use, was not initialized. Fix the output by addressing the correct mnemonic. Fixes: 65b3516dbe50 ("clk: stm32f4: support spread spectrum clock generation") Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/r/77355eb9-19b3-46e5-a003-c21c0fae5bcd@stanley.mountain Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://lore.kernel.org/r/20250124111711.1051436-1-dario.binacchi@amarulasolutions.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-03-04clk: keystone: syscon-clk: Do not use syscon helper to build regmapAndrew Davis
The syscon helper device_node_to_regmap() is used to fetch a regmap registered to a device node. It also currently creates this regmap if the node did not already have a regmap associated with it. This should only be used on "syscon" nodes. This driver is not such a device and instead uses device_node_to_regmap() on its own node as a hacky way to create a regmap for itself. This will not work going forward and so we should create our regmap the normal way by defining our regmap_config, fetching our memory resource, then using the normal regmap_init_mmio() function. Signed-off-by: Andrew Davis <afd@ti.com> Link: https://lore.kernel.org/r/20250123181913.597304-1-afd@ti.com Tested-by: Nishanth Menon <nm@ti.com> [sboyd@kernel.org: Drop dev_err_probe() because the mapping function already does it] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-03-04clk: renesas: r7s9210: Distinguish clocks by clock typeGeert Uytterhoeven
When registering a clock, its type should be devised from the clock's type member, not from its id member. Merge the two checks for the main clock, to improve readability. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/7e61ea78e9919148e73867088ccbc3509364952e.1740126560.git.geert+renesas@glider.be
2025-03-04clk: renesas: rzg2l: Remove unneeded nullify checksGeert Uytterhoeven
RZ/G2L family clock drivers never had a need to nullify clocks. Remove the unneeded checks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/64702c33396dde2689b44d3e326aa1727ef1557a.1740126560.git.geert+renesas@glider.be
2025-03-04clk: renesas: cpg-mssr: Remove obsolete nullify checkGeert Uytterhoeven
All core clock nullify users and helpers were removed in commit b1dec4e78599a2ce ("clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*"), but the CPG/MSSR driver still checks for nullified core clocks. Remove the obsolete check. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/59ef3eccde0b0b63626480f27e77d5c68948ca98.1740126560.git.geert+renesas@glider.be
2025-03-04clk: renesas: r9a09g057: Add entries for the DMACsFabrizio Castro
Add clock and reset entries for the Renesas RZ/V2H(P) DMAC IPs. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250220150110.738619-2-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-03-03clk: qcom: videocc: Constify 'struct qcom_cc_desc'Krzysztof Kozlowski
'struct qcom_cc_desc' is passed to qcom_cc_map() and qcom_cc_really_probe() only as pointer to const, so make the memory const for safety. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250228-clk-qcom-const-v1-4-611ab80d45e4@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-03-03clk: qcom: gpucc: Constify 'struct qcom_cc_desc'Krzysztof Kozlowski
'struct qcom_cc_desc' is passed to qcom_cc_map() and qcom_cc_really_probe() only as pointer to const, so make the memory const for safety. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250228-clk-qcom-const-v1-3-611ab80d45e4@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-03-03clk: qcom: dispcc: Constify 'struct qcom_cc_desc'Krzysztof Kozlowski
'struct qcom_cc_desc' is passed to qcom_cc_map() and qcom_cc_really_probe() only as pointer to const, so make the memory const for safety. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250228-clk-qcom-const-v1-2-611ab80d45e4@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-03-03clk: qcom: camcc: Constify 'struct qcom_cc_desc'Krzysztof Kozlowski
'struct qcom_cc_desc' is passed to qcom_cc_map() and qcom_cc_really_probe() only as pointer to const, so make the memory const for safety. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20250228-clk-qcom-const-v1-1-611ab80d45e4@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-03-03clk: imx8mp: inform CCF of maximum frequency of clocksAhmad Fatoum
The IMX8MPCEC datasheet lists maximum frequencies allowed for different modules. Some of these limits are universal, but some depend on whether the SoC is operating in nominal or in overdrive mode. The imx8mp.dtsi currently assumes overdrive mode and configures some clocks in accordance with this. Boards wishing to make use of nominal mode will need to override some of the clock rates manually. As operating the clocks outside of their allowed range can lead to difficult to debug issues, it makes sense to register the maximum rates allowed in the driver, so the CCF can take them into account. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Link: https://lore.kernel.org/r/20250218-imx8m-clk-v4-6-b7697dc2dcd0@pengutronix.de Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2025-03-03clk: clk-imx8mp-audiomix: fix dsp/ocram_a clock parentsLaurentiu Mihalcea
The DSP and OCRAM_A modules from AUDIOMIX are clocked by AUDIO_AXI_CLK_ROOT, not AUDIO_AHB_CLK_ROOT. Update the clock data accordingly. Fixes: 6cd95f7b151c ("clk: imx: imx8mp: Add audiomix block control") Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com> Reviewed-by: Iuliana Prodan <iuliana.prodan@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20250226164513.33822-3-laurentiumihalcea111@gmail.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2025-03-02clk: rockchip: Add clock controller for the RK3562Finley Xiao
Add the clock tree definition for the new RK3562 SoC. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Tao Huang <huangtao@rock-chips.com> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Link: https://lore.kernel.org/r/20250227105916.2340856-3-kever.yang@rock-chips.com [dropped non-working module code, cleaned up init a bit to address build failure reported from kernel test robot Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202503021302.FjsycBI2-lkp@intel.com/ ] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-03-01clk: samsung: add initial exynos7870 clock driverKaustabh Chakraborty
This is a basic implementation of the clock driver required by Samsung's Exynos7870 SoC. It implements CMU_MIF, CMU_DISPAUD, CMU_FSYS, CMU_G3D, CMU_ISP, CMU_MFCMSCL, and CMU_PERI. all other CMUs depend on CMU_MIF. Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Link: https://lore.kernel.org/r/20250301-exynos7870-pmu-clocks-v5-2-715b646d5206@disroot.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-03-01clk: samsung: introduce Exynos2200 clock driverIvaylo Ivanov
CMU_TOP is the top level clock management unit which contains PLLs, muxes, dividers and gates that feed the other clock management units. CMU_ALIVE provides clocks for SPMI, the new MCT and other clock management units CMU_CMGP provides clocks for USI blocks CMU_HSI0 provides clocks for USB CMU_PERIC0 provides clocks for USI4 and I3C blocks CMU_PERIC1 provides clocks for USI blocks CMU_PERIC2 provides clocks for USI and I3C blocks CMU_PERIS provides clocks for GIC and the legacy MCT CMU_UFS provides clocks for UFS CMU_VTS provides clocks for other clock management units like CMU_AUD, which will be added in the future. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20250223115601.723886-4-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-03-01clk: samsung: clk-pll: add support for pll_4311Ivaylo Ivanov
pll4311 (also known in the vendor kernel as frd_4311_rpll) is a PLL used in the Exynos2200 SoC. It's an integer/fractional PLL with mid frequency FVCO (650 to 3500Mhz). The PLL is functionally similar enough to pll531x, so the same code can handle both. Locktime for pll4311 is 500 - the same as the pll531x lock factor. MDIV, PDIV, SDIV and FDIV masks and bit shifts are also the same as pll531x. When defining a PLL, the "con" parameter should be set to CON3 register, like this: PLL(pll_4311, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL), Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20250223115601.723886-3-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-02-27clk: mediatek: Add SMI LARBs reset for MT8188Friday Yang
SMI LARBs require reset functions when MTCMOS powers on or off. Add reset platform data for SMI LARBs in the image, camera and IPE subsystems. Signed-off-by: Friday Yang <friday.yang@mediatek.com> Link: https://lore.kernel.org/r/20250221075058.14180-3-friday.yang@mediatek.com Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-02-27clk: rockchip: rk3528: Add reset lookup tableJonas Karlman
In the commit 5d0eb375e685 ("clk: rockchip: Add clock controller driver for RK3528 SoC") only the dt-binding header was added for the reset controller for the RK3528 SoC. Add a reset lookup table generated from the SRST symbols used by vendor linux-6.1-stan-rkr5 kernel to complete support for the reset controller. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250227175302.2950788-1-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-26clk: mediatek: mt8188-vdo1: Add VDO1_DPI1_HDMI clock for hdmitxAngeloGioacchino Del Regno
Add a missing clock found in the VDO1 controller for the HDMI TX controller over DPI1. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250212100342.33618-2-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-02-26clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parentKrzysztof Kozlowski
The parent of disp_cc_mdss_byte0_intf_clk clock should not propagate up the rates, because this messes up entire clock hierarchy when setting clock rates in MSM DSI driver. The dsi_link_clk_set_rate_6g() first sets entire clock hierarchy rates via dev_pm_opp_set_rate() on byte clock and then sets individual clock rates, like pixel and byte_intf clocks, to proper frequencies. Having CLK_SET_RATE_PARENT caused that entire tree was re-calced and the byte clock received halved frequency. Drop CLK_SET_RATE_PARENT to fix this and align with SM8550 and SM8650. Fixes: f1080d8dab0f ("clk: qcom: dispcc-sm8750: Add SM8750 Display clock controller") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250129154519.209791-1-krzysztof.kozlowski@linaro.org Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-02-26clk: check for disabled clock-provider in of_clk_get_hw_from_clkspec()Heiko Stuebner
of_clk_get_hw_from_clkspec() checks all available clock-providers by comparing their of nodes to the one from the clkspec. If no matching clock provider is found, the function returns -EPROBE_DEFER to cause a re-check at a later date. If a matching clock provider is found, an authoritative answer can be retrieved from it whether the clock exists or not. This does not take into account that the clock-provider may never appear, because it's node is disabled. This can happen when a clock is optional, provided by a separate block which never gets enabled. One example of this happening is the rk3588's VOP, which has optional additional display clocks coming from PLLs inside the hdmiphy blocks. These can be used for better rates, but the system will also work without them. The problem around that is described in the followups to[1]. As we already know the of node of the presumed clock provider, add a check via of_device_is_available() whether this is a "valid" device node. This prevents eternal defer loops. Link: https://lore.kernel.org/dri-devel/20250215-vop2-hdmi1-disp-modes-v1-3-81962a7151d6@collabora.com/ [1] Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Tested-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250222223733.2990179-1-heiko@sntech.de [sboyd@kernel.org: Reword commit text a bit] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-02-26clk: rockchip: Add clock controller driver for RK3528 SoCYao Zi
Add clock tree definition for RK3528. Similar to previous Rockchip SoCs, clock controller of RK3528 is combined with the reset controller. We omit the reset part for now since it's hard to test it without support for other basic peripherals. Signed-off-by: Yao Zi <ziyao@disroot.org> Link: https://lore.kernel.org/r/20250217061142.38480-8-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-26clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODEYao Zi
RK3528 comes with a new PLL variant: its "PPLL", which mainly generates clocks for the PCIe controller, operates in normal mode only. Let's describe it with flag ROCKCHIP_PLL_FIXED_MODE and handle it in code. Signed-off-by: Yao Zi <ziyao@disroot.org> Link: https://lore.kernel.org/r/20250217061142.38480-7-ziyao@disroot.org Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-26clk: rockchip: rk3328: fix wrong clk_ref_usb3otg parentPeter Geis
Correct the clk_ref_usb3otg parent to fix clock control for the usb3 controller on rk3328. Verified against the rk3328 trm, the rk3228h trm, and the rk3328 usb3 phy clock map. Fixes: fe3511ad8a1c ("clk: rockchip: add clock controller for rk3328") Signed-off-by: Peter Geis <pgwipeout@gmail.com> Reviewed-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/20250115012628.1035928-2-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-26clk: rockchip: rk3568: mark hclk_vi as criticalMichael Riesch
The clock 'pclk_vi_niu' has a dependency on 'hclk_vi_niu' according to the Technical Reference Manual section '2.8.6 NIU Clock gating reliance'. However, this kind of dependency cannot be addressed properly at the moment (until the support for linked clocks is implemented for the RK3568). As an intermediate solution, mark the hclk_vi as critical on the Rockchip RK3568. Suggested-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net> Link: https://lore.kernel.org/r/20250210-rk3568-hclk-vi-v1-1-9ade2626f638@wolfvision.net Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2025-02-26clk: rockchip: rk3188: use PCLK_CIF0/1 clock IDs on RK3066Val Packett
RK3066 has two "CIF" video capture interface blocks, reference the newly added IDs for their PCLK clocks. Signed-off-by: Val Packett <val@packett.cool> Link: https://lore.kernel.org/r/20241205182954.5346-2-val@packett.cool Signed-off-by: Heiko Stuebner <heiko@sntech.de>
generated by cgit (git 2.34.1) at 2025-07-15 18:01:50 +0000