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path: root/drivers/clk
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2024-11-14clk: en7523: remove REG_PCIE*_{MEM,MEM_MASK} configurationLorenzo Bianconi
REG_PCIE*_MEM and REG_PCIE*_MEM_MASK regs (PBUS_CSR memory region) are not part of the scu block on the EN7581 SoC and they are used to select the PCIE ports on the PBUS, so remove this configuration from the clock driver and set these registers in the PCIE host driver instead. This patch does not introduce any backward incompatibility since the dts for EN7581 SoC is not upstream yet. Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/20241112-clk-en7581-syscon-v2-2-8ada5e394ae4@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-11-14clk: mediatek: Add drivers for MT6735 syscon clock and reset controllersYassine Oudjana
Add drivers for IMGSYS, MFGCFG, VDECSYS and VENCSYS clocks and resets on MT6735. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Link: https://lore.kernel.org/r/20241106111402.200940-3-y.oudjana@protonmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-11-14clk: mediatek: mt6735-apmixedsys: Fix an error handling path in ↵Christophe JAILLET
clk_mt6735_apmixed_probe() If an error occurs after a successful mtk_alloc_clk_data(), mtk_free_clk_data() should be called, as already done in the .remove() function. Switch to mtk_devm_alloc_clk_data() in order to fix the memory leak in the probe function, and simplify the remove function. Fixes: 43c04ed79189 ("clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers") Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lore.kernel.org/r/89ad840e7a484eaf4727470824acfe0fdc60fcef.1729871146.git.christophe.jaillet@wanadoo.fr Tested-by: Yassine Oudjana <y.oudjana@protonmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-11-14clk: ralink: mtmips: add mmc related clocks for SoCs MT7620, MT7628 and MT7688Sergio Paracuellos
Original architecture clock code from where this driver was derived did not include nothing related to mmc clocks. OpenWRT people started to use mtk-sd upstream driver recently and they were forced to use a dts 'fixed-clock' node with 48 MHz clock: - https://github.com/openwrt/openwrt/pull/15896 The proper thing to do to avoid that is to add the mmc related clocks to the driver to avoid a dts with fixed clocks nodes. The minimal documentation in the mt7620 programming guide says that there is a BBP_PLL clock of 480 MHz derived from the 40 MHz XTAL and from there a clock divider by ten produces the desired SDHC clock of 48 MHz for the mmc. Hence add a fixed clock 'bbppll' and factor clock 'sdhc' ten divider child to properly set the 'mmc' peripheral clock with the desired 48 Mhz rate. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20240910044024.120009-4-sergio.paracuellos@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-11-14clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCsSergio Paracuellos
Base clocks are the first in being probed and are real dependencies of the rest of fixed, factor and peripheral clocks. For old ralink SoCs RT2880, RT305x and RT3883 'xtal' must be defined first since in any other case, when fixed clocks are probed they are delayed until 'xtal' is probed so the following warning appears: WARNING: CPU: 0 PID: 0 at drivers/clk/ralink/clk-mtmips.c:499 rt3883_bus_recalc_rate+0x98/0x138 Modules linked in: CPU: 0 PID: 0 Comm: swapper Not tainted 6.6.43 #0 Stack : 805e58d0 00000000 00000004 8004f950 00000000 00000004 00000000 00000000 80669c54 80830000 80700000 805ae570 80670068 00000001 80669bf8 00000000 00000000 00000000 805ae570 80669b38 00000020 804db7dc 00000000 00000000 203a6d6d 80669b78 80669e48 70617773 00000000 805ae570 00000000 00000009 00000000 00000001 00000004 00000001 00000000 00000000 83fe43b0 00000000 ... Call Trace: [<800065d0>] show_stack+0x64/0xf4 [<804bca14>] dump_stack_lvl+0x38/0x60 [<800218ac>] __warn+0x94/0xe4 [<8002195c>] warn_slowpath_fmt+0x60/0x94 [<80259ff8>] rt3883_bus_recalc_rate+0x98/0x138 [<80254530>] __clk_register+0x568/0x688 [<80254838>] of_clk_hw_register+0x18/0x2c [<8070b910>] rt2880_clk_of_clk_init_driver+0x18c/0x594 [<8070b628>] of_clk_init+0x1c0/0x23c [<806fc448>] plat_time_init+0x58/0x18c [<806fdaf0>] time_init+0x10/0x6c [<806f9bc4>] start_kernel+0x458/0x67c ---[ end trace 0000000000000000 ]--- When this driver was mainlined we could not find any active users of old ralink SoCs so we cannot perform any real tests for them. Now, one user of a Belkin f9k1109 version 1 device which uses RT3883 SoC appeared and reported some issues in openWRT: - https://github.com/openwrt/openwrt/issues/16054 Thus, define a 'rt2880_xtal_recalc_rate()' just returning the expected frequency 40Mhz and use it along the old ralink SoCs to have a correct boot trace with no warnings and a working clock plan from the beggining. Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs") Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20240910044024.120009-3-sergio.paracuellos@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-11-14clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883Sergio Paracuellos
Clock plan for Ralink SoC RT3883 needs an extra 'periph' clock to properly set some peripherals that has this clock as their parent. When this driver was mainlined we could not find any active users of this SoC so we cannot perform any real tests for it. Now, one user of a Belkin f9k1109 version 1 device which uses this SoC appear and reported some issues in openWRT: - https://github.com/openwrt/openwrt/issues/16054 The peripherals that are wrong are 'uart', 'i2c', 'i2s' and 'uartlite' which has a not defined 'periph' clock as parent. Hence, introduce it to have a properly working clock plan for this SoC. Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs") Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20240910044024.120009-2-sergio.paracuellos@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-11-14clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUXArnd Bergmann
As in most cases, using 'imply' is wrong here and does not prevent build failures since that code may not be visible to a built-in clk driver: axg-audio.c:(.text+0x15c): undefined reference to `devm_meson_rst_aux_register' Replace the incorrt 'imply' with the necessary 'depends on'. Fixes: 664988eb47dd ("clk: amlogic: axg-audio: use the auxiliary reset driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20241111102932.3209861-1-arnd@kernel.org Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-11-14clk: clk-apple-nco: Add NULL check in applnco_probeCharles Han
Add NULL check in applnco_probe, to handle kernel NULL pointer dereference error. Fixes: 6641057d5dba ("clk: clk-apple-nco: Add driver for Apple NCO") Signed-off-by: Charles Han <hanchunchao@inspur.com> Link: https://lore.kernel.org/r/20241114072820.3071-1-hanchunchao@inspur.com Reviewed-by: Martin Povišer <povik+lin@cutebit.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-11-11clk: qcom: remove unused data from gcc-ipq5424.cArnd Bergmann
The newly added driver causes a warnings when enabling -Wunused-const-variables: drivers/clk/qcom/gcc-ipq5424.c:1064:30: error: 'ftbl_gcc_q6_axi_clk_src' defined but not used [-Werror=unused-const-variable=] 1064 | static const struct freq_tbl ftbl_gcc_q6_axi_clk_src[] = { | ^~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/qcom/gcc-ipq5424.c:957:30: error: 'ftbl_gcc_qpic_clk_src' defined but not used [-Werror=unused-const-variable=] 957 | static const struct freq_tbl ftbl_gcc_qpic_clk_src[] = { | ^~~~~~~~~~~~~~~~~~~~~ drivers/clk/qcom/gcc-ipq5424.c:497:30: error: 'ftbl_gcc_qupv3_2x_core_clk_src' defined but not used [-Werror=unused-const-variable=] 497 | static const struct freq_tbl ftbl_gcc_qupv3_2x_core_clk_src[] = { | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In order to hopefully enable this warning by default in the future, remove the data for now. If it gets used in the future, it can trivially get added back. Fixes: 21b5d5a4a311 ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241111103258.3336183-1-arnd@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-10Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: "A handful of Qualcomm clk driver fixes: - Correct flags for X Elite USB MP GDSC and pcie pipediv2 clocks - Fix alpha PLL post_div mask for the cases where width is not specified - Avoid hangs in the SM8350 video driver (venus) by setting HW_CTRL trigger feature on the video clocks" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: qcom: gcc-x1e80100: Fix USB MP SS1 PHY GDSC pwrsts flags clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks clk: qcom: clk-alpha-pll: Fix pll post div mask when width is not set clk: qcom: videocc-sm8350: use HW_CTRL_TRIGGER for vcodec GDSCs
2024-11-06clk: renesas: vbattb: Add VBATTB clock driverClaudiu Beznea
The VBATTB IP of the Renesas RZ/G3S SoC controls the clock that is used by the RTC. The input to the VBATTB could be a 32KHz crystal or an external clock device. The HW block diagram for the clock generator is as follows: +----------+ XC `\ RTXIN --->| |----->| \ +----+ VBATTCLK | 32K clock| | |----->|gate|-----------> | osc | XBYP | | +----+ RTXOUT --->| |----->| / +----------+ , After discussions w/ Stephen Boyd the clock tree associated with this hardware block was exported in Linux as: vbattb-xtal xbyp xc mux vbattbclk where: - input-xtal is the input clock (connected to RTXIN, RTXOUT pins) - xc, xbyp are mux inputs - mux is the internal mux - vbattclk is the gate clock that feeds in the end the RTC to allow selecting the input of the MUX though assigned-clock DT properties, using the already existing clock drivers and avoid adding other DT properties. If the crystal is connected on RTXIN, RTXOUT pins the XC will be selected as mux input. If an external clock device is connected on RTXIN, RTXOUT pins the XBYP will be selected as mux input. The load capacitance of the internal crystal can be configured with renesas,vbattb-load-nanofarads DT property. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20241101095720.2247815-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-11-05clk: qcom: Add support for Global Clock Controller on QCS8300Imran Shaik
Add support for Global Clock Controller on QCS8300 platform. Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Reviewed-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20240822-qcs8300-gcc-v2-2-b310dfa70ad8@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoCSricharan Ramabadhran
Add support for the global clock controller found on IPQ5424 SoC. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> Link: https://lore.kernel.org/r/20241028060506.246606-4-quic_srichara@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574Devi Priya
Add support for NSS Huayra alpha pll found on ipq9574 SoCs. Programming sequence is the same as that of Huayra type Alpha PLL, so we can re-use the same. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> Link: https://lore.kernel.org/r/20241028060506.246606-2-quic_srichara@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05clk: qcom: add SAR2130P GPU Clock Controller supportKonrad Dybcio
Add support for the GPU Clock Controller as used on the SAR2130P and SAR1130P platforms. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-11-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05clk: qcom: dispcc-sm8550: enable support for SAR2130PDmitry Baryshkov
The display clock controller on SAR2130P is very close to the clock controller on SM8550 (and SM8650). Reuse existing driver to add support for the controller on SAR2130P. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-10-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05clk: qcom: tcsrcc-sm8550: add SAR2130P supportDmitry Baryshkov
The SAR2130P platform has the same TCSR Clock Controller as the SM8550, except for the lack of the UFS clocks. Extend the SM8550 TCSRCC driver to support SAR2130P. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-9-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05clk: qcom: add support for GCC on SAR2130PDmitry Baryshkov
Add driver for the Global Clock Controller as present on the Qualcomm SAR2130P platform. This is based on the msm-5.10 tree, tag KERNEL.PLATFORM.1.0.r4-00400-NEO.0. Co-developed-by: Kalpak Kawadkar <quic_kkawadka@quicinc.com> Signed-off-by: Kalpak Kawadkar <quic_kkawadka@quicinc.com> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-8-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05clk: qcom: rpmh: add support for SAR2130PDmitry Baryshkov
Define clocks as supported by the RPMh on the SAR2130P platform. The msm-5.10 kernel declares just the CXO clock, the RF_CLK1 clock was added following recommendation from Taniya Das. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-7-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05clk: qcom: rcg2: add clk_rcg2_shared_floor_opsDmitry Baryshkov
Generally SDCC clocks use clk_rcg2_floor_ops, however on SAR2130P platform it's recommended to use rcg2_shared_ops for all Root Clock Generators to park them instead of disabling. Implement a mix of those, clk_rcg2_shared_floor_ops. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-6-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05Merge tag 'qcom-clk-fixes-for-6.12' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-fixes Pull Qualcomm clk driver fixes from Bjorn Andersson: - Correct flags for X Elite USB MP GDSC and pcie pipediv2 clocks - Fix alpha PLL post_div mask for the cases where width is not specified - Avoid hangs in the SM8350 video driver (venus) by setting HW_CTRL trigger feature on the video clocks * tag 'qcom-clk-fixes-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: clk: qcom: gcc-x1e80100: Fix USB MP SS1 PHY GDSC pwrsts flags clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks clk: qcom: clk-alpha-pll: Fix pll post div mask when width is not set clk: qcom: videocc-sm8350: use HW_CTRL_TRIGGER for vcodec GDSCs
2024-11-05clk: sunxi-ng: Use of_property_present() for non-boolean propertiesRob Herring (Arm)
The use of of_property_read_bool() for non-boolean properties is deprecated in favor of of_property_present() when testing for property presence. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20241104190455.272527-1-robh@kernel.org Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2024-11-05clk: imx: imx8-acm: Fix return value check in clk_imx_acm_attach_pm_domains()Yang Yingliang
If device_link_add() fails, it returns NULL pointer not ERR_PTR(), replace IS_ERR() with NULL pointer check, and return -EINVAL. Fixes: d3a0946d7ac9 ("clk: imx: imx8: add audio clock mux driver") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20241026112452.1523-1-yangyingliang@huaweicloud.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-11-05clk: imx: lpcg-scu: Skip HDMI LPCG clock save/restorePeng Fan
On i.MX8QM, HDMI LPCG clocks operation needs SCU clock "hdmi_ipg_clk" to be ON. While during noirq suspend phase, "hdmi_ipg_clk" is disabled by HDMI IRQ STEER driver, so SError will be triggered when accessing the HDMI LPCG registers. Skip all HDMI LPCG clocks save/restore to avoid SError during system suspend/resume, it will NOT introduce additional power consumption as their parent clock is disabled when suspend. Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20241027-imx-clk-v1-v3-5-89152574d1d7@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-11-05clk: imx: clk-scu: fix clk enable state save and restoreDong Aisheng
The scu clk_ops only inplements prepare() and unprepare() callback. Saving the clock state during suspend by checking clk_hw_is_enabled() is not safe as it's possible that some device drivers may only disable the clocks without unprepare. Then the state retention will not work for such clocks. Fixing it by checking clk_hw_is_prepared() which is more reasonable and safe. Fixes: d0409631f466 ("clk: imx: scu: add suspend/resume support") Reviewed-by: Peng Fan <peng.fan@nxp.com> Tested-by: Carlos Song <carlos.song@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/20241027-imx-clk-v1-v3-4-89152574d1d7@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-11-05clk: imx: fracn-gppll: fix pll power upPeng Fan
To i.MX93 which features dual Cortex-A55 cores and DSU, when using writel_relaxed to write value to PLL registers, the value might be buffered. To make sure the value has been written into the hardware, using readl to read back the register could achieve the goal. current PLL power up flow can be simplified as below: 1. writel_relaxed to set the PLL POWERUP bit; 2. readl_poll_timeout to check the PLL lock bit: a). timeout = ktime_add_us(ktime_get(), timeout_us); b). readl the pll the lock reg; c). check if the pll lock bit ready d). check if timeout But in some corner cases, both the write in step 1 and read in step 2 will be blocked by other bus transaction in the SoC for a long time, saying the value into real hardware is just before step b). That means the timeout counting has begins for quite sometime since step a), but value still not written into real hardware until bus released just at a point before step b). Then there maybe chances that the pll lock bit is not ready when readl done but the timeout happens. readl_poll_timeout will err return due to timeout. To avoid such unexpected failure, read back the reg to make sure the write has been done in HW reg. So use readl after writel_relaxed to fix the issue. Since we are here, to avoid udelay to run before writel_relaxed, use readl before udelay. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Co-developed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20241027-imx-clk-v1-v3-3-89152574d1d7@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-11-05clk: imx: fracn-gppll: correct PLL initialization flowPeng Fan
Per i.MX93 Reference Mannual 22.4 Initialization information 1. Program appropriate value of DIV[ODIV], DIV[RDIV] and DIV[MFI] as per Integer mode. 2. Wait for 5 μs. 3. Program the following field in CTRL register. Set CTRL[POWERUP] to 1'b1 to enable PLL block. 4. Poll PLL_STATUS[PLL_LOCK] register, and wait till PLL_STATUS[PLL_LOCK] is 1'b1 and pll_lock output signal is 1'b1. 5. Set CTRL[CLKMUX_EN] to 1'b1 to enable PLL output clock. So move the CLKMUX_EN operation after PLL locked. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Co-developed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20241027-imx-clk-v1-v3-2-89152574d1d7@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-11-05clk: imx: lpcg-scu: SW workaround for errata (e10858)Peng Fan
Back-to-back LPCG writes can be ignored by the LPCG register due to a HW bug. The writes need to be separated by at least 4 cycles of the gated clock. See https://www.nxp.com.cn/docs/en/errata/IMX8_1N94W.pdf The workaround is implemented as follows: 1. For clocks running greater than or equal to 24MHz, a read followed by the write will provide sufficient delay. 2. For clocks running below 24MHz, add a delay of 4 clock cylces after the write to the LPCG register. Fixes: 2f77296d3df9 ("clk: imx: add lpcg clock support") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20241027-imx-clk-v1-v3-1-89152574d1d7@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-11-03clk: qcom: Make GCC_6125 depend on QCOM_GDSCKonrad Dybcio
Like all other non-ancient Qualcomm clock drivers, QCOM_GDSC is required, as the GCC driver defines and instantiates a bunch of GDSCs. Add the missing dependency. Reported-by: Kamil Gołda <kamil.golda@protonmail.com> Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20241003-topic-6125kconfig-v1-1-f5e1efbff07c@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-03clk: renesas: rzg2l: Fix FOUTPOSTDIV clkBiju Das
While computing foutpostdiv_rate, the value of params->pl5_fracin is discarded, which results in the wrong refresh rate. Fix the formula for computing foutpostdiv_rate. Fixes: 1561380ee72f ("clk: renesas: rzg2l: Add FOUTPOSTDIV clk support") Signed-off-by: Hien Huynh <hien.huynh.px@renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241024134236.315289-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-11-02clk: sunxi-ng: d1: Fix PLL_AUDIO0 presetAndre Przywara
To work around a limitation in our clock modelling, we try to force two bits in the AUDIO0 PLL to 0, in the CCU probe routine. However the ~ operator only applies to the first expression, and does not cover the second bit, so we end up clearing only bit 1. Group the bit-ORing with parentheses, to make it both clearer to read and actually correct. Fixes: 35b97bb94111 ("clk: sunxi-ng: Add support for the D1 SoC clocks") Signed-off-by: Andre Przywara <andre.przywara@arm.com> Link: https://patch.msgid.link/20241001105016.1068558-1-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2024-10-30clk: starfive: jh7110-pll: Mark the probe function as __initChanghuang Liang
Mark the jh7110_pll_probe function as __init. There's no need to support hotplugging in the jh7110-pll driver. We use builtin_platform_driver_probe, the probe function will only be called at startup. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Link: https://lore.kernel.org/r/20241029032828.238706-1-changhuang.liang@starfivetech.com Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-10-28clk: sophgo: avoid integer overflow in sg2042_pll_recalc_rate()Zichen Xie
This was found by a static analyzer. There may be a potential integer overflow issue in sg2042_pll_recalc_rate(). numerator is defined as u64 while parent_rate is defined as unsigned long and ctrl_table.fbdiv is defined as unsigned int. On 32-bit machine, the result of the calculation will be limited to "u32" without correct casting. Integer overflow may occur on high-performance systems. Fixes: 48cf7e01386e ("clk: sophgo: Add SG2042 clock driver") Signed-off-by: Zichen Xie <zichenxie0106@gmail.com> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Link: https://lore.kernel.org/r/20241023145146.13130-1-zichenxie0106@gmail.com Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-10-28clk: eyeq: add driverThéo Lebrun
Add Mobileye EyeQ5, EyeQ6L and EyeQ6H clock controller driver. It is both a platform driver and a hook onto of_clk_init() used for clocks required early (GIC timer, UARTs). For some compatible, it is both at the same time. eqc_early_init() initialises early PLLs and exposes its own clock provider. It marks other clocks as deferred. eqc_probe() adds all remaining clocks using another clock provider. It exposes read-only PLLs derived from the main crystal on board. It also exposes another type of clocks: divider clocks. They always have even divisors and have one PLL as parent. This driver also bears the responsability for optional reset and pinctrl auxiliary devices. The match data attached to the devicetree node compatible indicate if such devices should be created. They all get passed a pointer to the start of the OLB region. Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Link: https://lore.kernel.org/r/20241023-mbly-clk-v6-1-ca83e43daf93@bootlin.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-10-28clk: tegra: use clamp() in tegra_bpmp_clk_determine_rate()Li Zetao
When it needs to get a value within a certain interval, using clamp() makes the code easier to understand than min(max()). Signed-off-by: Li Zetao <lizetao1@huawei.com> Link: https://lore.kernel.org/r/20240830012344.603704-1-lizetao1@huawei.com Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-10-26clk: samsung: Introduce Exynos8895 clock driverIvaylo Ivanov
CMU_TOP is the top level clock management unit which contains PLLs, muxes, dividers and gates that feed the other clock management units. CMU_PERIS provides clocks for GIC and MCT CMU_FSYS0 provides clocks for USBDRD30 CMU_FSYS1 provides clocks for MMC, UFS and PCIE CMU_PERIC0 provides clocks for UART_DBG, USI00 ~ USI03 CMU_PERIC1 provides clocks for SPI_CAM0/1, UART_BT, USI04 ~ USI13, HSI2C_CAM0/1/2/3 Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20241023090136.537395-4-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-26clk: samsung: clk-pll: Add support for pll_{1051x,1052x}Ivaylo Ivanov
These plls are found in the Exynos8895 SoC: - pll1051x: Integer PLL with middle frequency - pll1052x: Integer PLL with low frequency The PLLs are similar enough to pll_0822x, so the same code can handle all. Locktime for 1051x, 1052x is 150 - the same as the pll_0822x lock factor. MDIV, SDIV, PDIV masks and bit shifts are also the same as 0822x. When defining a PLL, the "con" parameter should be set to CON0 register, like this: PLL(pll_1051x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, pll_shared0_rate_table), Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Link: https://lore.kernel.org/r/20241023090136.537395-3-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2024-10-25clk: sunxi-ng: Constify struct ccu_reset_mapChristophe JAILLET
'struct ccu_reset_map' are not modified in these drivers. Constifying this structure moves some data to a read-only section, so increase overall security. On a x86_64, with allmodconfig, as an example: Before: ====== text data bss dec hex filename 1533 2224 0 3757 ead drivers/clk/sunxi-ng/ccu-sun20i-d1-r.o After: ===== text data bss dec hex filename 1597 2160 0 3757 ead drivers/clk/sunxi-ng/ccu-sun20i-d1-r.o Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://patch.msgid.link/44745f27034fa670605cd16966a39b7fe88fe5a6.1726863905.git.christophe.jaillet@wanadoo.fr Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2024-10-25clk: sunxi-ng: h616: Add sigma-delta modulation settings for audio PLLRyan Walklin
Allwinner has previously released a H616 audio driver which also provides sigma-delta modulation for the audio PLL clocks. This approach is used in other Allwinner SoCs, including the H3 and A64. The manual-provided clock values are: PLL_AUDIO(hs) = 24 MHz*N/M1 PLL_AUDIO(4X) = 24 MHz*N/M0/M1/P PLL_AUDIO(2X) = 24 MHz*N/M0/M1/P/2 PLL_AUDIO(1X) = 24 MHz*N/M0/M1/P/4 A fixed post-divider of 2 is used to account for a M0 divider of 2, which cannot be modelled by the existing macros and ccu_nm struct. Add SDM to the H616 clock control unit driver. Signed-off-by: Ryan Walklin <ryan@testtoast.com> Tested-by: Marcus Cooper <codekipper@gmail.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Link: https://patch.msgid.link/20241023075917.186835-2-ryan@testtoast.com [wens@csie.org: Fixed whitespace errors] Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2024-10-25clk: renesas: r9a08g045: Add power domain for RTCClaudiu Beznea
The RTC and VBATTB don't share the MSTOP control bit (but only the bus clock and the reset signal). As the MSTOP control is modeled though power domains add power domain support for the RTC device available on the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241019084738.3370489-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-25clk: renesas: r9a08g045: Mark the watchdog and always-on PM domains as IRQ safeClaudiu Beznea
If the watchdog is part of a dedicated power domain (as it may be on RZ/G3S) the watchdog PM domain need to be powered on in the watchdog restart handler. Currently, only the clocks are enabled in the watchdog restart handler. To be able to also power on the PM domain we need to call pm_runtime_resume_and_get() on the watchdog restart handler, mark the watchdog device as IRQ safe and register the watchdog PM domain with GENPD_FLAG_IRQ_SAFE. Register watchdog PM domain as IRQ safe. Along with it the always-on PM domain (parent of the watchdog domain) was marked as IRQ safe. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/20241015164732.4085249-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-25clk: renesas: rzg2l-cpg: Use GENPD_FLAG_* flags instead of local onesClaudiu Beznea
For watchdog PM domain it is necessary to provide GENPD_FLAG_IRQ_SAFE flag to be able to power on the watchdog PM domain from atomic context. For this, adjust the current infrastructure to be able to provide GENPD_FLAG_* for individual PM domains. With this, remove the always_on flag from rzg2l_cpg_add_pm_domains() as it is not necessary anymore. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/20241015164732.4085249-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-25clk: renesas: rzg2l-cpg: Move PM domain power on in rzg2l_cpg_pd_setup()Claudiu Beznea
Move the PM domain power on in rzg2l_cpg_pd_setup(). With this the previously always-on power domains got struct generic_pm_domain::{power_on, power_off} populated (and registered with simple_qos_governor if #power-domain-cells = <1> and with pm_domain_always_on_gov if #power-domain-cells = <0>). The values for struct generic_pm_domain::{power_on, power_off} are now populated for all registered domains but used by core only for the domains that can use them (the PM domain should be non always-on and registered with simple_qos_governor). Moreover, the power on/off functions check if the mstop support is valid. The mstop is populated only by the RZ/G3S initialization code at the moment. This approach was chosen to keep the code simple and use the same code across different implementations. There should be no issues with this approach as the always on domains are registered with GENPD_FLAG_ALWAYS_ON and the PM domain core takes care of it. This approach allows doing further cleanups on the rzg2l_cpg power domain registering code that will be handled by the next commit. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/20241015164732.4085249-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2024-10-23clk: imx: add i.MX91 clkPengfei Li
Reuse i.MX93 clk driver for i.MX91, because i.MX91 reuses the Clock Control Module from i.MX93, with only a few clocks removed and a few clocks added. For clocks specific to i.MX93 use PLAT_IMX93 to flag them, for clocks specific to i.MX91, use PLAT_IMX91 to flag them. Others are shared by both. Signed-off-by: Pengfei Li <pengfei.li_1@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20241023184651.381265-5-pengfei.li_1@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-10-23clk: imx93: Move IMX93_CLK_END macro to clk driverPengfei Li
IMX93_CLK_END was previously defined in imx93-clock.h to indicate the number of clocks. However, it is not part of the ABI. For starters it does no really appear in DTS. But what's more important - new clocks are described later, which contradicts this define in binding header. So move this macro to clock driver. Signed-off-by: Pengfei Li <pengfei.li_1@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20241023184651.381265-2-pengfei.li_1@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
2024-10-23clk: qcom: ipq9574: remove q6 bring up clocksManikanta Mylavarapu
Q6 firmware takes care of bringup clocks, so remove them from gcc driver. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Link: https://lore.kernel.org/r/20240820055618.267554-3-quic_gokulsri@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-23clk: qcom: ipq5332: remove q6 bring up clocksManikanta Mylavarapu
Q6 firmware takes care of bringup clocks, so remove them from gcc driver. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com> Link: https://lore.kernel.org/r/20240820055618.267554-2-quic_gokulsri@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22clk: qcom: clk-alpha-pll: fix lucid 5lpe pll enabled checkJohan Hovold
The lucid 5lpe PLL enable check only checks for an impossible negative return value and does not actually return as intended in case the PLL is already enabled (e.g. has been left enabled by boot firmware). Fixes: f4c7e27aa4b6 ("clk: qcom: clk-alpha-pll: Add support for Lucid 5LPE PLL") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20241022080521.359-3-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22clk: qcom: clk-alpha-pll: drop lucid-evo pll enabled warningJohan Hovold
The boot firmware may have left the display enabled and its PLL running, which currently generates a warning on boot (e.g. on x1e80100): disp_cc_pll0 PLL is already enabled Drop the bogus warning and fix up the PLL enabled error handling (trion_pll_is_enabled() only returns 0 or 1). Fixes: d1b121d62b7e ("clk: qcom: Add LUCID_EVO PLL type for SDX65") Signed-off-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20241022080521.359-2-johan+linaro@kernel.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22clk: qcom: gcc-qcs404: fix initial rate of GPLL3Gabor Juhos
The comment before the config of the GPLL3 PLL says that the PLL should run at 930 MHz. In contrary to this, calculating the frequency from the current configuration values by using 19.2 MHz as input frequency defined in 'qcs404.dtsi', it gives 921.6 MHz: $ xo=19200000; l=48; alpha=0x0; alpha_hi=0x0 $ echo "$xo * ($((l)) + $(((alpha_hi << 32 | alpha) >> 8)) / 2^32)" | bc -l 921600000.00000000000000000000 Set 'alpha_hi' in the configuration to a value used in downstream kernels [1][2] in order to get the correct output rate: $ xo=19200000; l=48; alpha=0x0; alpha_hi=0x70 $ echo "$xo * ($((l)) + $(((alpha_hi << 32 | alpha) >> 8)) / 2^32)" | bc -l 930000000.00000000000000000000 The change is based on static code analysis, compile tested only. [1] https://git.codelinaro.org/clo/la/kernel/msm-5.4/-/blob/kernel.lnx.5.4.r56-rel/drivers/clk/qcom/gcc-qcs404.c?ref_type=heads#L335 [2} https://git.codelinaro.org/clo/la/kernel/msm-5.15/-/blob/kernel.lnx.5.15.r49-rel/drivers/clk/qcom/gcc-qcs404.c?ref_type=heads#L127 Cc: stable@vger.kernel.org Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Link: https://lore.kernel.org/r/20241022-fix-gcc-qcs404-gpll3-v1-1-c4d30d634d19@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit (git 2.34.1) at 2025-07-18 15:11:47 +0000