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2020-08-05Merge branch 'pci/doc'Bjorn Helgaas
- Fix several kerneldoc warnings (Krzysztof Kozlowski) * pci/doc: PCI: Fix kerneldoc warnings
2020-08-05Merge branch 'pci/host-probe-refactor'Bjorn Helgaas
- Use pci_host_bridge.windows list directly instead of splicing in a temporary list for cadence, mvebu, host-common (Rob Herring) - Use pci_host_probe() instead of open-coding all the pieces for altera, brcmstb, iproc, mobiveil, rcar, rockchip, tegra, v3, versatile, xgene, xilinx, xilinx-nwl (Rob Herring) - Convert to devm_platform_ioremap_resource_byname() instead of open-coding platform_get_resource_byname() and devm_ioremap_resource() for altera, cadence, mediatek, rockchip, tegra, xgene (Dejin Zheng) - Convert to devm_platform_ioremap_resource() instead of open-coding platform_get_resource() and devm_ioremap_resource() for aardvark, brcmstb, exynos, ftpci100, versatile (Dejin Zheng) - Remove redundant error messages from devm_pci_remap_cfg_resource() callers (Dejin Zheng) - Drop useless PCI_ENABLE_PROC_DOMAINS from versatile driver (Rob Herring) - Default host bridge parent device to the platform device (Rob Herring) - Drop unnecessary zeroing of host bridge fields (Rob Herring) - Use pci_is_root_bus() instead of tracking root bus number separately in aardvark, designware (imx6, keystone, designware-host), mobiveil, xilinx-nwl, xilinx, rockchip, rcar (Rob Herring) - Set host bridge bus number in pci_scan_root_bus_bridge() instead of each driver for aardvark, designware-host, host-common, mediatek, rcar, tegra, v3-semi (Rob Herring) - Use bridge resources instead of parsing DT 'ranges' again for cadence (Rob Herring) - Remove private bus number and range from cadence (Rob Herring) - Use devm_pci_alloc_host_bridge() to simplify rcar (Rob Herring) - Use struct pci_host_bridge.windows list directly rather than a temporary (Rob Herring) - Reduce OF "missing non-prefetchable window" from error to warning message (Rob Herring) - Convert rcar-gen2 from old Arm-specific pci_common_init_dev() to new arch-independent interfaces (Rob Herring) - Move DT resource setup into devm_pci_alloc_host_bridge() (Rob Herring) - Set bridge map_irq and swizzle_irq to default functions; drivers that don't support legacy IRQs (iproc) need to undo this (Rob Herring) * pci/host-probe-refactor: PCI: Set bridge map_irq and swizzle_irq to default functions PCI: Move DT resource setup into devm_pci_alloc_host_bridge() PCI: rcar-gen2: Convert to use modern host bridge probe functions PCI: of: Reduce missing non-prefetchable memory region to a warning PCI: rcar: Use struct pci_host_bridge.windows list directly PCI: rcar: Use devm_pci_alloc_host_bridge() PCI: cadence: Remove private bus number and range storage PCI: cadence: Use bridge resources for outbound window setup PCI: Move setting pci_host_bridge.busnr out of host drivers PCI: rcar: Use pci_is_root_bus() to check if bus is root bus PCI: rockchip: Use pci_is_root_bus() to check if bus is root bus PCI: xilinx: Use pci_is_root_bus() to check if bus is root bus PCI: xilinx-nwl: Use pci_is_root_bus() to check if bus is root bus PCI: mobiveil: Use pci_is_root_bus() to check if bus is root bus PCI: designware: Use pci_is_root_bus() to check if bus is root bus PCI: aardvark: Use pci_is_root_bus() to check if bus is root bus PCI: Drop unnecessary zeroing of bridge fields PCI: Set default bridge parent device PCI: versatile: Drop flag PCI_ENABLE_PROC_DOMAINS PCI: controller: Remove duplicate error message PCI: controller: Convert to devm_platform_ioremap_resource() PCI: controller: Convert to devm_platform_ioremap_resource_byname() PCI: xilinx: Use pci_host_probe() to register host PCI: xilinx-nwl: Use pci_host_probe() to register host PCI: rockchip: Use pci_host_probe() to register host PCI: rcar: Use pci_host_probe() to register host PCI: iproc: Use pci_host_probe() to register host PCI: altera: Use pci_host_probe() to register host PCI: xgene: Use pci_host_probe() to register host PCI: versatile: Use pci_host_probe() to register host PCI: v3: Use pci_host_probe() to register host PCI: tegra: Use pci_host_probe() to register host PCI: mobiveil: Use pci_host_probe() to register host PCI: brcmstb: Use pci_host_probe() to register host PCI: host-common: Use struct pci_host_bridge.windows list directly PCI: mvebu: Use struct pci_host_bridge.windows list directly PCI: cadence: Use struct pci_host_bridge.windows list directly # Conflicts: # drivers/pci/controller/cadence/pcie-cadence-host.c
2020-08-05Merge branch 'pci/xilinx-cpm'Bjorn Helgaas
* pci/xilinx-cpm: PCI: xilinx-cpm: Add Versal CPM Root Port driver PCI: xilinx-cpm: Add YAML schemas for Versal CPM Root Port
2020-08-05Merge branch 'remotes/lorenzo/pci/vmd'Bjorn Helgaas
- Use Shadow MEMBAR registers for QEMU/KVM guests (Jon Derrick) * remotes/lorenzo/pci/vmd: PCI: vmd: Use Shadow MEMBAR registers for QEMU/KVM guests
2020-08-05Merge branch 'remotes/lorenzo/pci/tegra'Bjorn Helgaas
- Revert tegra RAW fixup that caused a regression (Nicolas Chauvet) - Remove PLL power supplies from tegra driver and DT binding (Thierry Reding) * remotes/lorenzo/pci/tegra: PCI: tegra: Remove PLL power supplies dt-bindings: pci: tegra: Remove PLL power supplies PCI: tegra: Revert tegra124 raw_violation_fixup
2020-08-05Merge branch 'remotes/lorenzo/pci/runtime-pm'Bjorn Helgaas
- Fix runtime power management imbalance for cadence, dra7xx, qcom, rcar (Dinghao Liu) * remotes/lorenzo/pci/runtime-pm: PCI: rcar: Fix runtime PM imbalance on error PCI: qcom: Fix runtime PM imbalance on error PCI: cadence: Fix runtime PM imbalance on error PCI: dwc: pci-dra7xx: Fix runtime PM imbalance on error
2020-08-05Merge branch 'remotes/lorenzo/pci/mvebu'Bjorn Helgaas
- Set up mvebu BAR 0 so MSI works even if bootloader doesn't do this (Shmuel Hazan) * remotes/lorenzo/pci/mvebu: PCI: mvebu: Setup BAR0 in order to fix MSI
2020-08-05Merge branch 'remotes/lorenzo/pci/loongson'Bjorn Helgaas
- Fix loongson class code quirk so it happens early enough (Tiezhu Yang) * remotes/lorenzo/pci/loongson: PCI: loongson: Use DECLARE_PCI_FIXUP_EARLY for bridge_class_quirk()
2020-08-05Merge branch 'remotes/lorenzo/pci/hv'Bjorn Helgaas
- Fix hv timing issue that causes kdump failures (Wei Hu) - Make some hv functions static (Wei Yongjun) * remotes/lorenzo/pci/hv: PCI: hv: Make some functions static PCI: hv: Fix a timing issue which causes kdump to fail occasionally
2020-08-05Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas
- Add qcom ipq806x support (Ansuel Smith) - Support max-link-speed DT property for qcom (Sham Muthayyan) - Use PCI core #defines instead of adding qcom-specific ones (Ansuel Smith) - Convert to devm_platform_ioremap_resource_byname() instead of open-coding platform_get_resource_byname() and devm_ioremap_resource() for dra7xx, keystone, artpec6, designware-plat, histb, intel-gw, kirin, qcom, uniphier (Dejin Zheng) - Remove non-ECAM HiSilicon hip05/hip06 driver (Rob Herring) * remotes/lorenzo/pci/dwc: PCI: dwc: hisi: Remove non-ECAM HiSilicon hip05/hip06 driver PCI: dwc: Convert to devm_platform_ioremap_resource_byname() PCI: qcom: Replace define with standard value PCI: qcom: Support pci speed set for ipq806x dt-bindings: PCI: qcom: Add ipq8064 rev 2 variant PCI: qcom: Add ipq8064 rev2 variant PCI: qcom: Add support for tx term offset for rev 2.1.0 PCI: qcom: Define some PARF params needed for ipq8064 SoC PCI: qcom: Use bulk clk api and assert on error dt-bindings: PCI: qcom: Add ext reset PCI: qcom: Add missing reset for ipq806x PCI: qcom: Change duplicate PCI reset to phy reset dt-bindings: PCI: qcom: Add missing clks PCI: qcom: Add missing ipq806x clocks in PCIe driver
2020-08-05Merge branch 'remotes/lorenzo/pci/cadence'Bjorn Helgaas
- Convert cadence to use standard "dma-ranges" DT property instead of its own "cdns,no-bar-match-nbits" (Kishon Vijay Abraham I) - Fix pm_runtime_put_sync() issues in cadence error paths (Kishon Vijay Abraham I) - Add PTR_ALIGN_DOWN macro (Kishon Vijay Abraham I) - Convert cadence r/w accessors to only 32-bit accesses (Kishon Vijay Abraham I) - Add cadence support to start Link and check Link status (Kishon Vijay Abraham I) - Allow custom PCI ops for cadence-based drivers (Kishon Vijay Abraham I) - Remove "mem" from cadence reg binding since it's not memory and it overlaps the PCIe config and memory region (Kishon Vijay Abraham I) - Add cadence ->cpu_addr_fixup() for platforms that require absolute addresses in the ATU, not just offsets (Kishon Vijay Abraham I) - Update cadence Vendor IDs using local management registers, not architected config space (Kishon Vijay Abraham I) - Add cadence endpoint driver MSI-X support (Kishon Vijay Abraham I) - Add bindings and driver for TI J721E SoC, supporting both host and endpoint mode (Kishon Vijay Abraham I) * remotes/lorenzo/pci/cadence: MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe misc: pci_endpoint_test: Add J721E in pci_device_id table PCI: j721e: Add TI J721E PCIe driver dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC PCI: cadence: Add MSI-X support to Endpoint driver PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register PCI: cadence: Add new *ops* for CPU addr fixup dt-bindings: PCI: cadence: Remove "mem" from reg binding PCI: cadence: Allow pci_host_bridge to have custom pci_ops PCI: cadence: Add support to start link and verify link status PCI: cadence: Convert all r/w accessors to perform only 32-bit accesses linux/kernel.h: Add PTR_ALIGN_DOWN macro PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path PCI: cadence: Use "dma-ranges" instead of "cdns,no-bar-match-nbits" property
2020-08-05Merge branch 'remotes/lorenzo/pci/aardvark'Bjorn Helgaas
- Indicate error in 'val' when config read fails (Pali Rohár) - Don't touch PCIe registers if no card connected (Pali Rohár) * remotes/lorenzo/pci/aardvark: PCI: aardvark: Don't touch PCIe registers if no card connected PCI: aardvark: Indicate error in 'val' when config read fails
2020-08-05Merge branch 'pci/switchtec'Bjorn Helgaas
- Add __iomem and __user tags to switchtec driver (Logan Gunthorpe) * pci/switchtec: PCI: switchtec: Add missing __iomem tag to fix sparse warnings PCI: switchtec: Add missing __iomem and __user tags to fix sparse warnings
2020-08-05Merge branch 'pci/virtualization'Bjorn Helgaas
- Remove redundant variable init in xen (Colin Ian King) - Add pci_pri_supported() to check device or associated PF for PRI support (Ashok Raj) - Mark AMD Navi10 GPU rev 0x00 ATS as broken (Kai-Heng Feng) - Release IVRS table in AMD ACS quirk (Hanjun Guo) * pci/virtualization: PCI: Release IVRS table in AMD ACS quirk PCI: Mark AMD Navi10 GPU rev 0x00 ATS as broken PCI/ATS: Add pci_pri_supported() to check device or associated PF xen: Remove redundant initialization of irq
2020-08-05Merge branch 'pci/peer-to-peer'Bjorn Helgaas
- Allow P2PDMA on AMD Zen and newer CPUs (Logan Gunthorpe) * pci/peer-to-peer: PCI/P2PDMA: Allow P2PDMA on AMD Zen and newer CPUs
2020-08-05Merge branch 'pci/msi'Bjorn Helgaas
- Forward MSI-X error code in pci_alloc_irq_vectors_affinity() (Piotr Stankiewicz) * pci/msi: PCI/MSI: Forward MSI-X error code in pci_alloc_irq_vectors_affinity()
2020-08-05Merge branch 'pci/misc'Bjorn Helgaas
- Convert PCIe capability PCIBIOS errors to errno (Bolarinwa Olayemi Saheed) - Align PCIe capability and PCI accessor return values (Bolarinwa Olayemi Saheed) - Replace http:// links with https:// (Alexander A. Klimov) - Replace lkml.org, spinics, gmane with lore.kernel.org (Bjorn Helgaas) - Update panic message to mention kzalloc(), not kmalloc() (Liao Pingfang) - Move PCI_VENDOR_ID_REDHAT definition to pci_ids.h (Huacai Chen) - Remove unused pci_lost_interrupt() (Heiner Kallweit) * pci/misc: PCI: Remove unused pci_lost_interrupt() PCI: Move PCI_VENDOR_ID_REDHAT definition to pci_ids.h PCI: Fix error in panic message PCI: Replace lkml.org, spinics, gmane with lore.kernel.org PCI: Replace http:// links with https:// PCI: Align PCIe capability and PCI accessor return values PCI: Convert PCIe capability PCIBIOS errors to errno
2020-08-05Merge branch 'pci/hotplug'Bjorn Helgaas
- Fix pci_create_slot() reference count leak in failure path (Qiushi Wu) - Make rpadlpar functions static (Wei Yongjun) * pci/hotplug: PCI: rpadlpar: Make functions static PCI: Fix pci_create_slot() reference count leak
2020-08-05Merge branch 'pci/error'Bjorn Helgaas
- Use pci_channel_state_t instead of enum pci_channel_state (Luc Van Oostenryck) - Simplify __aer_print_error() (Bjorn Helgaas) - Log AER correctable errors as warning, not error (Matt Jolly) - Rename pci_aer_clear_device_status() to pcie_clear_device_status() (Bjorn Helgaas) - Clear PCIe Device Status errors only if OS owns AER (Jonathan Cameron) * pci/error: PCI/ERR: Clear PCIe Device Status errors only if OS owns AER PCI/ERR: Rename pci_aer_clear_device_status() to pcie_clear_device_status() PCI/AER: Log correctable errors as warning, not error PCI/AER: Simplify __aer_print_error() PCI: Use 'pci_channel_state_t' instead of 'enum pci_channel_state'
2020-08-05Merge branch 'pci/enumeration'Bjorn Helgaas
- Fix pci_cfg_wait queue locking problem (Xiang Zheng, Bjorn Helgaas) - Keep device in system even if driver attach fails (Rajat Jain) - Cache ACS capability offset in device (Rajat Jain) - Treat "external-facing" devices themselves as internal, not external (Rajat Jain) - Announce device after early fixups (Tiezhu Yang) * pci/enumeration: PCI: Announce device after early fixups PCI: Treat "external-facing" devices themselves as internal PCI: Cache ACS capability offset in device PCI: Reorder pci_enable_acs() and dependencies PCI: Add device even if driver attach failed PCI: Fix pci_cfg_wait queue locking problem
2020-08-05PCI: Fix kerneldoc warningsKrzysztof Kozlowski
Fix kerneldoc warnings, e.g., $ make W=1 drivers/pci/ drivers/pci/ats.c:196: warning: Function parameter or member 'pdev' not described in 'pci_enable_pri' drivers/pci/ats.c:196: warning: Function parameter or member 'reqs' not described in 'pci_enable_pri' ... Link: https://lore.kernel.org/r/20200729201224.26799-2-krzk@kernel.org Link: https://lore.kernel.org/r/20200729201224.26799-3-krzk@kernel.org Link: https://lore.kernel.org/r/20200729201224.26799-4-krzk@kernel.org Link: https://lore.kernel.org/r/20200729201224.26799-5-krzk@kernel.org Link: https://lore.kernel.org/r/20200729201224.26799-6-krzk@kernel.org Link: https://lore.kernel.org/r/20200729201224.26799-7-krzk@kernel.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-08-05PCI: xilinx-cpm: Add Versal CPM Root Port driverBharat Kumar Gogada
Add support for Versal CPM as Root Port. The Versal ACAP devices include CCIX-PCIe Module (CPM). The integrated block for CPM along with the integrated bridge can function as PCIe Root Port. Bridge error and legacy interrupts in Versal CPM are handled using Versal CPM specific interrupt line. [bhelgaas: fold in kerneldoc fix from https://lore.kernel.org/linux-acpi/20200729201224.26799-7-krzk@kernel.org/] Link: https://lore.kernel.org/r/1592312214-9347-3-git-send-email-bharat.kumar.gogada@xilinx.com Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-08-04PCI: Set bridge map_irq and swizzle_irq to default functionsRob Herring
The majority of DT based host drivers use the default .map_irq() and .swizzle_irq() functions, so let's initialize the function pointers to the default and drop setting them in the host drivers. Drivers like iProc which don't support legacy interrupts need to set .map_irq() back to NULL. Link: https://lore.kernel.org/r/20200722022514.1283916-20-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com>
2020-08-04PCI: Move DT resource setup into devm_pci_alloc_host_bridge()Rob Herring
Now that pci_parse_request_of_pci_ranges() callers just setup pci_host_bridge.windows and dma_ranges directly and don't need the bus range returned, we can just initialize them when allocating the pci_host_bridge struct. With this, pci_parse_request_of_pci_ranges() becomes a static function. Link: https://lore.kernel.org/r/20200722022514.1283916-19-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com>
2020-08-04PCI: rcar-gen2: Convert to use modern host bridge probe functionsRob Herring
The rcar-gen2 host driver still uses the old Arm PCI setup function pci_common_init_dev(). Let's update it to use the modern devm_pci_alloc_host_bridge(), pci_parse_request_of_pci_ranges() and pci_host_probe() functions. Link: https://lore.kernel.org/r/20200722022514.1283916-18-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-renesas-soc@vger.kernel.org
2020-08-03PCI: j721e: Add TI J721E PCIe driverKishon Vijay Abraham I
Add support for PCIe controller in J721E SoC. The controller uses the Cadence PCIe core programmed by pcie-cadence*.c. The PCIe controller will work in both host mode and device mode. Some of the features of the controller are: *) Supports both RC mode and EP mode *) Supports MSI and MSI-X support *) Supports upto GEN3 speed mode *) Supports SR-IOV capability *) Ability to route all transactions via SMMU (support will be added in a later patch). Link: https://lore.kernel.org/r/20200722110317.4744-14-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2020-07-31PCI: switchtec: Add missing __iomem tag to fix sparse warningsLogan Gunthorpe
Fix a missing __iomem tag in the init_pfn() function. This fixes a sparse warning of the form: $ make C=2 drivers/pci/switch/ drivers/pci/switch/switchtec.c:... incorrect type assignment(different address spaces) Fixes: 080b47def5e5 ("MicroSemi Switchtec management interface driver") Link: https://lore.kernel.org/r/20200728192434.18993-2-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-07-31PCI: switchtec: Add missing __iomem and __user tags to fix sparse warningsLogan Gunthorpe
Fix a number of missing __iomem and __user tags in the ioctl functions of the switchtec driver. This fixes a number of sparse warnings of the form: $ make C=2 drivers/pci/switch/ drivers/pci/switch/switchtec.c:... incorrect type in ... (different address spaces) Fixes: 52eabba5bcdb ("switchtec: Add IOCTLs to the Switchtec driver") Link: https://lore.kernel.org/r/20200728192434.18993-1-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-07-30PCI: rpadlpar: Make functions staticWei Yongjun
The sparse tool report build warnings as follows: drivers/pci/hotplug/rpadlpar_core.c:355:5: warning: symbol 'dlpar_remove_pci_slot' was not declared. Should it be static? drivers/pci/hotplug/rpadlpar_core.c:461:12: warning: symbol 'rpadlpar_io_init' was not declared. Should it be static? drivers/pci/hotplug/rpadlpar_core.c:473:6: warning: symbol 'rpadlpar_io_exit' was not declared. Should it be static? Those functions are not used outside of this file, so mark them static. Also mark rpadlpar_io_exit() as __exit. Link: https://lore.kernel.org/r/20200721151735.41181-1-weiyongjun1@huawei.com Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-07-30PCI/P2PDMA: Allow P2PDMA on AMD Zen and newer CPUsLogan Gunthorpe
Allow P2PDMA if the CPU vendor is AMD and family is 0x17 (Zen) or greater. [bhelgaas: commit log, simplify #if/#else/#endif] Link: https://lore.kernel.org/r/20200729231844.4653-1-logang@deltatee.com Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Huang Rui <ray.huang@amd.com>
2020-07-29PCI: Release IVRS table in AMD ACS quirkHanjun Guo
The acpi_get_table() should be coupled with acpi_put_table() if the mapped table is not used at runtime to release the table mapping. In pci_quirk_amd_sb_acs(), IVRS table is just used for checking AMD IOMMU is supported, not used at runtime, so put the table after using it. Fixes: 15b100dfd1c9 ("PCI: Claim ACS support for AMD southbridge devices") Link: https://lore.kernel.org/r/1595411068-15440-1-git-send-email-guohanjun@huawei.com Signed-off-by: Hanjun Guo <guohanjun@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-07-29PCI: Announce device after early fixupsTiezhu Yang
Announce the device, e.g., pci 0000:00:00.0: [8086:5910] type 00 class 0x060000 after running early fixups, so the log message reflects any device type or class code fixups. [bhelgaas: commit log] Link: https://lore.kernel.org/r/1595833615-8049-1-git-send-email-yangtiezhu@loongson.cn Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-07-29PCI: Mark AMD Navi10 GPU rev 0x00 ATS as brokenKai-Heng Feng
We are seeing AMD Radeon Pro W5700 doesn't work when IOMMU is enabled: iommu ivhd0: AMD-Vi: Event logged [IOTLB_INV_TIMEOUT device=63:00.0 address=0x42b5b01a0] iommu ivhd0: AMD-Vi: Event logged [IOTLB_INV_TIMEOUT device=63:00.0 address=0x42b5b01c0] The error also makes graphics driver fail to probe the device. It appears to be the same issue as commit 5e89cd303e3a ("PCI: Mark AMD Navi14 GPU rev 0xc5 ATS as broken") addresses, and indeed the same ATS quirk can workaround the issue. See-also: 5e89cd303e3a ("PCI: Mark AMD Navi14 GPU rev 0xc5 ATS as broken") See-also: d28ca864c493 ("PCI: Mark AMD Stoney Radeon R7 GPU ATS as broken") See-also: 9b44b0b09dec ("PCI: Mark AMD Stoney GPU ATS as broken") Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=208725 Link: https://lore.kernel.org/r/20200728104554.28927-1-kai.heng.feng@canonical.com Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2020-07-29PCI: Remove unused pci_lost_interrupt()Heiner Kallweit
388c8c16abaf ("PCI: add routines for debugging and handling lost interrupts") added pci_lost_interrupt() that apparently never has had a single user. Remove it. Link: https://lore.kernel.org/r/e328d059-3068-6a40-28df-f81f616d15a0@gmail.com Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2020-07-28PCI: cadence: Add MSI-X support to Endpoint driverAlan Douglas
Implement ->set_msix() and ->get_msix() callback functions in order to configure MSIX capability in the PCIe endpoint controller. Add cdns_pcie_ep_send_msix_irq() to send MSIX interrupts to Host. cdns_pcie_ep_send_msix_irq() gets the MSIX table address (virtual address) from "struct cdns_pcie_epf" that gets initialized in ->set_bar() call back function. [kishon@ti.com: Re-implement MSIX support in accordance with the re-designed core MSI-X interfaces] Link: https://lore.kernel.org/r/20200722110317.4744-11-kishon@ti.com Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2020-07-28PCI: hv: Make some functions staticWei Yongjun
sparse report build warning as follows: drivers/pci/controller/pci-hyperv.c:941:5: warning: symbol 'hv_read_config_block' was not declared. Should it be static? drivers/pci/controller/pci-hyperv.c:1021:5: warning: symbol 'hv_write_config_block' was not declared. Should it be static? drivers/pci/controller/pci-hyperv.c:1090:5: warning: symbol 'hv_register_block_invalidate' was not declared. Should it be static? Those functions are not used outside of this file, so mark them static. Link: https://lore.kernel.org/r/20200706135234.80758-1-weiyongjun1@huawei.com Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2020-07-28PCI: tegra: Remove PLL power suppliesThierry Reding
The Tegra PCI controller driver doesn't need to control the PLL power supplies directly, but rather uses the pads provided by the XUSB pad controller, which in turn is responsible for supplying power to the PLLs. Link: https://lore.kernel.org/r/20200623145528.1658337-2-thierry.reding@gmail.com Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-07-27PCI: dwc: hisi: Remove non-ECAM HiSilicon hip05/hip06 driverRob Herring
The HiSilicon non-ECAM PCIe has been broken since March 2016 commit 7e57fd1444bf ("PCI: designware: Move Root Complex setup code to dw_pcie_setup_rc()"). The reason is this commit moved the iATU setup code from dw_pcie_host_init() to dw_pcie_setup_rc(), but the hisi driver never calls dw_pcie_setup_rc(). The result is the PCI memory space is never configured and the driver can't work. It's also clear it has an iATU as the config space accesses use it. There's also no dts file using either "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie". Link: https://lore.kernel.org/r/20200724224204.3249055-1-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Zhou Wang <wangzhou1@hisilicon.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com>
2020-07-27PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID registerKishon Vijay Abraham I
Commit 1b79c5284439 ("PCI: cadence: Add host driver for Cadence PCIe controller") in order to update Vendor ID, directly wrote to PCI_VENDOR_ID register. However PCI_VENDOR_ID in root port configuration space is read-only register and writing to it will have no effect. Use local management register to configure Vendor ID and Subsystem Vendor ID. Link: https://lore.kernel.org/r/20200722110317.4744-10-kishon@ti.com Fixes: 1b79c5284439 ("PCI: cadence: Add host driver for Cadence PCIe controller") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-07-27PCI: cadence: Add new *ops* for CPU addr fixupKishon Vijay Abraham I
Cadence driver uses "mem" memory resource to obtain the offset of configuration space address region, memory space address region and message space address region. The obtained offset is used to program the Address Translation Unit (ATU). However certain platforms like TI's J721E SoC require the absolute address to be programmed in the ATU and not just the offset. Add new *ops* for CPU addr fixup for the platform drivers to provide the correct address to be programmed in the ATU. Link: https://lore.kernel.org/r/20200722110317.4744-9-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2020-07-27PCI: cadence: Allow pci_host_bridge to have custom pci_opsKishon Vijay Abraham I
Certain platforms like TI's J721E allows only 32-bit configuration space access. In such cases pci_generic_config_read and pci_generic_config_write cannot be used. Add support in Cadence core to let pci_host_bridge have custom pci_ops. Link: https://lore.kernel.org/r/20200722110317.4744-7-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2020-07-27PCI: cadence: Add support to start link and verify link statusKishon Vijay Abraham I
Add cdns_pcie_ops to start link and verify link status. The registers to start link and to check link status is in Platform specific PCIe wrapper. Add support for platform specific drivers to add callback functions for the PCIe Cadence core to start link and verify link status. Link: https://lore.kernel.org/r/20200722110317.4744-6-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-07-27PCI: cadence: Convert all r/w accessors to perform only 32-bit accessesKishon Vijay Abraham I
Certain platforms like TI's J721E using Cadence PCIe IP can perform only 32-bit accesses for reading or writing to Cadence registers. Convert all read and write accesses to 32-bit in Cadence PCIe driver in preparation for adding PCIe support in TI's J721E SoC. Also add spin lock to disable interrupts while modifying PCI_STATUS register while raising legacy interrupt since PCI_STATUS is accessible by both remote RC and EP and time between read and write should be minimized. Link: https://lore.kernel.org/r/20200722110317.4744-5-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2020-07-27PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error pathKishon Vijay Abraham I
commit bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library") while refactoring the Cadence PCIe driver to be used as library, removed pm_runtime_get_sync() from cdns_pcie_ep_setup() and cdns_pcie_host_setup() but missed to remove the corresponding pm_runtime_put_sync() in the error path. Fix it here. Link: https://lore.kernel.org/r/20200722110317.4744-3-kishon@ti.com Fixes: bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library") Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-07-27PCI: cadence: Use "dma-ranges" instead of "cdns,no-bar-match-nbits" propertyKishon Vijay Abraham I
Cadence PCIe core driver (host mode) uses "cdns,no-bar-match-nbits" property to configure the number of bits passed through from PCIe address to internal address in Inbound Address Translation register. This only used the NO MATCH BAR. However standard PCI dt-binding already defines "dma-ranges" to describe the address ranges accessible by PCIe controller. Add support in Cadence PCIe host driver to parse dma-ranges and configure the inbound regions for BAR0, BAR1 and NO MATCH BAR. Cadence IP specifies maximum size for BAR0 as 256GB, maximum size for BAR1 as 2 GB. This adds support to take the next biggest region in "dma-ranges" and find the smallest BAR that each of the regions fit in and if there is no BAR big enough to hold the region, split the region to see if it can be fitted using multiple BARs. "dma-ranges" of J721E will be dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; Since there is no BAR which can hold 2^48 size, NO_MATCH_BAR will be used here. Legacy device tree binding compatibility is maintained by retaining support for "cdns,no-bar-match-nbits". Link: https://lore.kernel.org/r/20200722110317.4744-2-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
2020-07-27PCI: hv: Fix a timing issue which causes kdump to fail occasionallyWei Hu
Kdump could fail sometime on Hyper-V guest because the retry in hv_pci_enter_d0() releases child device structures in hv_pci_bus_exit(). Although there is a second asynchronous device relations message sending from the host, if this message arrives to the guest after hv_send_resource_allocated() is called, the retry would fail. Fix the problem by moving retry to hv_pci_probe() and start the retry from hv_pci_query_relations() call. This will cause a device relations message to arrive to the guest synchronously; the guest would then be able to rebuild the child device structures before calling hv_send_resource_allocated(). Link: https://lore.kernel.org/r/20200727071731.18516-1-weh@microsoft.com Fixes: c81992e7f4aa ("PCI: hv: Retry PCI bus D0 entry on invalid device state") Signed-off-by: Wei Hu <weh@microsoft.com> [lorenzo.pieralisi@arm.com: fixed a comment and commit log] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Michael Kelley <mikelley@microsoft.com>
2020-07-24PCI/ATS: Add pci_pri_supported() to check device or associated PFAshok Raj
For SR-IOV, the PF PRI is shared between the PF and any associated VFs, and the PRI Capability is allowed for PFs but not for VFs. Searching for the PRI Capability on a VF always fails, even if its associated PF supports PRI. Add pci_pri_supported() to check whether device or its associated PF supports PRI. [bhelgaas: commit log, avoid "!!"] Fixes: b16d0cb9e2fc ("iommu/vt-d: Always enable PASID/PRI PCI capabilities before ATS") Link: https://lore.kernel.org/r/1595543849-19692-1-git-send-email-ashok.raj@intel.com Signed-off-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Acked-by: Joerg Roedel <jroedel@suse.de> Cc: stable@vger.kernel.org # v4.4+
2020-07-23PCI: of: Reduce missing non-prefetchable memory region to a warningRob Herring
The pci-rcar-gen2 controller requires only a prefetchable memory region, and the error prevents using pci_parse_request_of_pci_ranges() for it. Let's reduce this to just a warning message so this function can be used for pci-rcar-gen2. Link: https://lore.kernel.org/r/20200722022514.1283916-17-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
2020-07-23PCI: rcar: Use struct pci_host_bridge.windows list directlyRob Herring
There's no need to create a temporary resource list and then splice it to struct pci_host_bridge.windows list. Just use pci_host_bridge.windows directly. The necessary clean-up is already handled by the PCI core. Link: https://lore.kernel.org/r/20200722022514.1283916-16-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org
2020-07-23PCI: rcar: Use devm_pci_alloc_host_bridge()Rob Herring
Move to the resource managed devm_pci_alloc_host_bridge() and simplify the error path. Link: https://lore.kernel.org/r/20200722022514.1283916-15-robh@kernel.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-renesas-soc@vger.kernel.org
generated by cgit (git 2.34.1) at 2025-07-19 11:56:40 +0000