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2025-02-13phy: freescale: fsl-samsung-hdmi: Limit PLL lock detection clock divider to ↵Pei Xiao
valid range FIELD_PREP() checks that a value fits into the available bitfield, but the index div equals to 4,is out of range. which gcc complains about: In function ‘fsl_samsung_hdmi_phy_configure_pll_lock_det’, inlined from ‘fsl_samsung_hdmi_phy_configure’ at drivers/phy/freescale/phy-fsl-samsung-hdmi.c :470:2: ././include/linux/compiler_types.h:542:38: error: call to ‘__compiletime_assert_538’ declared with attribute error: FIELD_PREP: value too large for the field 542 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) | ^ ././include/linux/compiler_types.h:523:4: note: in definition of macro ‘__compiletime_assert’ 523 | prefix ## suffix(); | ^~~~~~ ././include/linux/compiler_types.h:542:2: note: in expansion of macro ‘_compiletime_assert’ 542 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) REG12_CK_DIV_MASK only two bit, limit div to range 0~3, so build error will fix. Fixes: d567679f2b6a ("phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation") Signed-off-by: Pei Xiao <xiaopei01@kylinos.cn> Changlog: Reviewed-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/tencent_6F503D43467AA99DD8CC59B8F645F0725B0A@qq.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: stih407-usb: Use syscon_regmap_lookup_by_phandle_argsKrzysztof Kozlowski
Use syscon_regmap_lookup_by_phandle_args() which is a wrapper over syscon_regmap_lookup_by_phandle() combined with getting the syscon argument. Except simpler code this annotates within one line that given phandle has arguments, so grepping for code would be easier. There is also no real benefit in printing errors on missing syscon argument, because this is done just too late: runtime check on static/build-time data. Dtschema and Devicetree bindings offer the static/build-time check for this already. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Link: https://lore.kernel.org/r/20250111185407.183855-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: exynos5-usbdrd: allow DWC3 runtime suspend with UDC bound (E850+)André Draszik
To make USB runtime suspend work when a UDC has been bound, the phy needs to inform the USBDRD controller (DWC3) that Vbus and bvalid are gone, so that it can in turn raise the respective gadget interrupt with event == DWC3_DEVICE_EVENT_DISCONNECT, which will cause the USB stack to clean up, allowing DWC3 to enter runtime suspend. On e850 and gs101 this isn't working, as the respective signals are not directly connected, and instead this driver uses override bits in the PHY IP to set those signals. It currently forcefully sets them to 'on', so the above mentioned interrupt will not be raised, preventing runtime suspend. To detect that state, update this driver to act on the TCPC's orientation signal - when orientation == NONE, Vbus is gone and we can clear the respective bits. Similarly, for other orientation values we re-enable them. This makes runtime suspend work on platforms with a TCPC (like Pixel6), while keeping compatibility with platforms without (e850-96). With runtime suspend working, USB-C cable orientation detection now also fully works on such platforms, and the link comes up as Superspeed as expected irrespective of the cable orientation and whether UDC / gadget are configured and active. Signed-off-by: André Draszik <andre.draszik@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-7-f5961268b149@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: exynos5-usbdrd: subscribe to orientation notifier if requiredAndré Draszik
gs101's SS phy needs to be configured differently based on the connector orientation, as the SS link can only be established if the mux is configured correctly. The code to handle programming of the mux is in place already, this commit now adds the missing pieces to subscribe to the Type-C orientation switch event. Note that for this all to work we rely on the USB controller re-initialising us. It should invoke our .exit() upon cable unplug, and during cable plug we'll receive the orientation event after which we expect our .init() to be called. Above reinitialisation happens if the DWC3 controller can enter runtime suspend automatically. For the DWC3 driver, this is an opt-in: echo auto > /sys/devices/.../11110000.usb/power/control Once done, things work as long as the UDC is not bound as otherwise it stays busy because it doesn't cancel / stop outstanding TRBs. For now we have to manually unbind the UDC in that case: echo "" > sys/kernel/config/usb_gadget/.../UDC Note that if the orientation-switch property is missing from the DT, the code will behave as before this commit (meaning for gs101 it will work in SS mode in one orientation only). Other platforms are not affected either way. Signed-off-by: André Draszik <andre.draszik@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-6-f5961268b149@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: exynos5-usbdrd: gs101: configure SS lanes based on orientationAndré Draszik
USB SS lanes need to be configured based on the connector orientation - at most two lanes will be in use for USB (and the remaining two for alternate modes like DP). For the USB link to come up in SS, the lane configuration registers have to be programmed accordingly. While we still need a way to be notified of the actual connector orientation and then reprogram the registers accordingly (at the moment the configuration happens just once during phy_init() and never again), we can prepare the code doing the configuration to take the orientation into account. Do so. Note: the mutex is needed to synchronize this with the upcoming connector orientation callback. Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-5-f5961268b149@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: exynos5-usbdrd: fix EDS distribution tuning (gs101)André Draszik
This code's intention is to configure lane0 and lane2 tunings, but for lane2 there is a typo and it ends up tuning something else. Fix the typo, as it doesn't appear to make sense to apply different tunings for lane0 vs lane2. The same typo appears to exist in the bootloader, hence we restore the original value in the typo'd registers as well. This can be removed once / if the bootloader is updated. Note that this is incorrect in the downstream driver as well - the values had been copied from there. Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Tested-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-4-f5961268b149@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-13phy: exynos5-usbdrd: convert to dev_err_probeAndré Draszik
dev_err_probe() exists to simplify code. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-3-f5961268b149@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10phy: Use (of|device)_property_present() for non-boolean propertiesRob Herring (Arm)
The use of (of|device)_property_read_bool() for non-boolean properties is deprecated in favor of (of|device)_property_present() when testing for property presence. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Link: https://lore.kernel.org/r/20241231163121.241543-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10phy: can-transceiver: Drop unnecessary "mux-states" property presence checkRob Herring (Arm)
It doesn't matter whether "mux-states" is not present or there is some other issue parsing it causing an error. Drop the presence check and rework the error handling to ignore anything other than deferred probe. Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250203185421.3383805-2-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10phy: qcom: qmp-pcie: Add X1P42100 Gen4x4 PHYKonrad Dybcio
Add a new, common configuration for Gen4x4 V6 PHYs without an init sequence. The bootloader configures the hardware once and the OS retains that configuration by using the NOCSR reset line (which doesn't drop register state on assert) in place of the "full reset" one. Use this new configuration for X1P42100's Gen4x4 PHY. Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz> Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250203-topic-x1p4_dts-v2-3-72cd4cdc767b@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10phy: phy-rockchip-samsung-hdptx: Don't use dt aliases to determine phy-idHeiko Stuebner
The phy needs to know its identity in the system (phy0 or phy1 on rk3588) for some actions and the driver currently contains code abusing of_alias for that. Devicetree aliases are always optional and should not be used for core device functionality, so instead keep a list of phys on a soc in the of_device_data and find the phy-id by comparing against the mapped register-base. Fixes: c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock provider support") Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20241206103401.1780416-3-heiko@sntech.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10phy: phy-rockchip-samsung-hdptx: annotate regmap register-callbackHeiko Stuebner
The variant of the driver in the vendor-tree contained those handy comments in the regmap register callback. Having the different ranges describe what they are looks helpful. Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20241206103401.1780416-2-heiko@sntech.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10phy: exynos5-usbdrd: fix MPLL_MULTIPLIER and SSC_REFCLKSEL masks in refclkKaustabh Chakraborty
In exynos5_usbdrd_{pipe3,utmi}_set_refclk(), the masks PHYCLKRST_MPLL_MULTIPLIER_MASK and PHYCLKRST_SSC_REFCLKSEL_MASK are not inverted when applied to the register values. Fix it. Cc: stable@vger.kernel.org Fixes: 59025887fb08 ("phy: Add new Exynos5 USB 3.0 PHY driver") Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Anand Moon <linux.amoon@gmail.com> Link: https://lore.kernel.org/r/20250209-exynos5-usbdrd-masks-v1-1-4f7f83f323d7@disroot.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-10phy: stm32: Fix constant-value overflow assertionChristian Bruel
Rework the workaround as the lookup tables always fits into the bitfield, and the default values are defined by the hardware and cannot be 0: Guard against false positive with a WARN_ON check to make the compiler happy: The offset range is pre-checked against the sorted imp_lookup_table values and overflow should not happen and would be caught by a warning and return in error. Also guard against a true positive found during the max_vswing lookup, as a max vswing value can be 802000 or 803000 microvolt depending on the current impedance. Therefore set the default impedence index. Fixes: 2de679ecd724 ("phy: stm32: work around constant-value overflow assertion") Signed-off-by: Christian Bruel <christian.bruel@foss.st.com> Link: https://lore.kernel.org/r/20250210103515.2598377-1-christian.bruel@foss.st.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-04phy: rockchip: naneng-combphy: compatible reset with old DTChukun Pan
The device tree of RK3568 did not specify reset-names before. So add fallback to old behaviour to be compatible with old DT. Fixes: fbcbffbac994 ("phy: rockchip: naneng-combphy: fix phy reset") Cc: Jianfeng Liu <liujianfeng1994@gmail.com> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20250106100001.1344418-2-amadeus@jmu.edu.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-02-04phy: rockchip: fix Kconfig dependency moreArnd Bergmann
A previous patch ensured that USB Type C connector support is enabled, but it is still possible to build the phy driver without enabling CONFIG_USB (host support) or CONFIG_USB_GADGET (device support), and in that case the common helper functions are unavailable: aarch64-linux-ld: drivers/phy/rockchip/phy-rockchip-usbdp.o: in function `rk_udphy_probe': phy-rockchip-usbdp.c:(.text+0xe74): undefined reference to `usb_get_maximum_speed' Select CONFIG_USB_COMMON directly here, like we do in some other phy drivers, to make sure this is available even when actual USB support is disabled or in a loadable module that cannot be reached from a built-in phy driver. Fixes: 9c79b779643e ("phy: rockchip: fix CONFIG_TYPEC dependency") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250122065249.1390081-1-arnd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2025-01-29Merge tag 'phy-for-6.14' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy Pull phy updates from Vinod Koul: "Lots of Qualcomm and Rockchip device support. New Support: - Qualcomm SAR2130P qmp usb, SAR2130P qmp pcie, QCS615 qusb2 and PCIe, IPQ5424 qmp pcie, IPQ5424 QUSB2 and USB3 PHY - Rockchip rk3576 combo phy support Updates: - Drop Shengyang for JH7110 maintainer - Freescale hdmi register calculation optimization - Rockchip pcie phy mutex and regmap updates" * tag 'phy-for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (37 commits) dt-bindings: phy: qcom,qmp-pcie: document the SM8350 two lanes PCIe PHY phy: rockchip: phy-rockchip-typec: Fix Copyright description dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the IPQ5424 QMP PCIe PHYs phy: qcom-qusb2: Add support for QCS615 dt-bindings: usb: qcom,dwc3: Add QCS615 to USB DWC3 bindings phy: core: Simplify API of_phy_simple_xlate() implementation phy: sun4i-usb: Remove unused of_gpio.h phy: HiSilicon: Don't use "proxy" headers phy: samsung-ufs: switch back to syscon_regmap_lookup_by_phandle() phy: qualcomm: qmp-pcie: add support for SAR2130P phy: qualcomm: qmp-pcie: define several new registers phy: qualcomm: qmp-pcie: split PCS_LANE1 region phy: qualcomm: qmp-combo: add support for SAR2130P dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SAR2130P compatible dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Add SAR2130P compatible phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation phy: freescale: fsl-samsung-hdmi: Stop searching when exact match is found phy: freescale: fsl-samsung-hdmi: Expand Integer divider range phy: rockchip-naneng-combo: add rk3576 support dt-bindings: phy: rockchip: add rk3576 compatible ...
2025-01-15mediatek: stop messing with ->d_inameAl Viro
use debgufs_{create_file,get}_aux_num() instead. Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Link: https://lore.kernel.org/r/20250112080705.141166-11-viro@zeniv.linux.org.uk Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-12-25phy: rockchip: phy-rockchip-typec: Fix Copyright descriptionAndy Yan
The company name has update to Rockchip Electronics Co., Ltd. since 2021. And change Co.Ltd to Co., Ltd. to fix mail server warning: DBL_SPAM(6.50)[co.ltd:url]; Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241216100739.3726293-1-andyshrk@163.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24phy: mediatek: phy-mtk-hdmi: add regulator dependencyArnd Bergmann
The driver no longer builds when regulator support is unavailable: arm-linux-gnueabi-ld: drivers/phy/mediatek/phy-mtk-hdmi.o: in function `mtk_hdmi_phy_register_regulators': phy-mtk-hdmi.c:(.text.unlikely+0x3e): undefined reference to `devm_regulator_register' arm-linux-gnueabi-ld: drivers/phy/mediatek/phy-mtk-hdmi-mt8195.o: in function `mtk_hdmi_phy_pwr5v_is_enabled': phy-mtk-hdmi-mt8195.c:(.text+0x326): undefined reference to `rdev_get_drvdata' arm-linux-gnueabi-ld: drivers/phy/mediatek/phy-mtk-hdmi-mt8195.o: in function `mtk_hdmi_phy_pwr5v_disable': phy-mtk-hdmi-mt8195.c:(.text+0x346): undefined reference to `rdev_get_drvdata' arm-linux-gnueabi-ld: drivers/phy/mediatek/phy-mtk-hdmi-mt8195.o: in function `mtk_hdmi_phy_pwr5v_enable': Fixes: 49393b2da1cd ("phy: mediatek: phy-mtk-hdmi: Register PHY provided regulator") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241213083056.2596499-1-arnd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24phy: freescale: fsl-samsung-hdmi: Fix 64-by-32 division cocci warningsAdam Ford
The Kernel test robot returns the following warning: do_div() does a 64-by-32 division, please consider using div64_ul instead. To prevent the 64-by-32 divsion, consolidate both the multiplication and the do_div into one line which explicitly uses u64 sizes. Fixes: 1951dbb41d1d ("phy: freescale: fsl-samsung-hdmi: Support dynamic integer") Signed-off-by: Adam Ford <aford173@gmail.com> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202412091243.fSObwwPi-lkp@intel.com/ Link: https://lore.kernel.org/r/20241215220555.99113-1-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24phy: qcom-qusb2: Add support for QCS615Krishna Kurapati
Add init sequence and phy configuration for QCS615. Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224084621.4139021-3-krishna.kurapati@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24phy: core: Simplify API of_phy_simple_xlate() implementationZijun Hu
Simplify of_phy_simple_xlate() implementation by API class_find_device_by_of_node(). Also correct comments to mark its parameter @dev as unused instead of @args in passing. Signed-off-by: Zijun Hu <quic_zijuhu@quicinc.com> Cc: Simon Horman <horms@kernel.org> Link: https://lore.kernel.org/r/20241213-phy_core_fix-v6-6-40ae28f5015a@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24phy: core: Fix an OF node refcount leakage in of_phy_provider_lookup()Zijun Hu
For macro for_each_child_of_node(parent, child), refcount of @child has been increased before entering its loop body, so normally needs to call of_node_put(@child) before returning from the loop body to avoid refcount leakage. of_phy_provider_lookup() has such usage but does not call of_node_put() before returning, so cause leakage of the OF node refcount. Fix by simply calling of_node_put() before returning from the loop body. The APIs affected by this issue are shown below since they indirectly invoke problematic of_phy_provider_lookup(). phy_get() of_phy_get() devm_phy_get() devm_of_phy_get() devm_of_phy_get_by_index() Fixes: 2a4c37016ca9 ("phy: core: Fix of_phy_provider_lookup to return PHY provider for sub node") Cc: stable@vger.kernel.org Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Zijun Hu <quic_zijuhu@quicinc.com> Link: https://lore.kernel.org/r/20241213-phy_core_fix-v6-5-40ae28f5015a@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24phy: core: Fix an OF node refcount leakage in _of_phy_get()Zijun Hu
_of_phy_get() will directly return when suffers of_device_is_compatible() error, but it forgets to decrease refcount of OF node @args.np before error return, the refcount was increased by previous of_parse_phandle_with_args() so causes the OF node's refcount leakage. Fix by decreasing the refcount via of_node_put() before the error return. Fixes: b7563e2796f8 ("phy: work around 'phys' references to usb-nop-xceiv devices") Cc: stable@vger.kernel.org Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Zijun Hu <quic_zijuhu@quicinc.com> Link: https://lore.kernel.org/r/20241213-phy_core_fix-v6-4-40ae28f5015a@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24phy: core: Fix that API devm_phy_destroy() fails to destroy the phyZijun Hu
For devm_phy_destroy(), its comment says it needs to invoke phy_destroy() to destroy the phy, but it will not actually invoke the function since devres_destroy() does not call devm_phy_consume(), and the missing phy_destroy() call will cause that the phy fails to be destroyed. Fortunately, the faulty API has not been used by current kernel tree. Fix by using devres_release() instead of devres_destroy() within the API. Fixes: ff764963479a ("drivers: phy: add generic PHY framework") Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Zijun Hu <quic_zijuhu@quicinc.com> Link: https://lore.kernel.org/r/20241213-phy_core_fix-v6-3-40ae28f5015a@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24phy: core: Fix that API devm_of_phy_provider_unregister() fails to ↵Zijun Hu
unregister the phy provider For devm_of_phy_provider_unregister(), its comment says it needs to invoke of_phy_provider_unregister() to unregister the phy provider, but it will not actually invoke the function since devres_destroy() does not call devm_phy_provider_release(), and the missing of_phy_provider_unregister() call will cause: - The phy provider fails to be unregistered. - Leak both memory and the OF node refcount. Fortunately, the faulty API has not been used by current kernel tree. Fix by using devres_release() instead of devres_destroy() within the API. Fixes: ff764963479a ("drivers: phy: add generic PHY framework") Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Zijun Hu <quic_zijuhu@quicinc.com> Link: https://lore.kernel.org/stable/20241213-phy_core_fix-v6-2-40ae28f5015a%40quicinc.com Link: https://lore.kernel.org/r/20241213-phy_core_fix-v6-2-40ae28f5015a@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24phy: core: Fix that API devm_phy_put() fails to release the phyZijun Hu
For devm_phy_put(), its comment says it needs to invoke phy_put() to release the phy, but it will not actually invoke the function since devres_destroy() does not call devm_phy_release(), and the missing phy_put() call will cause: - The phy fails to be released. - devm_phy_put() can not fully undo what API devm_phy_get() does. - Leak refcount of both the module and device for below typical usage: devm_phy_get(); // or its variant ... err = do_something(); if (err) goto err_out; ... err_out: devm_phy_put(); // leak refcount here The file(s) affected by this issue are shown below since they have such typical usage. drivers/pci/controller/cadence/pcie-cadence.c drivers/net/ethernet/ti/am65-cpsw-nuss.c Fix by using devres_release() instead of devres_destroy() within the API. Fixes: ff764963479a ("drivers: phy: add generic PHY framework") Cc: stable@vger.kernel.org Cc: Lorenzo Pieralisi <lpieralisi@kernel.org> Cc: Krzysztof Wilczyński <kw@linux.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: David S. Miller <davem@davemloft.net> Cc: Eric Dumazet <edumazet@google.com> Cc: Jakub Kicinski <kuba@kernel.org> Cc: Paolo Abeni <pabeni@redhat.com> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Zijun Hu <quic_zijuhu@quicinc.com> Link: https://lore.kernel.org/r/20241213-phy_core_fix-v6-1-40ae28f5015a@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08phy: rockchip: samsung-hdptx: Set drvdata before enabling runtime PMCristian Ciocaltea
In some cases, rk_hdptx_phy_runtime_resume() may be invoked before platform_set_drvdata() is executed in ->probe(), leading to a NULL pointer dereference when using the return of dev_get_drvdata(). Ensure platform_set_drvdata() is called before devm_pm_runtime_enable(). Reported-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20241023-phy-sam-hdptx-rpm-fix-v1-1-87f4c994e346@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08phy: sun4i-usb: Remove unused of_gpio.hAndy Shevchenko
of_gpio.h is deprecated and subject to remove. The drivers in question don't use it, simply remove the unused header. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Link: https://lore.kernel.org/r/20241031104631.2454581-1-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08phy: HiSilicon: Don't use "proxy" headersAndy Shevchenko
Update header inclusions to follow IWYU (Include What You Use) principle. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20241031104401.2454179-1-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08phy: samsung-ufs: switch back to syscon_regmap_lookup_by_phandle()Peter Griffin
Now exynos-pmu can register its custom regmap for gs101 via of_syscon_register_regmap() we can switch back to the standard syscon_regmap_lookup_by_phandle() api for obtaining the regmap. Additionally add a Kconfig dependency for MFD_SYSCON. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20241029192107.2344279-1-peter.griffin@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08phy: qualcomm: qmp-pcie: add support for SAR2130PDmitry Baryshkov
Add PCIe QMP PHY configuration for the Qualcomm SAR2130P platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-6-d883acf170f7@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08phy: qualcomm: qmp-pcie: define several new registersDmitry Baryshkov
Define several registers to be used by PCIe QMP PHYs on v6 platforms. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-5-d883acf170f7@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08phy: qualcomm: qmp-pcie: split PCS_LANE1 regionDmitry Baryshkov
The PCS_LANE1 region isn't a part of the PCS_PCIE region. It was handled this way as it simplified handled of devices with the old bindings. Nowadays it can be handled as is, without hacks. Split the PCS_LANE1 region from the PCS_PCIE / PCS_MISC region space. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-4-d883acf170f7@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08phy: qualcomm: qmp-combo: add support for SAR2130PDmitry Baryshkov
Extend the USB+DP combo QMP PHY driver to support the SAR2130P platform. It mosly follows the SM8550 QMP PHY, but the QSERDES programming differs, most likely because of the parent clock rate differences. NOTE: The DP part wasn't yet tested, but it is not possible to support just the USB part of the PHY. DP part might require additional fixes later. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241021-sar2130p-phys-v2-3-d883acf170f7@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculationAdam Ford
Currently, the calcuation for fld_tg_code is based on a lookup table, but there are gaps in the lookup table, and frequencies in these gaps may not properly use the correct divider. Based on the description of FLD_CK_DIV, the internal PLL frequency should be less than 50 MHz, so directly calcuate the value of FLD_CK_DIV from pixclk. This allow for proper calcuation of any pixel clock and eliminates a few gaps in the LUT. Since the value of the int_pllclk is in Hz, do the fixed-point math in Hz to achieve a more accurate value and reduces the complexity of the caluation to 24MHz * (256 / int_pllclk). Fixes: 6ad082bee902 ("phy: freescale: add Samsung HDMI PHY") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Link: https://lore.kernel.org/r/20241026132014.73050-3-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08phy: freescale: fsl-samsung-hdmi: Stop searching when exact match is foundAdam Ford
There are a series of for-loops which check various values of P and S for the integer divder PLL. The for loops search all entries and use the one closest to the nominal, but it continues to searches through all for loops even after the nominal is achieved. Ending when the nominal value is found stops wasting time, since it will not find a better value than a deviation of 0 Hz. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Link: https://lore.kernel.org/r/20241026132014.73050-2-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08phy: freescale: fsl-samsung-hdmi: Expand Integer divider rangeAdam Ford
The Integer divder uses values of P,M, and S to determine the PLL rate. Currently, the range of M was set based on a series of table entries where the range was limited. Since the ref manual shows it is 8-bit wide, expand the range to be up to 255. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Link: https://lore.kernel.org/r/20241026132014.73050-1-aford173@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-08phy: rockchip-naneng-combo: add rk3576 supportKever Yang
Rockchip RK3576 integrates two naneng-combo PHY, PHY0 is used for PCIE and SATA, PHY1 is used for PCIE, SATA and USB3. This adds device specific data support. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: William Wu <william.wu@rock-chips.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Test-by: Kever Yang <kever.yang@rock-chips.com> Link: https://lore.kernel.org/r/20241106021357.19782-2-frawang.cn@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04phy: stm32: work around constant-value overflow assertionArnd Bergmann
FIELD_PREP() checks that a constant fits into the available bitfield, but if one of the two lookup tables in stm32_impedance_tune() does not find a matching entry, the index is out of range, which gcc correctly complains about: In file included from <command-line>: In function 'stm32_impedance_tune', inlined from 'stm32_combophy_pll_init' at drivers/phy/st/phy-stm32-combophy.c:247:9: include/linux/compiler_types.h:517:38: error: call to '__compiletime_assert_447' declared with attribute error: FIELD_PREP: value too large for the field 517 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) | ^ include/linux/bitfield.h:68:3: note: in expansion of macro 'BUILD_BUG_ON_MSG' 68 | BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \ 115 | __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \ | ^~~~~~~~~~~~~~~~ drivers/phy/st/phy-stm32-combophy.c:162:8: note: in expansion of macro 'FIELD_PREP' 162 | FIELD_PREP(STM32MP25_PCIEPRG_IMPCTRL_VSWING, vswing_of)); | ^~~~~~~~~~ Rework this so the field value gets set inside of the loop and otherwise set to zero. Fixes: 47e1bb6b4ba0 ("phy: stm32: Add support for STM32MP25 COMBOPHY.") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20241111103712.3520611-1-arnd@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04phy: qcom-qmp: Fix register name in RX Lane config of SC8280XPKrishna Kurapati
In RX Lane configuration sequence of SC8280XP, the register V5_RX_UCDR_FO_GAIN is incorrectly spelled as RX_UCDR_SO_GAIN and hence the programming sequence is wrong. Fix the register sequence accordingly to avoid any compliance failures. This has been tested on SA8775P by checking device mode enumeration in SuperSpeed. Cc: stable@vger.kernel.org Fixes: c0c7769cdae2 ("phy: qcom-qmp: Add SC8280XP USB3 UNI phy") Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20241112092831.4110942-1-quic_kriskura@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04phy: qcom: qmp: Enable IPQ5424 supportVaradarajan Narayanan
Enable QMP USB3 phy support for IPQ5424 SoC. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20241118052839.382431-5-quic_varada@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04phy: qcom-qusb2: add QUSB2 support for IPQ5424Varadarajan Narayanan
Add the phy init sequence for the Super Speed ports found on IPQ5424. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20241118052839.382431-3-quic_varada@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04phy: mediatek: phy-mtk-hdmi: Register PHY provided regulatorAngeloGioacchino Del Regno
At least version 2 of the HDMI PHY, found in MediaTek MT8195 and MT8188 SoCs, does provide hardware support to switch on/off the HDMI 5V pins (which are also used for DDC), and this translates to this being a fixed regulator. Register this PHY-provided regulator so that it can be fed to the hdmi-connector driver to manage the HDMI +5V PWR rail. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20241120124143.132637-1-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04phy: rockchip: naneng-combphy: fix phy resetChukun Pan
Currently, the USB port via combophy on the RK3528/RK3588 SoC is broken. usb usb8-port1: Cannot enable. Maybe the USB cable is bad? This is due to the combphy of RK3528/RK3588 SoC has multiple resets, but only "phy resets" need assert and deassert, "apb resets" don't need. So change the driver to only match the phy resets, which is also what the vendor kernel does. Fixes: 7160820d742a ("phy: rockchip: add naneng combo phy for RK3568") Cc: FUKAUMI Naoki <naoki@radxa.com> Cc: Michael Zimmermann <sigmaepsilon92@gmail.com> Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: FUKAUMI Naoki <naoki@radxa.com> Link: https://lore.kernel.org/r/20241122073006.99309-2-amadeus@jmu.edu.cn Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04phy: usb: Toggle the PHY power during initJustin Chen
When bringing up the PHY, it might be in a bad state if left powered. One case is we lose the PLL lock if the PLL is gated while the PHY is powered. Toggle the PHY power so we can start from a known state. Fixes: 4e5b9c9a73b3 ("phy: usb: Add support for new Synopsys USB controller on the 7216") Signed-off-by: Justin Chen <justin.chen@broadcom.com> Acked-by: Florian Fainelli <florian.fainelli@broadcom.com> Link: https://lore.kernel.org/r/20241024213540.1059412-1-justin.chen@broadcom.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04phy: marvell: Fix spelling mistake "exlicitly" -> "explicitly"Advait Dhamorikar
Fix spelling mistake in mvebu_comphy_ethernet_init_reset comments. Signed-off-by: Advait Dhamorikar <advaitdhamorikar@gmail.com> Link: https://lore.kernel.org/r/20241127104333.18944-1-advaitdhamorikar@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04phy: tegra194: p2u: Allow to enable driver on Tegra234Lars-Peter Clausen
Commit de6026682569 ("phy: tegra: Add PCIe PIPE2UPHY support for Tegra234") add support for Tegra234 to the tegra194-p2u PHY driver. But the driver is currently not selectable when Tegra234 SoC support is enabled. Update the Kconfig entry to allow the driver to be built when support the Tegra234 SoC is enabled. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Link: https://lore.kernel.org/r/20241201002519.3468-1-lars@metafoo.de Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-04phy: qcom: qmp: Add phy register and clk setting for QCS615 PCIeKrishna chaitanya chundru
Add support for GEN3 x1 PCIe PHY found on Qualcomm QCS615 platform. Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241122023314.1616353-3-quic_ziyuzhan@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
generated by cgit (git 2.34.1) at 2025-07-16 13:42:32 +0000