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path: root/drivers/soc/bcm/brcmstb
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2017-10-03soc: brcmstb: Add Product ID and Family ID helper functionsAl Cooper
Add Product ID and Family ID helper functions for brcmstb soc. Signed-off-by: Al Cooper <alcooperx@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2017-09-25soc bcm: brcmstb: Add support for S2/S3/S5 suspend states (MIPS)Justin Chen
This commit adds support for the Broadcom STB S2/S3/S5 suspend states on MIPS based SoCs. This requires quite a lot of code in order to deal with the different HW blocks that need to be quiesced during suspend: - DDR PHY - DDR memory controller and arbiter - control processor The final steps of the suspend execute in cache and there is is a little bit of assembly code in order to shut down the DDR PHY PLL and then go into a wait loop until a wake-up even occurs. Conversely the resume part involves waiting for the DDR PHY PLL to come back up and resume executions where we left. Signed-off-by: Justin Chen <justinpopo6@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2017-09-25soc: bcm: brcmstb: Add support for S2/S3/S5 suspend states (ARM)Brian Norris
This commit adds support for the Broadcom STB S2/S3/S5 suspend states on ARM based SoCs. This requires quite a lot of code in order to deal with the different HW blocks that need to be quiesced during suspend: - DDR PHY SHIM - DDR memory controller and sequencer - control processor The final steps of the suspend execute in an on-chip SRAM and there is a little bit of assembly code in order to shut down the DDR PHY PLL and then go into a wfi loop until a wake-up even occurs. Conversely the resume part involves waiting for the DDR PHY PLL to come back up and resume executions where we left. For S3, because of our memory hashing (actual hashing code not included for simplicity, and is bypassed) we need to relocate the writable variables (stack) into SRAM shortly before suspending in order to leave the DRAM untouched and create a reliable hash of its contents. This code has been contributed by Brian Norris initially and has been incrementally fixed and updated to support new chips by a lot of people. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Markus Mayer <mmayer@broadcom.com> Signed-off-by: Justin Chen <justinpopo6@gmail.com> Signed-off-by: Gareth Powell <gpowell@broadcom.com> Signed-off-by: Doug Berger <opendmb@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2017-05-13soc: bcm: brcmstb: Correctly match 7435 SoCFlorian Fainelli
Remove the duplicate brcm,bcm7425-sun-top-ctrl compatible string and replace it with brcm,bcm7435-sun-top-ctrl which was intended. Fixes: bd0faf08dc7f ("soc: bcm: brcmstb: Match additional compatible strings") Reported-by: Andreas Oberritter <obi@saftware.de> Acked-by: Gregory Fong <gregory.0xf0@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2017-03-05soc: bcm: brcmstb: Match additional compatible stringsFlorian Fainelli
Match all known sun-top-ctrl compatible strings from our MIPS chips counterparts. This allows us to properly report the SoC information to user-space through our SoC driver. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-06-07soc: brcmstb: fix warning from missing includeBen Dooks
The brcmstb_biuctrl_init() is defined in the soc specific header file, but wasn't included in the driver file. Fix the following warning by including <linux/soc/brcmstb/brcmstb.h> in the driver: drivers/soc/brcmstb/biuctrl.c:101:13: warning: symbol 'brcmstb_biuctrl_init' was not declared. Should it be static? Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-05-31soc: Move brcmstb to bcm/brcmstbFlorian Fainelli
Unify the different Broadcom SoCs directory and have everybody live under drivers/soc/bcm/*. Acked-by: Scott Branden <scott.branden@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>