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2024-09-03soc: fsl: qe: Add resource-managed muram allocatorsHerve Codina
Introduce devm_cpm_muram_alloc() and devm_cpm_muram_alloc_fixed(), the resource-managed version of cpm_muram_alloc and cpm_muram_alloc_fixed(). These resource-managed versions simplify the user avoiding the need to call cpm_muram_free(). Indeed, the allocated area returned by these functions will be automatically freed on driver detach. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-33-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: qmc: Introduce qmc_versionHerve Codina
Current code handles the CPM1 version of QMC. In order to prepare the support for the QUICC Engine (QE) version of QMC, introduce qmc_version to identify versions. This will enable the code to make the distinction between several QMC implementations. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-32-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: qmc: Rename SCC_GSMRL_MODE_QMCHerve Codina
Current code handles CPM1 version of QMC. Even if GSMRL is specific to the CPM1 version, the exact same purpose and format register (GUMRL) is present in the QUICC Engine (QE) version of QMC. Compared to the QE version, the values defined for the mode bitfield are different and the 0x0A value defined for the QMC mode is CPM1 specific. In order to prepare the support for the QE version, rename this bitfield value to clearly identify it as CPM1 specific. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-31-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: qmc: Handle RPACK initializationHerve Codina
Current code handles the CPM1 version of QMC, RPACK does not need to be initialized. This is not the case in the QUICC Engine (QE) version. In preparation of the support for QE, initialize the RPACK register when the receiver is initialized and each time it is restarted. This additional RPACK initialization has no impact in the CPM1 version of QMC. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-30-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: qmc: Rename qmc_chan_command()Herve Codina
Current code handles CPM1 version of QMC and qmc_chan_command() is clearly CPM1 specific. In order to prepare the support for the QUICC Engine (QE) version, rename qmc_chan_command() to reflect that point. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-29-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: qmc: Introduce qmc_{init,exit}_xcc() and their CPM1 versionHerve Codina
Current code handles the CPM1 version of QMC and initialize the QMC used SCC. The QUICC Engine (QE) version uses an UCC (Unified Communication Controllers) instead of the SCC (Serial Communication Controllers) used in the CPM1 version. These controllers serve the same purpose and are used in the same way but their inializations are slightly different. In order to prepare the support for QE version of QMC, introduce qmc_init_xcc() to initialize theses controllers (UCC in QE and SCC in CPM1) and isolate the CPM1 specific SCC initialization in a specific function. Also introduce qmc_exit_xcc() for consistency to revert operations done in qmc_init_xcc(). Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-28-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: qmc: Introduce qmc_init_resource() and its CPM1 versionHerve Codina
Current code handles the CPM1 version of QMC. Resources initialisations (i.e. retrieving base addresses and offsets of different parts) will be slightly different in the QUICC Engine (QE) version. Indeed, in QE version, some resources need to be allocated and are no more "staticaly" defined. In order to prepare the support for QE version, introduce qmc_init_resource() to initialize those resources and isolate the CPM1 specific operations in a specific function. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-27-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: qmc: Re-order probe() operationsHerve Codina
Current code handles CPM1 version of QMC. In the QUICC Engine (QE) version, some operations done at probe() need to be done in a different order. In order to prepare the support for the QE version, changed the sequence of operation done at probe(): - Retrieve the tsa_serial earlier, before initializing resources. - Group SCC initialisation and do this initialization when it is really needed in the probe() sequence. Having the QE compatible sequence in the CPM1 version does not lead to any issue and works correctly without any regressions. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-26-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: qmc: Introduce qmc_data structureHerve Codina
Current code handles CPM1 version of QMC. Some hardcoded values are used several times to initialize the QMC state machine. In the QUICC Engine (QE) version of QMC, these values are different. In order to prepare the support for the QE version of QMC and avoid the copy of the hardcoded values, introduce the qmc_data structure to define these version specific values. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-25-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: qmc: Add missing spinlock commentHerve Codina
checkpatch.pl raises the following issue CHECK: spinlock_t definition without comment Add the missing comments. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-23-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: qmc: Fix 'transmiter' typoHerve Codina
checkpatch.pl raises the following issue CHECK: 'transmiter' may be misspelled - perhaps 'transmitter'? Indeed, fix it. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-22-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: qmc: Remove unneeded parenthesisHerve Codina
checkpatch.pl raises the following issue in several places CHECK: Unnecessary parenthesis around ... Remove them. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-21-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: qmc: Fix blank line and spacesHerve Codina
checkpatch.pl raises the following issues CHECK: Please don't use multiple blank lines CHECK: Alignment should match open parenthesis Fix them. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-20-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: qmc: Use BIT(), GENMASK() and FIELD_PREP() macrosHerve Codina
checkpatch.pl signals the following improvement for qmc.c CHECK: Prefer using the BIT macro Follow its suggestion and convert the code to BIT() and related macros. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-19-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: qmc: Rename QMC_TSA_MASKHerve Codina
QMC_TSA_MASK is a bitfield. The value defined is a specific value of this bitfield and correspond to the use of 8bit resolution for the routing entry. Be accurate and rename the defined constant to reflect this point. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-18-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: tsa: Introduce tsa_serial_get_num()Herve Codina
TSA consumers in CPM1 implementation don't need to know about the serial device number used by the TSA component. In QUICC Engine implementation, this information is needed. Improve the TSA API with tsa_serial_get_num() in order to provide this information. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-17-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: tsa: Add support for QUICC Engine (QE) implementationHerve Codina
Add support for the time slot assigner (TSA) available in some PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321. The QE TSA is similar to the CPM1 TSA except that it uses UCCs (Unified Communication Controllers) instead of SCCs (Serial Communication Controllers). Also, compared against the CPM1 TSA, this QE TSA can handle up to 4 TDMs instead of 2 and allows to configure the logic level of sync signals. At a lower level, compared against CPM TSA implementation, some registers are slightly different even if same features are present. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-15-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: tsa: Introduce tsa_versionHerve Codina
Current code handles CPM1 version of TSA. In order to prepare the support for the QUICC Engine (QE) version of TSA, introduce tsa_version to identify versions. This will enable the code to make the distinction between several TSA implementations. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-14-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: tsa: Isolate specific CPM1 part from tsa_serial_{dis}connect()Herve Codina
Current code handles the CPM1 version of TSA. Connecting and disconnecting the SCC to/from the TSA consists in handling SICR register which is CPM1 specific. The connection and disconnection operation in the QUICC Engine (QE) version are slightly different. In order to prepare the support for the QE version, clearly identify SICR register as specific to CPM1 and isolate its handling done in connect and disconnect functions. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-13-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: tsa: Introduce tsa_setup() and its CPM1 compatible versionHerve Codina
Current code handles the CPM1 version of TSA. Setting up TSA consists in handling SIMODE and SIGMR registers. These registers are CPM1 specific. Setting up the QUICC Engine (QE) version of TSA is slightly different. In order to prepare the support for QE version, clearly identify these registers as CPM1 compatible and isolate their handling in a CPM1 specific function. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-12-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: tsa: Make SIRAM entries specific to CPM1Herve Codina
Current code handles the CPM1 version of TSA. Compared against QUICC Engine (QE) version of TSA, CPM1 SIRAM entries are slightly different. In order to prepare the support for the QE version, clearly identify these entries and functions handling them as CPM1 compatible. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-11-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: tsa: Use ARRAY_SIZE() instead of hardcoded integer valuesHerve Codina
Loops handling the tdm array use hardcoded size and the initialization part uses hardcoded indexes to initialize the array. Use ARRAY_SIZE() to avoid the hardcoded size and initialize the array using a loop. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-10-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: tsa: Remove unused registers offset definitionHerve Codina
SISTR, SICMR and SIRP registers offset definitions are not used. In order to avoid unneeded code, remove them. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-9-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: tsa: Add missing spinlock commentHerve Codina
checkpatch.pl raises the following issue CHECK: spinlock_t definition without comment Add the missing comment. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-7-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: tsa: Fix blank line and spacesHerve Codina
checkpatch.pl raises the following issues CHECK: Please don't use multiple blank lines CHECK: spaces preferred around that '/' (ctx:VxV) CHECK: spaces preferred around that '+' (ctx:VxV) CHECK: spaces preferred around that '-' (ctx:VxV) Fix them. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-6-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: tsa: Use BIT(), GENMASK() and FIELD_PREP() macrosHerve Codina
checkpatch.pl signals the following improvement for tsa.c CHECK: Prefer using the BIT macro Follow its suggestion and convert the code to BIT() and related macros. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-5-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: tsa: Fix tsa_write8()Herve Codina
The tsa_write8() parameter is an u32 value. This is not consistent with the function itself. Indeed, tsa_write8() writes an 8bits value. Be consistent and use an u8 parameter value. Fixes: 1d4ba0b81c1c ("soc: fsl: cpm1: Add support for TSA") Cc: stable@vger.kernel.org Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-4-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: qmc: Enable TRNSYNC only when neededHerve Codina
The TRNSYNC feature is enabled whatever the number of time-slots used. The feature is needed only when more than one time-slot is used. Improve the driver enabling TRNSYNC only when it is needed. Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-3-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-03soc: fsl: cpm1: qmc: Update TRNSYNC only in transparent modeHerve Codina
The TRNSYNC feature is available (and enabled) only in transparent mode. Since commit 7cc9bda9c163 ("soc: fsl: cpm1: qmc: Handle timeslot entries at channel start() and stop()") TRNSYNC register is updated in transparent and hdlc mode. In hdlc mode, the address of the TRNSYNC register is used by the QMC for other internal purpose. Even if no weird results were observed in hdlc mode, touching this register in this mode is wrong. Update TRNSYNC only in transparent mode. Fixes: 7cc9bda9c163 ("soc: fsl: cpm1: qmc: Handle timeslot entries at channel start() and stop()") Cc: stable@vger.kernel.org Signed-off-by: Herve Codina <herve.codina@bootlin.com> Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> Link: https://lore.kernel.org/r/20240808071132.149251-2-herve.codina@bootlin.com Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
2024-09-02Merge tag 'tegra-for-6.12-soc' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers soc/tegra: Changes for v6.12-rc1 This is a single patch that simplifies code a little by employing the new scoped OF helpers. * tag 'tegra-for-6.12-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: pmc: Simplify with scoped for each OF child loop Link: https://lore.kernel.org/r/20240830141004.3195210-1-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-09-02Merge tag 'versatile-soc-for-v6.12' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into soc/drivers Some long due cleanups and modernizations of the Versatile SoC drivers from Krzysztof: - Put OF handle - Use devres to avoid memory leaks - Enable compile testing * tag 'versatile-soc-for-v6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: soc: versatile: enable compile testing soc: versatile: realview: fix soc_dev leak during device remove soc: versatile: realview: fix memory leak during device remove soc: versatile: integrator: fix OF node leak in probe() error path Link: https://lore.kernel.org/r/CACRpkda244rFHnnXPDPOhmKiJsRP08tNCcfFzpH5zR2cx1DFpw@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-09-02Merge tag 'v6.12-rockchip-drivers-1' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/drivers rk3308 io-domains, and some default settings for bits in the general register files for rk3128 and the new rk3576 soc. * tag 'v6.12-rockchip-drivers-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: soc: rockchip: grf: Add rk3576 default GRF values dt-bindings: soc: rockchip: Add rk3576 syscon compatibles soc: rockchip: grf: Set RK3128's vpu main clock soc: rockchip: io-domain: Add RK3308 IO voltage domains dt-bindings: power: rockchip: Document RK3308 IO voltage domains Link: https://lore.kernel.org/r/23316481.ssLaC8jLEa@diego Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-08-30soc: versatile: enable compile testingKrzysztof Kozlowski
Enable compile testing for broader build coverage. None of the drivers use anything from "asm", so code should build everywhere. CONFIG_PLAT_VERSATILE is being selected by driver dependencies (CONFIG_ARCH_INTEGRATOR and CONFIG_ARCH_REALVIEW), so directory can be always added to Makefile targets without impacting other configurations. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/20240825-soc-dev-fixes-v1-4-ff4b35abed83@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-08-30soc: versatile: realview: fix soc_dev leak during device removeKrzysztof Kozlowski
If device is unbound, the soc_dev should be unregistered to prevent memory leak. Fixes: a2974c9c1f83 ("soc: add driver for the ARM RealView") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/20240825-soc-dev-fixes-v1-3-ff4b35abed83@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-08-30soc: versatile: realview: fix memory leak during device removeKrzysztof Kozlowski
If device is unbound, the memory allocated for soc_dev_attr should be freed to prevent leaks. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/20240825-soc-dev-fixes-v1-2-ff4b35abed83@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-08-30soc: versatile: integrator: fix OF node leak in probe() error pathKrzysztof Kozlowski
Driver is leaking OF node reference obtained from of_find_matching_node(). Fixes: f956a785a282 ("soc: move SoC driver for the ARM Integrator") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/20240825-soc-dev-fixes-v1-1-ff4b35abed83@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-08-29soc/tegra: pmc: Simplify with scoped for each OF child loopJinjie Ruan
Use scoped for_each_child_of_node_scoped() when iterating over device nodes to make code a bit simpler. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2024-08-28Merge tag 'qcom-drivers-fixes-for-6.11' of ↵Arnd Bergmann
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes Qualcomm driver fixes for v6.11 This corrects the tzmem virt-to-phys conversion, which caused issues for the uefisecapp implementation of EFI variable access. SDM670 is excluded from tzmem usage due to reported issues. The SCM get wait queue context call is corrected to be marked ATOMIC and some dead code in qseecom, following the tzmem conversion, is removed. The memory backing command DB is remapped writecombined, to avoid XPU violations when Linux runs without the Qualcomm hypervisor. Two compile fixes are added for pd-mapper, and the broken reference count is corrected, to make pd-mapper deal with remoteprocs going away. In pmic_glink a race condition where the client callbacks might be called before we returned the client handle is corrected. The broken conditions for when to signal that the firmware is going down is also corrected. In the pmic_glink UCSI driver, the ucsi_unregister() is moved out of the pdr callback, as this is being invoked in atomic context. Konrad's email address is updated in MAINTAINERS, and related mailmap entries are added. * tag 'qcom-drivers-fixes-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: soc: qcom: pd-mapper: Fix singleton refcount firmware: qcom: tzmem: disable sdm670 platform soc: qcom: pmic_glink: Actually communicate when remote goes down usb: typec: ucsi: Move unregister out of atomic section soc: qcom: pmic_glink: Fix race during initialization firmware: qcom: qseecom: remove unused functions firmware: qcom: tzmem: fix virtual-to-physical address conversion firmware: qcom: scm: Mark get_wq_ctx() as atomic call MAINTAINERS: Update Konrad Dybcio's email address mailmap: Add an entry for Konrad Dybcio soc: qcom: pd-mapper: mark qcom_pdm_domains as __maybe_unused soc: qcom: cmd-db: Map shared memory as WC, not WB soc: qcom: pd-mapper: Depend on ARCH_QCOM || COMPILE_TEST Link: https://lore.kernel.org/r/20240826145209.1646159-1-andersson@kernel.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-08-28soc: ti: pm33xx: do device_node auto cleanupKousik Sanagavarapu
Use scope based cleanup instead of manual of_node_put() calls, hence simplifying the handling of error paths. Suggested-by: Julia Lawall <julia.lawall@inria.fr> Signed-off-by: Kousik Sanagavarapu <five231003@gmail.com> Link: https://lore.kernel.org/r/20240825085714.10736-5-five231003@gmail.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-08-28soc: ti: knav_qmss_queue: do device_node auto cleanupKousik Sanagavarapu
Use scope based cleanup, instead of manual of_node_put() calls, which automatically free()s "struct device_node". While at it, refactor the code from knav_queue_probe() into the separate functions to make auto cleanup look more neat. Doing the cleanup this way has the advantage of reducing the chance of memory leaks in case we need to read from new OF nodes in the future when we probe. Suggested-by: Julia Lawall <julia.lawall@inria.fr> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Kousik Sanagavarapu <five231003@gmail.com> Link: https://lore.kernel.org/r/20240825085714.10736-4-five231003@gmail.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-08-28soc: ti: pruss: do device_node auto cleanupKousik Sanagavarapu
Use scope based cleanup instead of manual of_node_put() calls, hence simplifying the handling of error paths at various places. While at it, use dev_err_probe() instead of dev_err() in all the code paths touched. Suggested-by: Julia Lawall <julia.lawall@inria.fr> Signed-off-by: Kousik Sanagavarapu <five231003@gmail.com> Link: https://lore.kernel.org/r/20240825085714.10736-3-five231003@gmail.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-08-28soc: ti: pruss: factor out memories setupKousik Sanagavarapu
Factor out memories setup code from probe() into a new function pruss_of_setup_memories(). This sets the stage for introducing auto cleanup of the device node (done in the subsequent patch), since the clean up depends on the scope of the pointer and factoring out code into a separate function obviously limits the scope of the various variables used in that function. Apart from the above, this change also has the advantage of making the code look more neat. While at it, use dev_err_probe() instead of plain dev_err() as this new function is called by the probe(). Signed-off-by: Kousik Sanagavarapu <five231003@gmail.com> Link: https://lore.kernel.org/r/20240825085714.10736-2-five231003@gmail.com Signed-off-by: Nishanth Menon <nm@ti.com>
2024-08-23soc: rockchip: grf: Add rk3576 default GRF valuesDetlev Casanova
Set SW controlled i3c weak pull up and disable JTAG function on SDMMC IO. The i3c weak pull up is activated to let all gpio banks be controlled by the pinctrl driver. Disabling the JTAG function lets the SDMMC core use its full IO width. Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Acked-by: Dragan Simic <dsimic@manjaro.org> Link: https://lore.kernel.org/r/20240822195706.920567-3-detlev.casanova@collabora.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-23soc: rockchip: grf: Set RK3128's vpu main clockAlex Bee
RK3128 has a setting in GRF which selects whether the vpu attached iommu uses the AXI clock of the decoder (vdpu) or the encoder (vepu). The default is vepu but some part of the vendor firmware sets it to vdpu. In order to be independent on whether any of those vendor firmware blobs is used to boot the SoC reset "vpu main clock" setting to it's default value. Signed-off-by: Alex Bee <knaerzche@gmail.com> Link: https://lore.kernel.org/r/20240523185633.71355-3-knaerzche@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-23soc: rockchip: io-domain: Add RK3308 IO voltage domainsDavid Wu
Add IO voltage domains support for the RK3308 SoC. Signed-off-by: David Wu <david.wu@rock-chips.com> Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Link: https://lore.kernel.org/r/20240521211029.1236094-11-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2024-08-21soc: qcom: pd-mapper: Fix singleton refcountBjorn Andersson
The Qualcomm pd-mapper is a refcounted singleton, but the refcount is never incremented, which means the as soon as any remoteproc instance stops the count will hit 0. At this point the pd-mapper QMI service is stopped, leaving firmware without access to the PD information. Stopping any other remoteproc instances will result in a use-after-free, which best case manifest itself as a refcount underflow: refcount_t: underflow; use-after-free. WARNING: CPU: 1 PID: 354 at lib/refcount.c:87 refcount_dec_and_mutex_lock+0xc4/0x148 ... Call trace: refcount_dec_and_mutex_lock+0xc4/0x148 qcom_pdm_remove+0x40/0x118 [qcom_pd_mapper] ... Fix this by incrementing the refcount, so that the pd-mapper is only torn down when the last remoteproc stops, as intended. Fixes: 1ebcde047c54 ("soc: qcom: add pd-mapper implementation") Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240820-pd-mapper-refcount-fix-v1-1-03ea65c0309b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-21soc: qcom: pmic_glink: Actually communicate when remote goes downBjorn Andersson
When the pmic_glink state is UP and we either receive a protection- domain (PD) notification indicating that the PD is going down, or that the whole remoteproc is going down, it's expected that the pmic_glink client instances are notified that their function has gone DOWN. This is not what the code does, which results in the client state either not updating, or being wrong in many cases. So let's fix the conditions. Fixes: 58ef4ece1e41 ("soc: qcom: pmic_glink: Introduce base PMIC GLINK driver") Cc: stable@vger.kernel.org Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Amit Pundir <amit.pundir@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240820-pmic-glink-v6-11-races-v3-3-eec53c750a04@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-21usb: typec: ucsi: Move unregister out of atomic sectionBjorn Andersson
Commit '9329933699b3 ("soc: qcom: pmic_glink: Make client-lock non-sleeping")' moved the pmic_glink client list under a spinlock, as it is accessed by the rpmsg/glink callback, which in turn is invoked from IRQ context. This means that ucsi_unregister() is now called from atomic context, which isn't feasible as it's expecting a sleepable context. An effort is under way to get GLINK to invoke its callbacks in a sleepable context, but until then lets schedule the unregistration. A side effect of this is that ucsi_unregister() can now happen after the remote processor, and thereby the communication link with it, is gone. pmic_glink_send() is amended with a check to avoid the resulting NULL pointer dereference. This does however result in the user being informed about this error by the following entry in the kernel log: ucsi_glink.pmic_glink_ucsi pmic_glink.ucsi.0: failed to send UCSI write request: -5 Fixes: 9329933699b3 ("soc: qcom: pmic_glink: Make client-lock non-sleeping") Cc: stable@vger.kernel.org Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Amit Pundir <amit.pundir@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240820-pmic-glink-v6-11-races-v3-2-eec53c750a04@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-21soc: qcom: pmic_glink: Fix race during initializationBjorn Andersson
As pointed out by Stephen Boyd it is possible that during initialization of the pmic_glink child drivers, the protection-domain notifiers fires, and the associated work is scheduled, before the client registration returns and as a result the local "client" pointer has been initialized. The outcome of this is a NULL pointer dereference as the "client" pointer is blindly dereferenced. Timeline provided by Stephen: CPU0 CPU1 ---- ---- ucsi->client = NULL; devm_pmic_glink_register_client() client->pdr_notify(client->priv, pg->client_state) pmic_glink_ucsi_pdr_notify() schedule_work(&ucsi->register_work) <schedule away> pmic_glink_ucsi_register() ucsi_register() pmic_glink_ucsi_read_version() pmic_glink_ucsi_read() pmic_glink_ucsi_read() pmic_glink_send(ucsi->client) <client is NULL BAD> ucsi->client = client // Too late! This code is identical across the altmode, battery manager and usci child drivers. Resolve this by splitting the allocation of the "client" object and the registration thereof into two operations. This only happens if the protection domain registry is populated at the time of registration, which by the introduction of commit '1ebcde047c54 ("soc: qcom: add pd-mapper implementation")' became much more likely. Reported-by: Amit Pundir <amit.pundir@linaro.org> Closes: https://lore.kernel.org/all/CAMi1Hd2_a7TjA7J9ShrAbNOd_CoZ3D87twmO5t+nZxC9sX18tA@mail.gmail.com/ Reported-by: Johan Hovold <johan@kernel.org> Closes: https://lore.kernel.org/all/ZqiyLvP0gkBnuekL@hovoldconsulting.com/ Reported-by: Stephen Boyd <swboyd@chromium.org> Closes: https://lore.kernel.org/all/CAE-0n52JgfCBWiFQyQWPji8cq_rCsviBpW-m72YitgNfdaEhQg@mail.gmail.com/ Fixes: 58ef4ece1e41 ("soc: qcom: pmic_glink: Introduce base PMIC GLINK driver") Cc: stable@vger.kernel.org Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Amit Pundir <amit.pundir@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> Tested-by: Johan Hovold <johan+linaro@kernel.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240820-pmic-glink-v6-11-races-v3-1-eec53c750a04@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-20soc: amlogic: meson-gx-socinfo: add new SoCs idXianwei Zhao
Add new definition for Amlogi SoCs, include S4, C3, T7, A4, A5. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240719-soc_info-v3-2-020a3b687c0c@amlogic.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
generated by cgit (git 2.34.1) at 2025-07-18 20:37:41 +0000