summaryrefslogtreecommitdiff
path: root/drivers/spi
AgeCommit message (Collapse)Author
2025-05-19spi: sh-msiof: SITMDR1/SIRMDR1 bitfield conversionGeert Uytterhoeven
Convert MSIOF Transmit and Receive Mode Register 1 field accesses to use the FIELD_PREP() bitfield access macro. This gets rid of explicit shifts. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/9685c54e752b8ef4256c9b281e9d8292e71d222e.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Make words/fs unsigned in FIFO helpersGeert Uytterhoeven
Make the words and fs parameters of the various FIFO filler and emptier functions unsigned, as they can never be negative. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/a7b13ecb1811148227ec8c883079085ed1ea6eac.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Make words/bits unsigned in sh_msiof_spi_txrx_once()Geert Uytterhoeven
Make the words and bits parameters of sh_msiof_spi_txrx_once() unsigned, as that matches what is passed by the caller. This allows us to replace min_t() by the safer min(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/30eff1052642a4bcb0f1bc4bed7aae25d355a7dc.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Use bool for boolean flagsGeert Uytterhoeven
Use bools instead of integers for boolean flags, which allows us to remove the "!!" idiom from several expressions. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/35cd51bdfb3c810911a5be757e0ce5bb29dcc755.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Complete using dev in sh_msiof_spi_probe()Geert Uytterhoeven
Commit c4887bd4b35b225f ("spi: sh-msiof: use dev in sh_msiof_spi_probe()") forgot to convert one instance. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Link: https://patch.msgid.link/88d271b2d16c6ad7f174858894573f91cec1bc90.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Fix maximum DMA transfer sizeGeert Uytterhoeven
The maximum amount of data to transfer in a single DMA request is calculated from the FIFO sizes (which is technically not 100% correct, but a simplification, as it is limited by the maximum word count values in the Transmit and Control Data Registers). However, in case there is both data to transmit and to receive, the transmit limit is overwritten by the receive limit. Fix this by using the minimum applicable FIFO size instead. Move the calculation outside the loop, so it is not repeated for each individual DMA transfer. As currently tx_fifo_size is always equal to rx_fifo_size, this bug had no real impact. Fixes: fe78d0b7691c0274 ("spi: sh-msiof: Fix FIFO size to 64 word from 256 word") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/d9961767a97758b2614f2ee8afe1bd56dc900a60.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Remove unneeded compatible valuesGeert Uytterhoeven
The Clock-Synchronized Serial Interfaces with FIFO (MSIOF) driver matches against both SoC-specific and family-specific compatible values to maintain backwards-compatibility with old DTBs predating the introduction of the family-specific compatible values. For RZ/G1, the SoC-specific compatible match entry can be removed from the driver: their DT always had the family-specific compatible values, and thus there was never a need to add the SoC-specific compatible values to the driver. For R-Car Gen2 and M3-W, the SoC-specific compatible match entries can be removed, too, as there are a few points in time where DT backwards-compatibility was broken for other reasons: - Legacy DT clock support is no longer supported since commit 58256143cff7c2e0 ("clk: renesas: Remove R-Car Gen2 legacy DT clock support") in v5.5, and the addition of "renesas,rcar-gen2-msiof" to DTS in v4.11 predates the completion of the clock conversion in v4.15, - Legacy DT LVDS support is no longer supported since commit 841281fe52a769fe ("drm: rcar-du: Drop LVDS device tree backward compatibility") in v5.18, and the addition of "renesas,rcar-gen3-msiof" in commit 8b51f97138ca22b6 ("arm64: dts: r8a7796: Use R-Car Gen 3 fallback binding for msiof nodes") in v4.11 predates the LVDS conversion in commit 58e8ed2ee9abe718 ("arm64: dts: renesas: Convert to new LVDS DT bindings") in v4.20. For R-Car H3, the SoC-specific compatible match entry cannot be removed, as its purpose is to handle an SoC-specific quirk. Suggested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/d33393ac7536bc3f0f624b079f70d80dd19843db.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-19spi: sh-msiof: Drop comma after OF match table sentinelGeert Uytterhoeven
It does not make sense to have a comma after a sentinel, as any new elements must be added before the sentinel. Add a comment to clarify the purpose of the empty element. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/2ab5745407339ba54b63c3e6410082c7c566bf95.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16spi: spi-qpic-snand: extend FIELD_PREP() macro usageGabor Juhos
Large part of the code uses the FIELD_PREP() macro already to construct values to be written to hardware registers. Change the code to use also the macro for more registers of which the corresponding bitmasks are defined already. This makes the code more readable. It also syncs the affected codes with their counterparts in the 'qcom_nandc' driver, so it makes it easier to spot the differences between the two implementations. No functional changes intended. Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Reviewed-by: Md Sadre Alam <quic_mdalam@quicinc.com> Link: https://patch.msgid.link/20250515-qpic-snand-use-bitmasks-v1-2-11729aeae73b@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-16spi: spi-qpic-snand: use CW_PER_PAGE_MASK bitmaskGabor Juhos
Change the code to use the already defined CW_PER_PAGE_MASK bitmask along with the FIELD_PREP() macro instead of using magic values. This makes the code more readable. It also syncs the affected codes with their counterparts in the 'qcom_nandc' driver, so it makes it easier to spot the differences between the two implementations. No functional changes intended. Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Reviewed-by: Md Sadre Alam <quic_mdalam@quicinc.com> Link: https://patch.msgid.link/20250515-qpic-snand-use-bitmasks-v1-1-11729aeae73b@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-15spi: tegra210-quad: Add support for internal DMAVishwaroop A
Add support for internal DMA in Tegra234 devices. Tegra234 has an internal DMA controller, while Tegra241 continues to use an external DMA controller (GPCDMA). This patch adds support for both internal and external DMA controllers. Signed-off-by: Vishwaroop A <va@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Link: https://patch.msgid.link/20250513200043.608292-2-va@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-14spi: spi-qpic-snand: validate user/chip specific ECC propertiesGabor Juhos
The driver only supports 512 bytes ECC step size and 4 bit ECC strength at the moment, however it does not reject unsupported step/strength configurations. Due to this, whenever the driver is used with a flash chip which needs stronger ECC protection, the following warning is shown in the kernel log: [ 0.574648] spi-nand spi0.0: GigaDevice SPI NAND was found. [ 0.635748] spi-nand spi0.0: 256 MiB, block size: 128 KiB, page size: 2048, OOB size: 128 [ 0.649079] nand: WARNING: (null): the ECC used on your system is too weak compared to the one required by the NAND chip Although the message indicates that something is wrong, but it often gets unnoticed, which can cause serious problems. For example when the user writes something into the flash chip despite the warning, the written data may won't be readable by the bootloader or by the boot ROM. In the worst case, when the attached SPI NAND chip is the boot device, the board may not be able to boot anymore. Also, it is not even possible to create a backup of the flash, because reading its content results in bogus data. For example, dumping the first page of the flash gives this: # hexdump -C -n 2048 /dev/mtd0 00000000 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f |................| * 00000040 0f 0f 0f 0f 0f 0f 0f 0d 0f 0f 0f 0f 0f 0f 0f 0f |................| 00000050 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f |................| * 000001c0 0f 0f 0f 0f ff 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f |................| 000001d0 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f |................| * 00000200 0f 0f 0f 0f f5 5b ff ff 0f 0f 0f 0f 0f 0f 0f 0f |.....[..........| 00000210 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f |................| * 000002f0 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 1f 0f 0f |................| 00000300 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f |................| * 000003c0 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f ff 0f 0f 0f |................| 000003d0 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f |................| * 00000400 0f 0f 0f 0f 0f 0f 0f 0f e9 74 c9 06 f5 5b ff ff |.........t...[..| 00000410 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f |................| * 000005d0 0f 0f 0f 0f ff 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f |................| 000005e0 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f |................| * 00000600 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f c6 be 0f c3 |................| 00000610 e9 74 c9 06 f5 5b ff ff 0f 0f 0f 0f 0f 0f 0f 0f |.t...[..........| 00000620 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f |................| * 00000770 0f 0f 0f 0f 8f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f |................| 00000780 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f |................| * 00000800 # Doing the same by using the downstream kernel results in different output: # hexdump -C -n 2048 /dev/mtd0 00000000 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f 0f |................| * 00000800 # This patch adds some sanity checks to the code to prevent using the driver with unsupported ECC step/strength configurations. After the change, probing of the driver fails in such cases: [ 0.655038] spi-nand spi0.0: GigaDevice SPI NAND was found. [ 0.659159] spi-nand spi0.0: 256 MiB, block size: 128 KiB, page size: 2048, OOB size: 128 [ 0.669138] qcom_snand 79b0000.spi: only 4 bits ECC strength is supported [ 0.677476] nand: No suitable ECC configuration [ 0.689909] spi-nand spi0.0: probe with driver spi-nand failed with error -95 This helps to avoid the aforementioned hassles until support for 8 bit ECC strength gets implemented. Fixes: 7304d1909080 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Link: https://patch.msgid.link/20250501-qpic-snand-validate-ecc-v1-1-532776581a66@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-14spi: spi-sun4i: fix early activationAlessandro Grassi
The SPI interface is activated before the CPOL setting is applied. In that moment, the clock idles high and CS goes low. After a short delay, CPOL and other settings are applied, which may cause the clock to change state and idle low. This transition is not part of a clock cycle, and it can confuse the receiving device. To prevent this unexpected transition, activate the interface while CPOL and the other settings are being applied. Signed-off-by: Alessandro Grassi <alessandro.grassi@mailbox.org> Link: https://patch.msgid.link/20250502095520.13825-1-alessandro.grassi@mailbox.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-12Add more devm_ functions to fix PM imbalance inMark Brown
Merge series from Bence Csókás <csokas.bence@prolan.hu>: The probe() function of the atmel-quadspi driver got quite convoluted, especially since the addition of SAMA7G5 support, that was forward-ported from an older vendor kernel. During the port, a bug was introduced, where the PM get() and put() calls were imbalanced. To alleivate this - and similar problems in the future - an effort was made to migrate as many functions as possible, to their devm_ managed counterparts. The few functions, which did not yet have a devm_ variant, are added in patch 1 of this series. Patch 2 then uses these APIs to fix the probe() function.
2025-05-11spi: atmel-quadspi: Fix unbalanced pm_runtime by using devm_ APIBence Csókás
Fix unbalanced PM in error path of `atmel_qspi_probe()` by using `devm_pm_runtime_*()` functions. Reported-by: Alexander Dahl <ada@thorsis.com> Closes: https://lore.kernel.org/linux-spi/20250110-paycheck-irregular-bcddab1276c7@thorsis.com/ Fixes: 5af42209a4d2 ("spi: atmel-quadspi: Add support for sama7g5 QSPI") Signed-off-by: Bence Csókás <csokas.bence@prolan.hu> Link: https://patch.msgid.link/20250327195928.680771-4-csokas.bence@prolan.hu Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-09Add RZ/G3E xSPI supportMark Brown
Merge series from Biju Das <biju.das.jz@bp.renesas.com>: The xSPI IP found on RZ/G3E SoC similar to RPC-IF interface, but it can support writes on memory-mapped area. Even though the registers are different, the rpcif driver code can be reused for xSPI by adding wrapper functions.
2025-05-08spi: rpc-if: Add write support for memory-mapped areaBiju Das
Add write support for memory-mapped area as xSPI interface require it. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20250424090000.136804-8-biju.das.jz@bp.renesas.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-08spi: tegra114: Use value to check for invalid delaysAaron Kling
A delay unit of 0 is a valid entry, thus it is not valid to check for unused delays. Instead, check the value field; if that is zero, the given delay is unset. Fixes: 4426e6b4ecf6 ("spi: tegra114: Don't fail set_cs_timing when delays are zero") Cc: stable@vger.kernel.org Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Link: https://patch.msgid.link/20250506-spi-tegra114-fixup-v1-1-136dc2f732f3@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-07This patch set did some clean up and add runtime pmMark Brown
Merge series from Haibo Chen <haibo.chen@nxp.com>: PATCH1/3/4 to clean up the code, make the code more readable PATCH2 add the runtime pm support PATCH5 use devm_add_action_or_reset() to replace remove() callback, this can avoid oops when do bind/unbind test
2025-05-06spi: nxp-fspi: use devm instead of remove for driver detachHan Xu
fspi driver use devm APIs to manage clk/irq/resources and register the spi controller, but the legacy remove function will be called first during device detach and trigger kernel panic. Drop the remove function and use devm_add_action_or_reset() for driver cleanup to ensure the release sequence. Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Link: https://patch.msgid.link/20250428-flexspipatch-v3-5-61d5e8f591bc@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-06spi: spi-nxp-fspi: remove the unchecked return value for ↵Haibo Chen
nxp_fspi_clk_disable_unprep For nxp_fspi_clk_disable_unprep(), no caller check the return value, so remove the unchecked return value. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Link: https://patch.msgid.link/20250428-flexspipatch-v3-4-61d5e8f591bc@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-06spi: spi-nxp-fspi: use guard(mutex) to simplify the codeHaibo Chen
Use guard(mutex) to simplify the code logic. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Link: https://patch.msgid.link/20250428-flexspipatch-v3-3-61d5e8f591bc@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-06spi: spi-nxp-fspi: enable runtime pm for fspiHaibo Chen
Enable the runtime PM in fspi driver. Also for system PM, On some board like i.MX8ULP-EVK board, after system suspend, IOMUX module will lost power, so all the pinctrl setting will lost when system resume back, need driver to save/restore the pinctrl setting. Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Link: https://patch.msgid.link/20250428-flexspipatch-v3-2-61d5e8f591bc@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-06spi: spi-nxp-fspi: remove the goto in probeHaibo Chen
Remove all the goto in probe to simplify the driver. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Link: https://patch.msgid.link/20250428-flexspipatch-v3-1-61d5e8f591bc@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-06AsoC: Phase out hybrid PCI devresMark Brown
Merge series from Philipp Stanner <phasta@kernel.org>: A year ago we spent quite some work trying to get PCI into better shape. Some pci_ functions can be sometimes managed with devres, which is obviously bad. We want to provide an obvious API, where pci_ functions are never, and pcim_ functions are always managed. Thus, everyone enabling his device with pcim_enable_device() must be ported to pcim_ functions. Porting all users will later enable us to significantly simplify parts of the PCI subsystem. See here [1] for details. This patch series does that for sound. Feel free to squash the commits as you see fit. P. [1] https://elixir.bootlin.com/linux/v6.14-rc4/source/drivers/pci/devres.c#L18
2025-05-05spi: cadence-quadspi: Assume device could match via platformKrzysztof Kozlowski
Driver has only of_device_id table, however it also has MODULE_ALIAS() for platform name, thus assume there is a configuration where this can be loaded outside of OF system. In such case of_device_get_match_data() will return NULL, which is already checked in one place of probe() function but not in the other, leading to Smatch warning: drivers/spi/spi-cadence-quadspi.c:1942 cqspi_probe() error: we previously assumed 'ddata' could be null (see line 1885) Driver should be consistent, so assume device can be matched via platform bus and of_device_get_match_data() can indeed return NULL. This is also possible with malformed DTS on OF-platform: no unit address and device node name matching driver name. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250501-n-smatch-fixes-v2-3-d2ad9c1f2e67@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-05spi: cs42l43: Make handling missing spk-id GPIOs explicitKrzysztof Kozlowski
gpiod_get_array_optional() for spk-id GPIOs can return NULL, if they are missing, so do not pass the value to PTR_ERR but instead explicitly treat NULL as acceptable condition. The old code was correct, but misleading because PTR_ERR usually is used on errors. Reported by Smatch: drivers/spi/spi-cs42l43.c:241 cs42l43_get_speaker_id_gpios() warn: passing zero to 'PTR_ERR' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com> Link: https://patch.msgid.link/20250501-n-smatch-fixes-v2-2-d2ad9c1f2e67@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-05spi: atmel-quadspi: Fix printed error code during DMA setupKrzysztof Kozlowski
On dma_request_chan() failure driver NULL-ifies the 'rx_chan' and immediately uses it as PTR_ERR() so dev_err_probe() prints incorrect error code. Rework the code so proper error code will be printed and NULL-ifying of 'rx_chan' will happen in common error handling block (failure of DMA setup is not fatal for the driver and further code depends on 'rx_chan' being non-NULL for DMA operations). Reported by Smatch: drivers/spi/atmel-quadspi.c:1287 atmel_qspi_dma_init() warn: passing zero to 'PTR_ERR' Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20250501-n-smatch-fixes-v2-1-d2ad9c1f2e67@linaro.org Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-05spi: loopback-test: Do not split 1024-byte hexdumpsGeert Uytterhoeven
spi_test_print_hex_dump() prints buffers holding less than 1024 bytes in full. Larger buffers are truncated: only the first 512 and the last 512 bytes are printed, separated by a truncation message. The latter is confusing in case the buffer holds exactly 1024 bytes, as all data is printed anyway. Fix this by printing buffers holding up to and including 1024 bytes in full. Fixes: 84e0c4e5e2c4ef42 ("spi: add loopback test driver to allow for spi_master regression tests") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/37ee1bc90c6554c9347040adabf04188c8f704aa.1746184171.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-02Merge tag 'spi-fix-v6.15-rc4' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi Pull spi fixes from Mark Brown: "A fairly small pile of fixes, plus one new compatible string addition to the Synopsis driver for a new platform. The most notable thing is the fix for divide by zeros in spi-mem if an operation has no dummy bytes" * tag 'spi-fix-v6.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: tegra114: Don't fail set_cs_timing when delays are zero spi: spi-qpic-snand: fix NAND_READ_LOCATION_2 register handling spi: spi-mem: Add fix to avoid divide error spi: dt-bindings: snps,dw-apb-ssi: Add compatible for SOPHGO SG2042 SoC spi: dt-bindings: snps,dw-apb-ssi: Merge duplicate compatible entry spi: spi-qpic-snand: propagate errors from qcom_spi_block_erase() spi: stm32-ospi: Fix an error handling path in stm32_ospi_probe()
2025-05-03spi: loopback-test: Simplify strange loopback value checkGeert Uytterhoeven
Apply De Morgan's Theorem and drop superfluous parentheses to simplify the check for strange loopback values. While at it, add the missing zero in the related comment. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/da612090f543c8c7cc99fb9dc6ef4abc9560abe4.1746184293.git.geert+renesas@glider.be Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-02spi: tegra114: Don't fail set_cs_timing when delays are zeroAaron Kling
The original code would skip null delay pointers, but when the pointers were converted to point within the spi_device struct, the check was not updated to skip delays of zero. Hence all spi devices that didn't set delays would fail to probe. Fixes: 04e6bb0d6bb1 ("spi: modify set_cs_timing parameter") Cc: stable@vger.kernel.org Signed-off-by: Aaron Kling <webgeek1234@gmail.com> Link: https://patch.msgid.link/20250423-spi-tegra114-v1-1-2d608bcc12f9@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-05-01ASoC: codec: twl4030: Convert to GPIO descriptorsMark Brown
Merge series from "Peng Fan (OSS)" <peng.fan@oss.nxp.com>: This is separated from [1]. With an update that sorting the headers in a separate patch. No other changes, so I still keep Linus' R-b for Patch 2. [1] https://lore.kernel.org/all/20250408-asoc-gpio-v1-3-c0db9d3fd6e9@nxp.com/
2025-04-30spi: axi-spi-engine: offload instruction optimizationMark Brown
Merge series from David Lechner <dlechner@baylibre.com>: In order to achieve a 4 MSPS rate on a 16-bit ADC with a 80 MHz SCLK using the SPI offload feature of the AXI SPI Engine, we need to shave off some time that is spent executing unnecessary instructions. There are a few one-time setup instructions that can be moved so that they execute only once when the SPI offload trigger is enabled rather than repeating each time the offload is triggered. Additionally, a recent change to the IP block allows dropping the SYNC instruction completely. With these changes, we are left with only the 3 instructions that are needed to to assert CS, transfer the data, and deassert CS. This makes 3 + 16 * 12.5 ns = 237.5 ns < 250 ns which is comfortably within the available time period.
2025-04-30spi: axi-spi-engine: omit SYNC from offload instructionsDavid Lechner
Add optimization to omit SYNC instructions from offload messages. Starting with IP core v1.5.0, the SYNC instruction is no longer required for proper operation when using the offload feature. Omitting the SYNC instruction saves a few clock cycles needed to executed which can e.g. allow achieving higher sample rates on ADCs. Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20250428-adi-main-v1-4-4b8a1b88a212@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-30spi: axi-spi-engine: optimize bits_per_word for offloadDavid Lechner
Add an optimization to avoid repeating bits_per_word instructions in each message when using SPI offload. This only applies when all data xfers in a message have the same bits_per_word. In this case, we can execute the instruction that sets bits_per_word when the offload trigger is enabled. This is useful e.g. for obtaining higher sample rates on ADCs since each message takes less time to execute. Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20250428-adi-main-v1-3-4b8a1b88a212@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-30spi: axi-spi-engine: don't repeat mode config for offloadDavid Lechner
Add an optimization to avoid repeating the config instruction in each SPI message when using SPI offloading. Instead, the instruction is run once when the SPI offload trigger is enabled. This is done to allow higher sample rates for ADCs using this SPI controller. Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20250428-adi-main-v1-2-4b8a1b88a212@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-30spi: axi-spi-engine: wait for completion in setupDavid Lechner
Add a polling wait for SPI instruction execution to complete in the spi_engine_setup() function. In practice, these instructions complete in a few 10s of nanoseconds, so we never ran into any race conditions, but it is good practice to wait for the completion of the SPI engine instructions before returning from the setup function. Signed-off-by: David Lechner <dlechner@baylibre.com> Link: https://patch.msgid.link/20250428-adi-main-v1-1-4b8a1b88a212@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-30spi: spi-qpic-snand: fix NAND_READ_LOCATION_2 register handlingGabor Juhos
The precomputed value for the NAND_READ_LOCATION_2 register should be stored in 'snandc->regs->read_location2'. Fix the qcom_spi_set_read_loc_first() function accordingly. Fixes: 7304d1909080 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Reviewed-by: Md Sadre Alam <quic_mdalam@quicinc.com> Link: https://patch.msgid.link/20250428-qpic-snand-readloc2-fix-v1-1-50ce0877ff72@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-29mtd: rawnand: qcom: Pass 18 bit offset from NANDc base to BAM baseMd Sadre Alam
The BAM command descriptor provides only 18 bits to specify the BAM register offset. Additionally, in the BAM command descriptor, the BAM register offset is supposed to be specified as "(NANDc base - BAM base) + reg_off". Since, the BAM controller expecting the value in the form of "NANDc base - BAM base", so that added a new field 'bam_offset' in the NAND properties structure and use it while preparing the command descriptor. Previously, the driver was specifying the NANDc base address in the BAM command descriptor. Cc: stable@vger.kernel.org Fixes: 8d6b6d7e135e ("mtd: nand: qcom: support for command descriptor formation") Tested-by: Lakshmi Sowjanya D <quic_laksd@quicinc.com> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Acked-by: Mark Brown <broonie@kernel.org> Tested-by: Gabor Juhos <j4g8y7@gmail.com> # on IPQ9574 Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2025-04-25Configure Clocks, Add Internal DMA supportMark Brown
Merge series from Vishwaroop A <va@nvidia.com>: This series introduces QSPI clock configuration and internal DMA support for Quad SPI controller. The patches have been reorganized for better logical flow and review comments from v2 have been addressed.
2025-04-25ASoC: add Renesas MSIOF sound driverMark Brown
Merge series from Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>: Renesas MSIOF can work as both SPI and I2S. Current Linux supports MSIOF-SPI. This patch-set adds new MSIOF-I2S. Because it is using same HW-IP, we want to share same compatible for both MSIOF-SPI/I2S case. MSIOF-I2S (Sound) will use Audio-Graph-Card/Card2 which uses Of-Graph, but MSIOF-SPI is not use Of-Graph. So, this patch-set assumes it was used as MSIOF-I2S if DT is using Of-Graph, otherwise, it is MSIOF-SPI (This assumption will works if SPI *never* use Of-Graph in the future). One note so far is that it is using "spi@xxx" node name for both MSIOF-SPI/I2S. DTC will automatically checks "spi@xxx" node as SPI device which requests #address-cells/#size-cells. But is not needed for I2S. So we will get warning about it on Sparrow Hawk which uses MSIOF-I2S. We have no solution about it, so far. Link: https://lore.kernel.org/r/87zfgi1a5a.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/87h62vh5mj.wl-kuninori.morimoto.gx@renesas.com Link: https://lore.kernel.org/r/875xjeb0wu.wl-kuninori.morimoto.gx@renesas.com
2025-04-25spi: spi-qpic-snand: remove unused 'wlen' member of 'struct qpic_spi_nand'Gabor Juhos
The 'wlen' member of the qpic_spi_nand structure is never used in the code so remove that. Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> Link: https://patch.msgid.link/20250424-qpic-snand-remove-wlen-v1-1-2a7467ce2e3a@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-25spi: spi-mem: Add fix to avoid divide errorRaju Rangoju
For some SPI flash memory operations, dummy bytes are not mandatory. For example, in Winbond SPINAND flash memory devices, the `write_cache` and `update_cache` operation variants have zero dummy bytes. Calculating the duration for SPI memory operations with zero dummy bytes causes a divide error when `ncycles` is calculated in the spi_mem_calc_op_duration(). Add changes to skip the 'ncylcles' calculation for zero dummy bytes. Following divide error is fixed by this change: Oops: divide error: 0000 [#1] PREEMPT SMP NOPTI ... ? do_trap+0xdb/0x100 ? do_error_trap+0x75/0xb0 ? spi_mem_calc_op_duration+0x56/0xb0 ? exc_divide_error+0x3b/0x70 ? spi_mem_calc_op_duration+0x56/0xb0 ? asm_exc_divide_error+0x1b/0x20 ? spi_mem_calc_op_duration+0x56/0xb0 ? spinand_select_op_variant+0xee/0x190 [spinand] spinand_match_and_init+0x13e/0x1a0 [spinand] spinand_manufacturer_match+0x6e/0xa0 [spinand] spinand_probe+0x357/0x7f0 [spinand] ? kernfs_activate+0x87/0xd0 spi_mem_probe+0x7a/0xb0 spi_probe+0x7d/0x130 Fixes: 226d6cb3cb79 ("spi: spi-mem: Estimate the time taken by operations") Suggested-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Akshata MukundShetty <akshata.mukundshetty@amd.com> Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com> Link: https://patch.msgid.link/20250424121333.417372-1-Raju.Rangoju@amd.com Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-24spi: meson-spicc: add DMA supportXianwei Zhao
Add DMA support for spicc driver. DMA works if the transfer meets the following conditions: 1. 64 bits per word; 2. The transfer length must be multiples of the dma_burst_len, and the dma_burst_len should be one of 8,7...2, otherwise, it will be split into several SPI bursts. Signed-off-by: Sunny Luo <sunny.luo@amlogic.com> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://patch.msgid.link/20250414-spi-dma-v2-1-84bbd92fa469@amlogic.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-24spi: tegra210-quad: Update dummy sequence configurationVishwaroop A
Adding support for the dummy sequence configuration. The dummy sequence introduces a delay between the command and the data phases of a transfer. This delay, measured in clock cycles, allows the slave device to prepare for data transmission, ensuring data integrity and proper synchronization. Signed-off-by: Vishwaroop A <va@nvidia.com> Link: https://patch.msgid.link/20250416110606.2737315-6-va@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-24spi: tegra210-quad: modify chip select (CS) deactivationVishwaroop A
Modify the chip select (CS) deactivation and inter-transfer delay execution only during the DATA_TRANSFER phase when the cs_change flag is not set. This ensures proper CS handling and timing between transfers while eliminating redundant operations. Fixes: 1b8342cc4a38 ("spi: tegra210-quad: combined sequence mode") Signed-off-by: Vishwaroop A <va@nvidia.com> Link: https://patch.msgid.link/20250416110606.2737315-4-va@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-24spi: tegra210-quad: remove redundant error handling codeVishwaroop A
Remove unnecessary error handling code that terminated transfers and executed delay on errors. This code was redundant as error handling is already done at a higher level in the SPI core. Fixes: 1b8342cc4a38 ("spi: tegra210-quad: combined sequence mode") Signed-off-by: Vishwaroop A <va@nvidia.com> Link: https://patch.msgid.link/20250416110606.2737315-3-va@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-24spi: tegra210-quad: Fix X1_X2_X4 encoding and support x4 transfersVishwaroop A
This patch corrects the QSPI_COMMAND_X1_X2_X4 and QSPI_ADDRESS_X1_X2_X4 macros to properly encode the bus width for x1, x2, and x4 transfers. Although these macros were previously incorrect, they were not being used in the driver, so no functionality was affected. The patch updates tegra_qspi_cmd_config() and tegra_qspi_addr_config() function calls to use the actual bus width from the transfer, instead of hardcoding it to 0 (which implied x1 mode). This change enables proper support for x1, x2, and x4 data transfers by correctly configuring the interface width for commands and addresses. These modifications improve the QSPI driver's flexibility and prepare it for future use cases that may require different bus widths for commands and addresses. Fixes: 1b8342cc4a38 ("spi: tegra210-quad: combined sequence mode") Signed-off-by: Vishwaroop A <va@nvidia.com> Link: https://patch.msgid.link/20250416110606.2737315-2-va@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-04-24spi: intel: Improve resource mappingHeiner Kallweit
Let's use the pci/platform-specialized functions for mapping a resource, and pass the mapped address to intel_spi_probe. Benefits are: - No separate call needed for getting the resource, and no access to struct pci_dev internals (pdev->resource[]). - More user-friendly output in /proc/iomem. In my case: before 80704000-80704fff : 0000:00:1f.5 80704000-80704fff : 0000:00:1f.5 0000:00:1f.5 after 80704000-80704fff : 0000:00:1f.5 80704000-80704fff : spi_intel_pci Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Link: https://patch.msgid.link/2585fa05-60c4-48c4-a838-e87014665ae2@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
generated by cgit (git 2.34.1) at 2025-07-15 10:33:21 +0000