From aac8aa7717a23a9bf8740dbfb59755b1d62f04bf Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Tue, 14 Jun 2005 17:35:03 +0000 Subject: Enable a suitable ISA for the assembler around ll/sc so that code builds even for processors that don't support the instructions. Plus minor formatting fixes. Signed-off-by: Ralf Baechle --- arch/mips/kernel/semaphore.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'arch/mips/kernel/semaphore.c') diff --git a/arch/mips/kernel/semaphore.c b/arch/mips/kernel/semaphore.c index 9c40fe5a8e8d..dbb145ee00a7 100644 --- a/arch/mips/kernel/semaphore.c +++ b/arch/mips/kernel/semaphore.c @@ -42,24 +42,28 @@ static inline int __sem_update_count(struct semaphore *sem, int incr) if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( - "1: ll %0, %2 \n" + " .set mips2 \n" + "1: ll %0, %2 # __sem_update_count \n" " sra %1, %0, 31 \n" " not %1 \n" " and %1, %0, %1 \n" - " add %1, %1, %3 \n" + " addu %1, %1, %3 \n" " sc %1, %2 \n" " beqzl %1, 1b \n" + " .set mips0 \n" : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count) : "r" (incr), "m" (sem->count)); } else if (cpu_has_llsc) { __asm__ __volatile__( - "1: ll %0, %2 \n" + " .set mips2 \n" + "1: ll %0, %2 # __sem_update_count \n" " sra %1, %0, 31 \n" " not %1 \n" " and %1, %0, %1 \n" - " add %1, %1, %3 \n" + " addu %1, %1, %3 \n" " sc %1, %2 \n" " beqz %1, 1b \n" + " .set mips0 \n" : "=&r" (old_count), "=&r" (tmp), "=m" (sem->count) : "r" (incr), "m" (sem->count)); } else { -- cgit From c4559f67b73d6c34fde0faac5c6c890a2cf3527c Mon Sep 17 00:00:00 2001 From: "Maciej W. Rozycki" Date: Thu, 23 Jun 2005 15:57:15 +0000 Subject: Always use ".set mips3" rather than select between "mips2" or "mips3" for assembling ll/sc sequences to avoid problems with 64-bit configurations. Signed-off-by: Ralf Baechle --- arch/mips/kernel/semaphore.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/mips/kernel/semaphore.c') diff --git a/arch/mips/kernel/semaphore.c b/arch/mips/kernel/semaphore.c index dbb145ee00a7..1265358cdca1 100644 --- a/arch/mips/kernel/semaphore.c +++ b/arch/mips/kernel/semaphore.c @@ -42,7 +42,7 @@ static inline int __sem_update_count(struct semaphore *sem, int incr) if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( - " .set mips2 \n" + " .set mips3 \n" "1: ll %0, %2 # __sem_update_count \n" " sra %1, %0, 31 \n" " not %1 \n" @@ -55,7 +55,7 @@ static inline int __sem_update_count(struct semaphore *sem, int incr) : "r" (incr), "m" (sem->count)); } else if (cpu_has_llsc) { __asm__ __volatile__( - " .set mips2 \n" + " .set mips3 \n" "1: ll %0, %2 # __sem_update_count \n" " sra %1, %0, 31 \n" " not %1 \n" -- cgit