From 9287d95ea194abf32fab24c6909f8ea55ab0292f Mon Sep 17 00:00:00 2001 From: Hirokazu Takata Date: Fri, 6 Jan 2006 00:18:41 -0800 Subject: [PATCH] m32r: Support M32104UT target platform This patch is for supporting a new target platform, Renesas M32104UT evaluation board. The M32104UT is an eval board based on an uT-Engine specification. This board has an MMU-less M32R family processor, M32104. http://www-wa0.personal-media.co.jp/pmc/archive/te/te_m32104_e.pdf This board is one of the most popular M32R platform, so we have ported Linux/M32R to it. Signed-off-by: Naoto Sugai Signed-off-by: Hirokazu Takata Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/asm-m32r/system.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'include/asm-m32r/system.h') diff --git a/include/asm-m32r/system.h b/include/asm-m32r/system.h index 5eee832b73a0..dcf619a0a0b0 100644 --- a/include/asm-m32r/system.h +++ b/include/asm-m32r/system.h @@ -69,12 +69,12 @@ } while(0) /* Interrupt Control */ -#if !defined(CONFIG_CHIP_M32102) +#if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104) #define local_irq_enable() \ __asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory") #define local_irq_disable() \ __asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory") -#else /* CONFIG_CHIP_M32102 */ +#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ static inline void local_irq_enable(void) { unsigned long tmpreg; @@ -96,7 +96,7 @@ static inline void local_irq_disable(void) "mvtc %0, psw \n\t" : "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory"); } -#endif /* CONFIG_CHIP_M32102 */ +#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ #define local_save_flags(x) \ __asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */) @@ -105,13 +105,13 @@ static inline void local_irq_disable(void) __asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \ : "r" (x) : "cbit", "memory") -#if !defined(CONFIG_CHIP_M32102) +#if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104)) #define local_irq_save(x) \ __asm__ __volatile__( \ "mvfc %0, psw; \n\t" \ "clrpsw #0x40 -> nop; \n\t" \ : "=r" (x) : /* no input */ : "memory") -#else /* CONFIG_CHIP_M32102 */ +#else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ #define local_irq_save(x) \ ({ \ unsigned long tmpreg; \ @@ -124,7 +124,7 @@ static inline void local_irq_disable(void) : "=r" (x), "=&r" (tmpreg) \ : : "cbit", "memory"); \ }) -#endif /* CONFIG_CHIP_M32102 */ +#endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ #define irqs_disabled() \ ({ \ -- cgit From 4dc7a0bbeb6882ad665e588e82fabe5bb4645f2f Mon Sep 17 00:00:00 2001 From: Ingo Molnar Date: Thu, 12 Jan 2006 01:05:27 -0800 Subject: [PATCH] sched: add cacheflush() asm Add per-arch sched_cacheflush() which is a write-back cacheflush used by the migration-cost calibration code at bootup time. Signed-off-by: Ingo Molnar Cc: Nick Piggin Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- include/asm-m32r/system.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include/asm-m32r/system.h') diff --git a/include/asm-m32r/system.h b/include/asm-m32r/system.h index dcf619a0a0b0..06c12a037cba 100644 --- a/include/asm-m32r/system.h +++ b/include/asm-m32r/system.h @@ -68,6 +68,16 @@ last = __last; \ } while(0) +/* + * On SMP systems, when the scheduler does migration-cost autodetection, + * it needs a way to flush as much of the CPU's caches as possible. + * + * TODO: fill this in! + */ +static inline void sched_cacheflush(void) +{ +} + /* Interrupt Control */ #if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104) #define local_irq_enable() \ -- cgit