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authorRussell King <rmk+kernel@armlinux.org.uk>2020-07-08 11:44:36 +0100
committerRussell King (Oracle) <rmk+kernel@armlinux.org.uk>2021-07-02 16:36:16 +0100
commit12edc8b11b076d92df15fa2f52bb4966e87a1e5e (patch)
treeaf813c8cf4fcfbd66014ef3b0805ccafe35809fe
parent71be330fe62b8867384c9c4dc821b5f72dff307f (diff)
net: mvneta: move 1ms clock control into mac_prepare/mac_finish
Move the 1ms clock control out of mac_config() into mac_prepare() and mac_finish(), which simplifies the mac_config() code. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
-rw-r--r--drivers/net/ethernet/marvell/mvneta.c27
1 files changed, 16 insertions, 11 deletions
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index 471bd4cefc5e..6afbd790ac24 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -3946,6 +3946,14 @@ static int mvneta_mac_prepare(struct phylink_config *config, unsigned int mode,
if (pp->phy_interface != interface)
WARN_ON(phy_power_off(pp->comphy));
+ /* Enable the 1ms clock */
+ if (phylink_autoneg_inband(mode)) {
+ unsigned long rate = clk_get_rate(pp->clk);
+
+ mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER,
+ MVNETA_GMAC_1MS_CLOCK_ENABLE | (rate / 1000));
+ }
+
return 0;
}
@@ -3957,14 +3965,12 @@ static void mvneta_mac_config(struct phylink_config *config, unsigned int mode,
u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4);
- u32 new_clk, gmac_clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
u32 new_an, gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
new_ctrl0 = gmac_ctrl0 & ~MVNETA_GMAC0_PORT_1000BASE_X;
new_ctrl2 = gmac_ctrl2 & ~(MVNETA_GMAC2_INBAND_AN_ENABLE |
MVNETA_GMAC2_PORT_RESET);
new_ctrl4 = gmac_ctrl4 & ~(MVNETA_GMAC4_SHORT_PREAMBLE_ENABLE);
- new_clk = gmac_clk & ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
new_an = gmac_an & ~(MVNETA_GMAC_INBAND_AN_ENABLE |
MVNETA_GMAC_INBAND_RESTART_AN |
MVNETA_GMAC_AN_SPEED_EN |
@@ -3992,7 +3998,6 @@ static void mvneta_mac_config(struct phylink_config *config, unsigned int mode,
} else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
/* SGMII mode receives the state from the PHY */
new_ctrl2 |= MVNETA_GMAC2_INBAND_AN_ENABLE;
- new_clk = MVNETA_GMAC_1MS_CLOCK_ENABLE;
new_an = (new_an & ~(MVNETA_GMAC_CONFIG_MII_SPEED |
MVNETA_GMAC_CONFIG_GMII_SPEED |
MVNETA_GMAC_CONFIG_FULL_DUPLEX)) |
@@ -4002,7 +4007,6 @@ static void mvneta_mac_config(struct phylink_config *config, unsigned int mode,
} else {
/* 802.3z negotiation - only 1000base-X */
new_ctrl0 |= MVNETA_GMAC0_PORT_1000BASE_X;
- new_clk = MVNETA_GMAC_1MS_CLOCK_ENABLE;
new_an = (new_an & ~MVNETA_GMAC_CONFIG_MII_SPEED) |
MVNETA_GMAC_INBAND_AN_ENABLE |
MVNETA_GMAC_CONFIG_GMII_SPEED |
@@ -4013,10 +4017,6 @@ static void mvneta_mac_config(struct phylink_config *config, unsigned int mode,
new_an |= MVNETA_GMAC_AN_FLOW_CTRL_EN;
}
- /* Set the 1ms clock divisor */
- if (new_clk == MVNETA_GMAC_1MS_CLOCK_ENABLE)
- new_clk |= clk_get_rate(pp->clk) / 1000;
-
/* When at 2.5G, the link partner can send frames with shortened
* preambles.
*/
@@ -4029,8 +4029,6 @@ static void mvneta_mac_config(struct phylink_config *config, unsigned int mode,
mvreg_write(pp, MVNETA_GMAC_CTRL_2, new_ctrl2);
if (new_ctrl4 != gmac_ctrl4)
mvreg_write(pp, MVNETA_GMAC_CTRL_4, new_ctrl4);
- if (new_clk != gmac_clk)
- mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, new_clk);
if (new_an != gmac_an)
mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, new_an);
@@ -4046,7 +4044,14 @@ static int mvneta_mac_finish(struct phylink_config *config, unsigned int mode,
{
struct net_device *ndev = to_net_dev(config->dev);
struct mvneta_port *pp = netdev_priv(ndev);
- u32 val;
+ u32 val, clk;
+
+ /* Disable 1ms clock if not in in-band mode */
+ if (!phylink_autoneg_inband(mode)) {
+ clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
+ clk &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE;
+ mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, clk);
+ }
if (pp->phy_interface != interface)
/* Enable the Serdes PHY */