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authorScott Tsai <scottt@scottt.tw>2017-09-20 02:16:00 +0800
committerPaul E. McKenney <paulmck@linux.vnet.ibm.com>2017-10-20 11:09:32 -0700
commitd92f842bb30f52beedad63a4a850b39ca0dbc45f (patch)
tree03d81db6292daff1a2932584b6fc0f3234327394
parent0902b1f44a72558aece92f074154044861681f84 (diff)
memory-barriers.txt: Fix typo in pairing example
In the "general barrier pairing with implicit control depdendency" example, the last write by CPU 1 was meant to change variable x and not y. The example would be pretty uninteresting if no CPU ever changes x and the variable was initialized to zero. Signed-off-by: Scott Tsai <scottt@scottt.tw> Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
-rw-r--r--Documentation/memory-barriers.txt2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index 7deee1441640..f37375544d71 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -947,7 +947,7 @@ Or even:
=============== ===============================
r1 = READ_ONCE(y);
<general barrier>
- WRITE_ONCE(y, 1); if (r2 = READ_ONCE(x)) {
+ WRITE_ONCE(x, 1); if (r2 = READ_ONCE(x)) {
<implicit control dependency>
WRITE_ONCE(y, 1);
}