path: root/Documentation/atomic_t.txt
diff options
authorAlan Stern <>2019-05-03 13:13:44 -0400
committerPaul E. McKenney <>2019-06-19 09:31:53 -0700
commit2966f8d440c3d2b6ef6c44093a9f9c42701a077a (patch)
tree00e538245c0fb16d6bab0d69d7f2d0c418f6d47c /Documentation/atomic_t.txt
parent0031e38adf38779acce5737f4905b9f60750b674 (diff)
Documentation: atomic_t.txt: Explain ordering provided by smp_mb__{before,after}_atomic()
The description of smp_mb__before_atomic() and smp_mb__after_atomic() in Documentation/atomic_t.txt is slightly terse and misleading. It does not clearly state which other instructions are ordered by these barriers. This improves the text to make the actual ordering implications clear, and also to explain how these barriers differ from a RELEASE or ACQUIRE ordering. Signed-off-by: Alan Stern <> Cc: Jonathan Corbet <> Cc: Peter Zijlstra <> Acked-by: Andrea Parri <> Signed-off-by: Paul E. McKenney <>
Diffstat (limited to 'Documentation/atomic_t.txt')
1 files changed, 13 insertions, 4 deletions
diff --git a/Documentation/atomic_t.txt b/Documentation/atomic_t.txt
index dca3fb0554db..b3afe69d03a1 100644
--- a/Documentation/atomic_t.txt
+++ b/Documentation/atomic_t.txt
@@ -187,8 +187,14 @@ The barriers:
-only apply to the RMW ops and can be used to augment/upgrade the ordering
-inherent to the used atomic op. These barriers provide a full smp_mb().
+only apply to the RMW atomic ops and can be used to augment/upgrade the
+ordering inherent to the op. These barriers act almost like a full smp_mb():
+smp_mb__before_atomic() orders all earlier accesses against the RMW op
+itself and all accesses following it, and smp_mb__after_atomic() orders all
+later accesses against the RMW op and all accesses preceding it. However,
+accesses between the smp_mb__{before,after}_atomic() and the RMW op are not
+ordered, so it is advisable to place the barrier right next to the RMW atomic
+op whenever possible.
These helper barriers exist because architectures have varying implicit
ordering on their SMP atomic primitives. For example our TSO architectures
@@ -212,7 +218,9 @@ Further, while something like:
is a 'typical' RELEASE pattern, the barrier is strictly stronger than
-a RELEASE. Similarly for something like:
+a RELEASE because it orders preceding instructions against both the read
+and write parts of the atomic_dec(), and against all following instructions
+as well. Similarly, something like:
@@ -244,7 +252,8 @@ strictly stronger than ACQUIRE. As illustrated:
This should not happen; but a hypothetical atomic_inc_acquire() --
(void)atomic_fetch_inc_acquire() for instance -- would allow the outcome,
-since then:
+because it would not order the W part of the RMW against the following
P1 P2