path: root/Documentation/hwmon
diff options
authorKun Yi <>2020-12-11 13:54:26 -0800
committerGuenter Roeck <>2020-12-12 08:34:29 -0800
commit6ec3fcf556fe44542934b778aea1b725b0793418 (patch)
tree1488e0b8280df21a32a9e52ef2f3c7c38fb75949 /Documentation/hwmon
parente7bb1a2ab8c4b1569f5b271fd87ca203b1e673a5 (diff)
hwmon: (sbtsi) Add documentation
Document the SB-TSI sensor interface driver. Signed-off-by: Kun Yi <> Link: [groeck: Added SPDX license identifier, same as source] Signed-off-by: Guenter Roeck <>
Diffstat (limited to 'Documentation/hwmon')
2 files changed, 43 insertions, 0 deletions
diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst
index 7e5104c8f477..fcb870ce6286 100644
--- a/Documentation/hwmon/index.rst
+++ b/Documentation/hwmon/index.rst
@@ -154,6 +154,7 @@ Hardware Monitoring Kernel Drivers
+ sbtsi_temp
diff --git a/Documentation/hwmon/sbtsi_temp.rst b/Documentation/hwmon/sbtsi_temp.rst
new file mode 100644
index 000000000000..922b3c8db666
--- /dev/null
+++ b/Documentation/hwmon/sbtsi_temp.rst
@@ -0,0 +1,42 @@
+.. SPDX-License-Identifier: GPL-2.0-or-later
+Kernel driver sbtsi_temp
+Supported hardware:
+ * Sideband interface (SBI) Temperature Sensor Interface (SB-TSI)
+ compliant AMD SoC temperature device.
+ Prefix: 'sbtsi_temp'
+ Addresses scanned: This driver doesn't support address scanning.
+ To instantiate this driver on an AMD CPU with SB-TSI
+ support, the i2c bus number would be the bus connected from the board
+ management controller (BMC) to the CPU. The i2c address is specified in
+ Section 6.3.1 of the SoC register reference: The SB-TSI address is normally
+ 98h for socket 0 and 90h for socket 1, but it could vary based on hardware
+ address select pins.
+ Datasheet: The SB-TSI interface and protocol is available as part of
+ the open source SoC register reference at:
+ The Advanced Platform Management Link (APML) Specification is
+ available at:
+Author: Kun Yi <>
+The SBI temperature sensor interface (SB-TSI) is an emulation of the software
+and physical interface of a typical 8-pin remote temperature sensor (RTS) on
+AMD SoCs. It implements one temperature sensor with readings and limit
+registers encode the temperature in increments of 0.125 from 0 to 255.875.
+Limits can be set through the writable thresholds, and if reached will trigger
+corresponding alert signals.