path: root/Documentation/index.rst
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authorPaul Cercueil <>2019-07-24 13:16:04 -0400
committerPaul Burton <>2019-08-08 15:30:05 -0700
commit97689a1a3fdad101d41488f9da0b1d99aa0b6aa2 (patch)
treeae9793f71621bd8ceaa1e8dd67d3cb8f2a0461fb /Documentation/index.rst
parent4bc3c420246e70088c1d09f7bc30ab5583fbd5f9 (diff)
doc: Add doc for the Ingenic TCU hardware
Add documentation about the Timer/Counter Unit (TCU) present in the Ingenic JZ47xx SoCs. The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function hardware block. It features up to to eight channels, that can be used as counters, timers, or PWM. - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all have eight channels. - JZ4725B introduced a separate channel, called Operating System Timer (OST). It is a 32-bit programmable timer. On JZ4770 and above, it is 64-bit. - Each one of the TCU channels has its own clock, which can be reparented to three different clocks (pclk, ext, rtc), gated, and reclocked, through their TCSR register. * The watchdog and OST hardware blocks also feature a TCSR register with the same format in their register space. * The TCU registers used to gate/ungate can also gate/ungate the watchdog and OST clocks. - Each TCU channel works in one of two modes: * mode TCU1: channels cannot work in sleep mode, but are easier to operate. * mode TCU2: channels can work in sleep mode, but the operation is a bit more complicated than with TCU1 channels. - The mode of each TCU channel depends on the SoC used: * On the oldest SoCs (up to JZ4740), all of the eight channels operate in TCU1 mode. * On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1. * On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the others operate as TCU1. - Each channel can generate an interrupt. Some channels share an interrupt line, some don't, and this changes between SoC versions: * on older SoCs (JZ4740 and below), channel 0 and channel 1 have their own interrupt line; channels 2-7 share the last interrupt line. * On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one interrupt line; the OST uses the last interrupt line. * on newer SoCs (JZ4750 and above), channel 5 has its own interrupt; channels 0-4 and (if eight channels) 6-7 all share one interrupt line; the OST uses the last interrupt line. Signed-off-by: Paul Cercueil <> Tested-by: Mathieu Malaterre <> Tested-by: Artur Rojek <> Signed-off-by: Paul Burton <> Cc: Ralf Baechle <> Cc: James Hogan <> Cc: Jonathan Corbet <> Cc: Lee Jones <> Cc: Arnd Bergmann <> Cc: Daniel Lezcano <> Cc: Thomas Gleixner <> Cc: Michael Turquette <> Cc: Stephen Boyd <> Cc: Jason Cooper <> Cc: Marc Zyngier <> Cc: Rob Herring <> Cc: Mark Rutland <> Cc: Cc: Cc: Cc: Cc: Cc:
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