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authorVignesh Raghavendra <vigneshr@ti.com>2021-05-10 23:36:01 +0530
committerNishanth Menon <nm@ti.com>2021-05-14 12:47:09 -0500
commit52ae30f55a2a40cff549fac95de82f25403bd387 (patch)
tree7d94a45d8627dfb7638aced8866a52cef572974d /arch/arm64
parentdf61cd9393845383adc4ea2410f2a91e1d1972b6 (diff)
arm64: dts: ti: j7200-main: Mark Main NAVSS as dma-coherent
Traffic through main NAVSS interconnect is coherent wrt ARM caches on J7200 SoC. Add missing dma-coherent property to main_navss node. Also add dma-ranges to be consistent with mcu_navss node and with AM65/J721e main_navss and mcu_navss nodes. Fixes: d361ed88455fe ("arm64: dts: ti: Add support for J7200 SoC") Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20210510180601.19458-1-vigneshr@ti.com
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/boot/dts/ti/k3-j7200-main.dtsi2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index f86c493a44f1..a6826f1888ef 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -85,6 +85,8 @@
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
ti,sci-dev-id = <199>;
+ dma-coherent;
+ dma-ranges;
main_navss_intr: interrupt-controller1 {
compatible = "ti,sci-intr";